阅读说明：本技术 数字功率复用器 (Digital power multiplexer ) 是由 V·纳拉亚南 D·库玛 R·维兰谷迪皮查 V·宝娜帕里 于 2018-06-15 设计创作，主要内容包括：一种功率复用器包括：第一支路,包括与第二晶体管串联耦合在第一电源与功率输出之间的第一晶体管；第二支路,包括与第四晶体管串联耦合在第二电源与功率输出之间的第三晶体管；控制器,被配置为向第一支路和第二支路选择性地确立和解除确立控制信号；第一电压电平移位器,耦合在第二晶体管与控制器之间；以及第二电压电平移位器,耦合在第三晶体管与控制器之间。(A power multiplexer comprising: a first branch comprising a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch comprising a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first leg and the second leg; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.)

1. A power multiplexer, comprising:

a first branch comprising a first transistor coupled in series with a second transistor between a first power supply and a power output;

a second branch comprising a third transistor coupled in series with a fourth transistor between a second power supply and the power output;

a controller configured to selectively assert and de-assert a control signal to the first leg and the second leg;

a first voltage level shifter coupled between the second transistor and the controller; and

a second voltage level shifter coupled between the third transistor and the controller.

2. The power multiplexer of claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each comprise a respective P-type metal-oxide-semiconductor (PMOS) transistor.

3. The power multiplexer of claim 1, wherein the first power supply is operable to output a first voltage level, and wherein the second power supply is operable to output a second voltage level, and wherein the second voltage level is higher than the first voltage level.

4. The power multiplexer of claim 1, wherein the first transistor is configured to receive the control signal at a voltage level of the first power supply from the controller, and wherein the first voltage level shifter is configured to increase a voltage of the control signal to a voltage level associated with the second power supply.

5. The power multiplexer of claim 1, wherein the fourth transistor is configured to receive the control signal at a voltage level of the first power supply from the controller, and wherein the second voltage level shifter is configured to increase a voltage of the control signal to a voltage level associated with the second power supply.

6. The power multiplexer of claim 1, wherein the controller is configured to turn off the first and second transistors by asserting the control signal to the first branch, and is configured to turn on the third and fourth transistors by de-asserting the control signal to the second branch.

7. The power multiplexer of claim 1, further comprising:

a processing unit coupled to the power output and configured to receive power from the power multiplexer, wherein the processing unit is configured to provide a second control signal to the controller, further wherein the controller is configured to turn on the first branch or the second branch in response to the second control signal.

8. The power multiplexer of claim 1, wherein the power multiplexer is implemented in a system on a chip (SOC) and is configured to output a first voltage associated with the first power supply or a second voltage associated with the second power supply to a processing unit in the SOC.

9. The power multiplexer of claim 1, wherein the controller is configured to receive power from the first power supply, and wherein the control signal is at a voltage level of the first power supply.

10. The power multiplexer of claim 9, wherein the first power supply comprises an always-on power supply.

11. A method, comprising:

asserting a control signal to a first branch of a power multiplexer, the first branch comprising a first transistor and a second transistor coupled between a first power supply and a power output, wherein the control signal is applied to a gate of the first transistor and to a level shifter at a gate of the second transistor;

de-asserting the control signal to a second leg of the power multiplexer, the second leg comprising third and fourth transistors coupled between a second power supply and the power output; and

conducting current from the second power supply to the power output after de-asserting the control signal to the second branch.

12. The method of claim 11, wherein asserting the control signal causes the first and second transistors to turn off.

13. The method of claim 12, further comprising:

applying, by the level shifter, the level-shifted voltage to the gate of the second transistor.

14. The method of claim 11, wherein de-asserting the control signal causes the third and fourth transistors to turn on, thereby creating a current path from the second power supply to the power output.

15. The method of claim 11, further comprising:

shifting, by the level shifter, a voltage of the control signal to a voltage associated with the second power supply; and

applying the voltage associated with the second power supply to the gate of the second transistor.

16. The method of claim 15, wherein the gate of the first transistor is at a voltage equal to or higher than a voltage associated with the first power supply;

wherein the gate of the second transistor is at a voltage equal to or higher than a voltage associated with the second power supply; and is

Wherein the first transistor and the second transistor are off.

17. A digital power multiplexer, comprising:

means for conducting current from a first power supply, the means for conducting current from the first power supply comprising a first transistor and a second transistor coupled in series between the first power supply and a power output;

means for conducting current from a second power supply, the means for conducting current from the second power supply comprising a third transistor and a fourth transistor coupled in series between the second power supply and the power output; and

means for selecting the first power supply or the second power supply at a given time and not selecting the other of the first power supply or the second power supply at the given time, the means for selecting comprising control signal outputs to the first transistor and the fourth transistor and a control signal output to a voltage level shifter at the second transistor and the third transistor.

18. The digital power multiplexer of claim 17, wherein the first, second, third, and fourth transistors comprise respective P-type metal-oxide-semiconductor (PMOS) transistors.

19. The digital power multiplexer of claim 17, wherein the means for selecting comprises means for generating a control signal having a voltage corresponding to a voltage of the first power supply.

20. The digital power multiplexer of claim 17, wherein the voltage level shifter is configured to: shifting a voltage level associated with a control signal for the selected component to a voltage level associated with the second power supply.

21. The digital power multiplexer of claim 17, wherein the means for selecting is configured to receive power from the first power source.

22. The digital power multiplexer of claim 21, wherein the first power supply comprises an always-on power supply.

Technical Field

The present application relates generally to power multiplexers, and more particularly to digital power multiplexers.

Background

Conventional computing devices (e.g., smartphones, tablet computers, etc.) may include a system on a chip (SOC) having a processor and other operating circuitry. The SOC may receive its power from the battery, and thus conventional designs may balance SOC performance and power usage to deliver a desirable experience to the user while requiring as little battery charging as is feasible.

Some conventional SOC designs include multiple power domains that receive power from one or more power sources. Power multiplexing may be used in some conventional systems to reduce power consumption during normal operation of a computing device. For example, the power multiplexer may include a multiplexer that receives multiple (e.g., two) power inputs at its inputs and has a power output, and the power multiplexer selects between the power inputs. Further, a given SOC design may include multiple different power multiplexers to provide power to different processing units in the SOC.

One way some conventional systems may use power multiplexing to save power is to enable power collapse of portions of the processing core (using a first power multiplexer and a first power domain) while providing power to portions of the processing core that store state values (using a second power multiplexer and a second power domain). Both the first and second power multiplexers may select between the first and second power domains. Another way some conventional systems may use power multiplexing is to switch from a first power supply to a second power supply to power a Central Processing Unit (CPU) memory, and then adjust the second power supply to overdrive the CPU memory. This technique may save power by allowing the SOC to selectively increase the voltage at some components without increasing the voltage at other components.

Thus, a power multiplexer (or power multiplexer) may be used to switch the core between two or more power supplies, depending on the mode of operation. Conventional power multiplexers may include a mixed signal design that employs analog components (e.g., VDD comparators) to detect the higher of the two power supplies and an analog voltage generator that generates the higher of the two (or more) voltages that are switched to the internal power supply. Analog circuitry, such as comparators and voltage generators, can be complex and use an undesirably large amount of circuit space. Accordingly, there is a need in the art for a power multiplexer design that omits the analog comparator and the voltage generator.

Such conventional power multiplexers may use headswitches that each have a single transistor. Conventional power multiplexers may operate under the assumption that only one side is active at any given time, allowing switching between power domains. However, if the transistor used in one of the headswitches is not completely off, it may allow leakage between the power domains, which may be undesirable. Accordingly, there is a need in the art for a more reliable power multiplexer.

Disclosure of Invention

Various embodiments provide a digital power multiplexer having at least a first branch and a second branch, each of the first and second branches including two or more transistors. At least two of the transistors in a given branch are controlled by different voltages to turn off the transistors in the branch intended to be off. Thus, various embodiments may reduce or eliminate the possibility of undesired leakage from one power domain to another. Furthermore, various embodiments may use digital components instead of some analog components, thereby reducing complexity and circuit space.

According to one embodiment, a power multiplexer comprises: a first branch comprising a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch comprising a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first leg and the second leg; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.

According to another embodiment, a method comprises: asserting a control signal to a first branch of a power multiplexer, the first branch comprising a first transistor and a second transistor coupled between a first power supply and a power output, wherein the control signal is applied to a gate of the first transistor and to a level shifter at a gate of the second transistor; de-asserting the control signal to a second leg of the power multiplexer, the second leg including a third transistor and a fourth transistor coupled between a second power supply and the power output; and conducting current from the second power supply to the power output after de-asserting the control signal to the second branch.

According to another embodiment, a digital power multiplexer includes: means for conducting current from a first power supply, the means for conducting current from the first power supply comprising a first transistor and a second transistor coupled in series between the first power supply and a power output; means for conducting current from a second power supply, the means for conducting current from the second power supply comprising a third transistor and a fourth transistor coupled in series between the second power supply and the power output; and means for selecting the first power supply or the second power supply at a given time and not selecting the other of the first power supply or the second power supply at the given time, the means for selecting comprising control signal outputs to the first and fourth transistors and control signal outputs to the voltage level shifters at the second and third transistors.

Drawings

Fig. 1 is an illustration of an example power multiplexer, in accordance with various embodiments.

Fig. 2 is an illustration of an example internal architecture of the power multiplexer controller of fig. 1, according to one embodiment.

Fig. 3 is a diagram of the example power multiplexer of fig. 1 illustrating one leg on and one leg off, according to one embodiment.

FIG. 4 is an illustration of an example portion of a computing device using more than two power supplies, multiple processing units, and multiple power multiplexers, according to an embodiment.

Fig. 5 is an illustration of an example method for power multiplexing, according to one embodiment.

Detailed Description

Various embodiments provided herein include systems and methods for distributing power using a digital power multiplexer. The digital power multiplexer includes at least two branches, each of the branches having at least two transistors connected in series between a respective power supply and a power output. In addition, a voltage level shifter may be used at each branch at the gate of at least one of the transistors. Thus, at each branch there is at least one transistor receiving the control signal at the first voltage and another transistor receiving the level shifted control signal. In other words, the two transistors in each branch are controlled by different voltages. As explained further below, this architecture may help ensure that a given branch is turned off when another power source is used to supply current to the power output.

In one embodiment, a computer processor includes a number of integrated circuit chips (e.g., an SOC having a number of processing cores, a Power Management Integrated Circuit (PMIC), and the like). These chips are provided within a computing device, such as a smartphone. The computing device includes, among other things, a battery, a printed circuit board hosting a chip, a touch screen display, and a housing. A power supply (e.g., PMIC) converts the voltage and current from the battery to a voltage and current that can be used by other chips.

Continuing with the example, the PMIC may be coupled with the first power domain. The computer processor may also include other power domains, and these other power domains may be used to provide power at different voltages, easily collapsible power, and the like. Throughout the computer processor, there may be a plurality of power multiplexers, where each of the power multiplexers may receive power from and select between two or more power domains. For example, each processing core in a SOC may have its own power multiplexer so that the core may be power collapsed or provided with a higher or lower voltage at a given time. Indeed, any particular component may receive its power via a power multiplexer, thereby allowing the power domain to be appropriately selected and/or adjusted for a given target.

In one example, a particular power multiplexer may include a first leg for conducting current from a first power supply. The first branch may include a first transistor and a second transistor coupled in series between the first power supply and the power output. The example power multiplexer may also include a second leg to conduct current from a second power supply. The second branch may comprise two more transistors-a third transistor and a fourth transistor-coupled in series between the second power supply and the power output. In this example, the transistors include P-type metal oxide semiconductor (PMOS) transistors that can be turned off by a gate voltage that is higher than or equal to a source voltage or a drain voltage.

The power multiplexer may further include a power multiplexer controller for selecting the first power supply or the second power supply at a given time and deselecting the other power supply. The power multiplexer controller has control signal outputs to the first leg and the second leg, while allowing the power multiplexer controller to selectively assert the control signal to one of the legs and to selectively de-assert the control signal to the other of the legs.

Continuing with the example, the power multiplexer controller may turn off the first leg by asserting a control signal to the first leg, thereby deselecting the first power supply. One of the transistors of the first branch receives the control signal at a first voltage (e.g., a voltage associated with a first power supply) and another one of the transistors of the first branch receives the asserted control signal through a voltage level shifter that shifts the voltage from the first voltage to a second voltage (e.g., a voltage associated with a second power supply). In examples where the second voltage is higher than the first voltage, applying the second voltage to the gate of the second transistor helps to ensure that the second transistor is turned off, even when the source or drain in the second transistor may be at the second voltage itself.

Further, in this example, the power multiplexer controller turns on one leg or the other at a particular time. Accordingly, the power multiplexer controller may switch on the second branch, thereby selecting the second power supply. The power multiplexer controller may in this example turn on the second branch by de-asserting the control signals to the third and fourth transistors. The second power supply conducts current to the power output when the second branch is on.

The power multiplexer controller may select the first power supply by de-asserting the control signal to the first leg and asserting the control signal to the second leg. Again, one of the transistors of the second branch (e.g., the third transistor) receives the asserted control signal through the voltage level shifter, while another one of the transistors (e.g., the fourth transistor) receives the asserted control signal without level shifting. The higher voltage at the gate of the third transistor helps to ensure that the third transistor is turned off and does not allow current from the second power supply to flow. In contrast, de-assertion of the control signal to the first branch turns on the transistor of the first branch, thereby allowing current to be conducted from the first power source to the power output. In this manner, the CPU or other logic device in the chip may select a power supply at a given power multiplexer by: such that the controller asserts the control signal to one leg of the power multiplexer and de-asserts the control signal to the other leg of the power multiplexer. In another embodiment, the logic for selecting the power supply may be embedded in the power multiplexer controller itself.

Fig. 1 is a simplified diagram illustrating an example power multiplexer 100 in accordance with one embodiment. The example power multiplexer 100 includes a first branch 101, the first branch 101 having a transistor 111 and a transistor 112 coupled in series between a first power supply (VDD _ AUX) and a power output 120. Although not explicitly shown in fig. 1, power output 120 may be coupled to, for example, clock circuits, processing cores, sequential logic components within cores, and the like.

The example power multiplexer 100 also includes a second branch 102, the second branch 102 having transistors 113, 114 coupled in series between a second power supply (VDD _ DOM) and a power output 120. Further, in this example, the first power supply VDD _ AUX includes an "always on" power supply. Of course, it is possible that VDD _ AUX is turned off by, for example, removing the battery from the device. However, VDD _ AUX may include a power domain that is distributed to a plurality of different devices (not shown here) that use the power domain for consistent voltage levels and reliable access to the voltage during normal operation of the devices. In various embodiments, VDD _ AUX may provide a voltage that varies by a relatively small amount to account for temperature of operation, aging of transistors, and other phenomena. The power mux controller 130 is powered by VDD _ AUX to utilize a consistent and reliable voltage.

VDD _ DOM is another power supply in this example, and may comprise yet another "always on" power supply, or may comprise another type of power supply that may be expected to be turned on or off at various times, or may be associated with a voltage that may vary relatively widely (e.g., for power conservation or overdrive). Power multiplexer 100 allows selection between VDD _ AUX and VDD _ DOM so that one or the other of these power supplies conducts current to power output 120.

The example power multiplexer 100 also includes a power multiplexer controller 130 that can assert and de-assert the control signals En _1 and En _ 2. Further, this example, the control signals En _1 and En _2 have voltage levels corresponding to the voltage level of VDD _ AUX at least when asserted. Looking at the first branch 101, a voltage level shifter 132 is coupled between the gate of the transistor 112 and the power multiplexer controller 130. Similarly, a level shifter 134 is coupled between the gate of the transistor 113 and the controller 130. When the control signal En _1 is asserted, it has a voltage level corresponding to VDD _ AUX, such that the voltage level of VDD _ AUX is applied to the gate of the transistor 111. The voltage level shifter 132 shifts the voltage level of En _1 to a voltage level corresponding to the voltage level of VDD _ DOM, thereby applying the voltage level of VDD _ DOM to the gate of the transistor 112. This turns off the first branch 101 when the control signal En _1 is asserted. The first branch 101 may be turned on by de-asserting the control signal En _1, thereby applying 0V or other suitable low voltage to the gates of the transistors 111, 112.

When the control signal En _2 is asserted, a voltage level corresponding to the voltage level of VDD _ AUX is applied to the gate of the transistor 114. The level shifter 134 shifts the voltage of En _2 to the voltage of VDD _ DOM, thereby applying the voltage level of VDD _ DOM to the gate of the transistor 113. This turns off the second branch 102 when the control signal En _2 is asserted. De-assertion of control signal En _2 turns branch 102 on by applying a low voltage (such as 0V) to the gates of transistors 113, 114. Of course, in this particular example, at any given time, one of the control signals En _1 or En _2 will be asserted and the other will be de-asserted. For example, if En _1 is de-asserted, then En _2 will be asserted (and vice versa) to prevent a scenario where both branches 101, 102 are on at the same time. Some embodiments may also include turning off both legs 101, 102 simultaneously to de-power downstream components.

Power multiplexer controller 130 may be implemented using any suitable technology. For example, power multiplexer controller 130 may include a computer processor that operates a state machine in accordance with hardware, software, or a combination thereof. Similarly, power multiplexer controller 130 may be implemented using a combination of digital logic gates. An example combination of digital logic gates, according to one embodiment, is shown in fig. 2. In the example of fig. 2, the two and logic gates 202, 204 are combined as shown to output En _1 or En _2, depending on which branch is selected. For example, if signal select 1 corresponds to En _1, and if signal select 2 corresponds to En _2, then asserting one or the other of select 1 or select 2 will assert En _1 or En _2, respectively, and the other is deasserted. In some examples, the "select 1" signal and the "select 2" signal may be provided by a CPU or other component running a power management algorithm.

Various embodiments may scale the power multiplexer 100 appropriately. For example, although each branch 101, 102 is shown as having two transistors each, other embodiments may include three or more transistors in each branch. Similarly, each branch in fig. 1 is associated with a particular power supply, such that power multiplexer 100 as shown in fig. 1 selects between two power supply options. However, other embodiments may include more than two branches to enable selection between three or more power sources. For example, the number of control signals may be increased so that each branch may be individually turned on or off to allow a selected power supply to conduct current to the power output while branches at other power supplies are turned off.

Fig. 3 is an illustration of a use case of an example power multiplexer 100, in accordance with one embodiment. Although the multiplexer controller 130 is not shown in fig. 3, it is understood that the control signals En _1, En _2 are provided by the multiplexer controller 130. Further, although the description of fig. 3 uses particular voltage values, it is understood that various embodiments may use any suitable voltage values, and the scope of embodiments is not limited to any particular set of voltage values.

Continuing with this example, VDD _ AUX has a value of 0.75V, and VDD _ DOM has a value of 0.95V. Thus, power multiplexer controller 130 (not shown) may be powered by 0.75V, and control signals En _1, En _2 may have a voltage level of 0.75V when asserted and a voltage level of 0V when de-asserted.

The example of fig. 3 assumes that the first branch 101 is off and the second branch 102 is on, thereby selecting the power supply VDD _ DOM to conduct current to the power output 120. Since the first branch 101 is turned off, VDD _ AUX is not selected.

This applies 0.75V to the gate of transistor 111 when control signal En _1 is asserted. The level shifter 132 shifts the voltage value of the control signal En _1 to a value associated with the voltage level (0.95V) of VDD _ DOM. Thus, 0.95V is applied to the gate of the transistor 112. Note that the source or drain of transistor 112 is also at 0.95V, and thus transistor 112 is turned off because its gate is at a voltage higher than or equal to its source/drain voltage. In practice, because the gate of transistor 112 is held at a voltage equal to or higher than VDD _ DOM, this eliminates or minimizes any current flowing through transistor 112 when branch 101 is off and branch 102 is on. In embodiments where the value of VDD _ DOM may vary, the level shifters 132, 134 may output a voltage associated with the highest expected value of VDD _ DOM in order to ensure that transistor 112 (or transistor 113) is turned off when appropriate. Transistor 111 is also turned off because its gate is at a voltage higher than or equal to the voltage at its source or drain (0.75V).

Looking at branch 102, control signal En _2 is de-asserted and is at 0V in this example, which causes 0V to be applied to the gates of both transistors 113, 114. This turns on branch 102 and creates a current path from power source VDD _ DOM to power output 120.

Similarly, by de-asserting control signal En _1 and asserting control signal En _2, branch 101 may be turned on and branch 102 may be turned off. Although not shown in fig. 3, such action will result in 0V being applied at the gates of transistors 111, 112, thereby turning on branch 101. Such action would also result in 0.95V being applied at the gate of transistor 113 and 0.75V being applied at the gate of transistor 114. Since transistor 113 will have its gate at a voltage higher than or equal to the voltage of its source (0.95V), transistor 113 will be turned off and any current flowing through transistor 113 will be eliminated or minimized. Transistor 114 will also be turned off because its gate will be held at 0.75V, which is higher than or equal to the voltage at its source or drain.

Fig. 4 is an illustration of an example system 400 adapted according to an embodiment. As noted above, various computing systems may include multiple processing units. Thus, FIG. 4 includes two processing units-a Central Processing Unit (CPU)402 and a Graphics Processing Unit (GPU) 404. The example of fig. 4 illustrates a portion of a computing system, such as an SOC or other multi-component computing system, which may be implemented in any of a variety of devices, such as a smartphone, tablet, laptop, and the like.

Fig. 4 includes a power multiplexer 410 coupled to the CPU 402 and a power multiplexer 420 coupled to the GPU 404. The power multiplexers 410, 420 are controlled by a power multiplexer controller 430, the power multiplexer controller 430 outputting control signals En _1-En _4 as appropriate to select a given power supply at a given processing unit. In contrast to the illustration of fig. 1, where a single power multiplexer controller is associated with a single power multiplexer, the embodiment of fig. 4 illustrates that the control functionality of the power multiplexer controller may be used to control multiple power multiplexers throughout the system. For example, the power multiplexer controller 430 may select the power supply 412 or the power supply 414 by asserting one of the control signals En _1 or En _2 and de-asserting the other control signal. This may cause the power multiplexer 410 to conduct current from one of the power supplies 412, 414 to the CPU 402 and turn off the branch associated with the other of the power supplies.

Similarly, the power multiplexer controller 430 may select the power supply 412 or 422 by asserting one of the control signals En _3 or En _4 and de-asserting the other of the control signals. This may cause power multiplexer 420 to conduct current from one of power supplies 412, 422 to GPU 404 and turn off the branch associated with the other of the power supplies. Power multiplexer controller 430 is controlled by CPU 402 in this example via a "select" signal that causes power multiplexer controller 430 to assert or de-assert any of the En _ X control signals as appropriate. Of course, the scope of embodiments is not limited to this particular manner of control, as power multiplexer controller 430 may be controlled by any suitable logic suitable for a particular application.

Each of the power multiplexers 410, 420 in the example of fig. 4 may be implemented according to the architecture illustrated above with respect to fig. 1-3. In particular, each of the power multiplexers 410, 420 may include two branches-one for each of its respective power supplies-and each of the branches has at least two transistors. Each branch may have one transistor controlled by the voltage from the level shifter and another transistor controlled by the voltage of the corresponding control signal En _ X.

Continuing with the example, power supply 412 may be an "always on" power supply that provides a reliable and stable voltage, while power supplies 414, 422 may or may not be "always on" power supplies. For example, one embodiment may implement power supply 412 using PMICs feeding widely used power domains, as illustrated by power supply 412 providing power at multiplexer 410, multiplexer 420, and power multiplexer controller 430. Examples of power supplies 414 and 422 may include Switched Mode Power Supplies (SMPS) associated with less widely used local power domains. Further, in this example, the power supply 412 is associated with a higher current than the power supplies 414, 422, because the power supply 412 may be used to power both processing units 402, 404 during normal operation.

Consider an example use case in which it is desirable to regulate the voltage of the CPU 402. For example, it may be desirable to increase the voltage at the CPU 402 in order to increase the frequency of operation, or it may be desirable to decrease the voltage at the CPU 402 in order to save power. In any case, such voltage changes may be facilitated by the power supply 414 (local to the CPU 402) so as to leave the GPU 404 unaffected. In such an example, CPU 402 may use a "select" signal to cause power multiplexer controller 430 to assert or de-assert the appropriate one of En _1 or En _2 to cause power multiplexer 410 to conduct current from power supply 414 and to turn off the branch associated with power supply 412. When the CPU 402 receives its power from the power supply 414, other processes may reduce or increase the voltage from the power supply 414 accordingly.

In some cases, the frequency and voltage changes are determined by an operating system kernel executed by the CPU 402, although the scope of embodiments may include any functionality that provides frequency and voltage changes. Once the operating system kernel determines to change the frequency and voltage of the CPU 402 back to normal, the CPU 402 may use the "select" signal to cause the power mux controller 430 to assert or de-assert En _1 or En _2 as appropriate so that the power mux 410 conducts current from the power supply 412 instead of from the power supply 414.

Similar operations may be performed at the GPU 404 with respect to the power multiplexer 420. In other words, assuming that the power supply 412 is an "always on" power supply, the voltage change may be accomplished by: the power mux controller 430 causes the power mux 420 to switch to the power supply 422 and accordingly increases or decreases the voltage at the power supply 422. The power mux controller 430 may switch the power mux 420 back at a later time to conduct current from the power supply 412 to the GPU 404.

The embodiment of fig. 4 shows a CPU 402 and a GPU 404, but the scope of the embodiments is not limited to any number of processing units, nor to any number of components that may be individually voltage controlled by a power multiplexer. Rather, the principles described with respect to fig. 1-4 may be scaled to include any number of power multiplexer controllers, any number of power multiplexers, power supplies, and processing units. Further, although power multiplexers 410, 420 are shown as corresponding to individual processing units, the scope of embodiments is not limited to the level of abstraction at the processing units. Rather, any power consuming component (for which it may be desirable to select a power domain for that individual component) may be associated with the power multiplexer. Also, any number of power multiplexers may be used in a computing system to properly supply power to any component that is both reliable and flexible.

Various embodiments may include one or more advantages over conventional systems. For example, some conventional power multiplexers may use branches that may be turned on or off, where the branches each have only a single transistor. However, such conventional power multiplexers may not completely turn off the transistors, thereby allowing current to leak from the power supply (when it is intended that another power supply be selected). In contrast, various embodiments described herein use multiple transistors in each branch, where the transistors in each branch may be controlled by different voltages, thereby taking a higher voltage to turn off the transistor (when the source/drain of the transistor may be exposed to a higher voltage). Thus, such embodiments may reduce or eliminate current through the transistor intended to be off.

In addition, various embodiments may omit analog comparators and voltage generators, instead using logic and voltage level shifters of multiple transistors in each branch to turn a given branch on or off in response to assertion or de-assertion of a control signal. Such embodiments may therefore be less complex and use less circuit space than some conventional power multiplexers.

A flow diagram of an example method 500 of multiplexing between multiple power supplies is illustrated in fig. 5. In one example, method 500 is performed by a power management unit, which may include hardware and/or software functionality at a processor (e.g., CPU) of a computing device. In some examples, the power management unit includes processing circuitry that executes computer-readable instructions to switch between the plurality of power sources according to a particular algorithm. In some embodiments, the power management unit may include functionality provided by an operating system kernel or other utility in a GPU, CPU, or other processing unit. This function causes the GPU, CPU, or other processing unit to send signals to one or more power multiplexers to control these power multiplexers to switch between different power sources. The power multiplexer controller receives these signals from the processing unit and then asserts or de-asserts the control signal accordingly.

At act 510, the power multiplexer controller asserts a control signal to a first leg of the power multiplexer to turn off the first leg. An example is shown in fig. 3, where the first branch 101 comprises a first PMOS transistor 111 and a second PMOS transistor 112 coupled between the first power supply VDD _ AUX and the power output 120. In this example, the asserted control signal is applied to the gate of the first transistor 111 and to the level shifter 132 at the gate of the second transistor 112.

In this example, asserting the control signal causes the first and second transistors to turn off. For example, at act 510, the gate of the first transistor 111 is at a voltage (0.75V) that is equal to or higher than the voltage associated with the first power supply VDD _ AUX (0.75V). Continuing the example, the voltage level shifter 132 shifts the voltage of the control signal to a voltage associated with the second power supply VDD _ DOM (0.95V). Accordingly, the gate of the second transistor 112 is at a voltage equal to or higher than the voltage associated with the second power supply.

At act 520, the power multiplexer controller de-asserts the control signal to the second leg of the power multiplexer. Act 520 causes the second leg to turn on.

An example is shown in fig. 3, where de-asserting the control signal comprises: a lower voltage level (e.g., 0V) is applied to the gates of the third and fourth PMOS transistors 113, 114. In the present example, the third and fourth transistors 113, 114 are switched on when their gates are at a lower voltage than their sources or their drains.

At act 530, the power multiplexer conducts current from the second power supply to the power output. In the example of fig. 3, when the second branch 102 is turned on, the second branch 102 conducts current from the second power supply VDD _ DOM to the power output 120.