阅读说明：本技术 一种基于fpga的多级逻辑结构 (Multistage logic structure based on FPGA ) 是由 不公告发明人 于 2018-08-31 设计创作，主要内容包括：一种基于FPGA的多级逻辑结构,包括第1级FPGA单元、第2级FPGA单元和第3级FPGA单元。第1级FPGA单元的电信号连接到第2级FPGA单元的输入端,第2级FPGA单元的输出端连接到第3级FPGA单元的输入端。(A multi-level logic structure based on FPGA comprises a 1 st-level FPGA unit, a 2 nd-level FPGA unit and a 3 rd-level FPGA unit. The electric signal of the 1 st-level FPGA unit is connected to the input end of the 2 nd-level FPGA unit, and the output end of the 2 nd-level FPGA unit is connected to the input end of the 3 rd-level FPGA unit.)

1. The utility model provides a multistage logical structure based on FPGA, includes 1 st level FPGA unit, 2 nd level FPGA unit and 3 rd level FPGA unit, the electrical signal connection of 1 st level FPGA unit is to the input of 2 nd level FPGA unit, and the output of 2 nd level FPGA unit is connected to the input of 3 rd level FPGA unit.

Technical Field

The invention relates to a multilevel logic structure based on an FPGA.

Background

Some existing electronic functional components gradually adopt FPGA devices to realize online programmability. However, due to the limited internal effective logic resources of the single-chip FPGA, the on-line upgrade operation may not be completed for some complex functions. If a multi-level logic structure is adopted, the method has certain value for upgrading complex functions.

Disclosure of Invention

In order to overcome the defects of the existing equipment, the invention provides a multilevel logic structure based on an FPGA.

The technical scheme adopted by the invention for solving the technical problems is as follows: a multi-level logic structure based on FPGA comprises a 1 st-level FPGA unit, a 2 nd-level FPGA unit and a 3 rd-level FPGA unit. The electric signal of the 1 st-level FPGA unit is connected to the input end of the 2 nd-level FPGA unit, and the output end of the 2 nd-level FPGA unit is connected to the input end of the 3 rd-level FPGA unit.

The invention has the following beneficial effects: compared with the existing device, the FPGA-based multi-level logic structure provided by the invention can improve the online programmability of complex functions.

Drawings

Fig. 1 is a block diagram of a multi-level logic structure based on an FPGA.

Detailed Description

The invention is further described below with reference to fig. 1.

A multi-level logic structure based on FPGA comprises a 1 st-level FPGA unit, a 2 nd-level FPGA unit and a 3 rd-level FPGA unit. The electric signal of the 1 st-level FPGA unit is connected to the input end of the 2 nd-level FPGA unit, and the output end of the 2 nd-level FPGA unit is connected to the input end of the 3 rd-level FPGA unit.

The embodiments described in this specification are merely illustrative of implementations of the inventive concept and the scope of the present invention should not be considered limited to the specific forms set forth in the embodiments but rather by the equivalents thereof as may occur to those skilled in the art upon consideration of the present inventive concept.