阅读说明：本技术 一种量子密钥分发的光源编码驱动系统 (Light source coding driving system for quantum key distribution ) 是由 郭邦红 胡敏 于 2021-06-26 设计创作，主要内容包括：本发明公开了一种量子密钥分发的光源编码驱动系统,包括偏振编码驱动单元,相位编码驱动单元,衰减控制驱动单元和控制单元,所述偏振编码驱动单元,相位编码驱动单元,衰减控制驱动单元均分别与控制单元连接,其中：所述偏振编码驱动单元与偏振调制器连接,用于驱动与控制偏振调制器,为所述偏振调制器提供RF激励信号和偏置电；所述相位编码驱动单元与相位调制器连接,用于驱动与控制相位调制器,为偏振调制器提供RF激励信号；所述衰减控制单元与衰减器连接,用于调节衰减器衰减值,为衰减器提供模拟量调节信号。本发明采用激光窄脉冲结合RF调制信号的方式,与传统的激光器连续发光相比,降低了激光器的能耗,提升了光源的使用寿命。(The invention discloses a light source coding driving system for quantum key distribution, which comprises a polarization coding driving unit, a phase coding driving unit, an attenuation control driving unit and a control unit, wherein the polarization coding driving unit, the phase coding driving unit and the attenuation control driving unit are respectively connected with the control unit, and the polarization coding driving unit, the phase coding driving unit and the attenuation control driving unit are respectively connected with the control unit, wherein: the polarization coding driving unit is connected with the polarization modulator and used for driving and controlling the polarization modulator and providing an RF excitation signal and bias electricity for the polarization modulator; the phase coding driving unit is connected with the phase modulator, and is used for driving and controlling the phase modulator and providing an RF excitation signal for the polarization modulator; the attenuation control unit is connected with the attenuator and used for adjusting the attenuation value of the attenuator and providing an analog quantity adjusting signal for the attenuator. The invention adopts the mode of combining the laser narrow pulse with the RF modulation signal, and compared with the traditional laser for continuous light emitting, the invention reduces the energy consumption of the laser and prolongs the service life of the light source.)

1. The light source coding driving system for quantum key distribution is characterized by comprising a polarization coding driving unit, a phase coding driving unit, an attenuation control driving unit and a control unit, wherein the polarization coding driving unit, the phase coding driving unit and the attenuation control driving unit are respectively connected with the control unit, and the polarization coding driving unit, the phase coding driving unit and the attenuation control driving unit are respectively connected with the control unit, wherein:

the polarization coding driving unit is connected with the polarization modulator and used for driving and controlling the polarization modulator and providing an RF excitation signal and a bias voltage for the polarization modulator;

the phase coding driving unit is connected with the phase modulator and is used for driving and controlling the phase modulator and providing an RF excitation signal for the phase modulator;

the attenuation control unit is connected with the attenuator and is used for adjusting the attenuation value of the attenuator and providing an analog quantity adjusting signal for the attenuator;

the control unit is used for adjusting the frequency, amplitude, time delay and bias voltage of the polarization coding driving unit RF; the control unit is used for adjusting the frequency, amplitude and time delay of the phase coding driving unit RF; the control unit is used for adjusting the analog quantity value output by the attenuation control driving unit.

2. The light source coding driving system for quantum key distribution according to claim 1, wherein the polarization coding driving unit comprises a first signal delay circuit, a second signal delay circuit, a first high-speed digital-to-analog conversion DAC circuit, a first signal amplification circuit and a second low-speed digital-to-analog conversion DAC circuit, wherein:

the first signal delay circuit and the second signal delay circuit are respectively connected with the control unit through respective input ports;

an output port of the first signal delay circuit is connected with an input port of a second signal delay circuit, and an output port of the second signal delay circuit is connected with the first high-speed digital-to-analog conversion DAC circuit;

the first high-speed digital-to-analog conversion DAC circuit, the first signal amplifying circuit and the polarization modulator are sequentially connected;

the input end of the second low-speed digital-to-analog conversion DAC circuit is connected with the control unit, and the output end of the second low-speed digital-to-analog conversion DAC circuit is connected with the polarization modulator.

3. The light source coding driving system for quantum key distribution according to claim 2, wherein the control unit sends out RF _ IN pulse signals, which sequentially pass through the first signal delay circuit, the second signal delay circuit performs two delay processes and inputs the RF _ IN pulse signals into the first high-speed digital-to-analog conversion DAC circuit, the first high-speed digital-to-analog conversion DAC circuit randomly outputs pulses with different amplitudes corresponding to signal lights IN horizontal, vertical, positive 45 degree and negative 45 degree polarization states according to the received RF _ IN pulse signals, and then inputs the pulses into the first signal amplification circuit for amplification and then inputs the pulses into the polarization modulator to drive the polarization modulator;

and the second low-speed digital-to-analog conversion DAC circuit receives the setting parameters transmitted by the control unit through the SPI bus and adjusts the bias voltage of the polarization modulator.

4. The light source coding driving system for quantum key distribution according to claim 2, wherein the first signal delay circuit and the second signal delay circuit are both provided with delay chips, two of the delay chips are serially cascaded, the two chips are respectively connected with the control unit through the delay configuration port, and the delay time of the delay chips is configured through the control unit;

the high-speed digital-to-analog conversion DAC circuit adopts an AD970X series DAC chip, and the control unit configures the DAC chip through an SPI bus.

5. The quantum key distributed light source coding driving system according to claim 2, wherein the first signal amplifying circuit comprises a high-speed operational amplifier chip, and the amplified signal is input to a polarization modulator;

and the control unit configures the second low-speed digital-to-analog conversion DAC circuit to output an analog voltage output value through an SPI bus, and an output port of the second low-speed digital-to-analog conversion DAC circuit is connected to the bias voltage input end of the polarization modulator.

6. The light source coding driving system for quantum key distribution according to claim 1, wherein the phase coding driving unit comprises a third delay circuit, a fourth delay circuit, a third high-speed digital-to-analog conversion (DAC) circuit and a third signal amplifying circuit;

the third signal delay circuit and the fourth signal delay circuit are respectively connected with the control unit through respective input ports, an output port of the third signal delay circuit is connected with the fourth signal delay circuit, and a port of the fourth signal delay circuit is connected with the third high-speed digital-to-analog conversion DAC circuit; and the third high-speed digital-to-analog conversion DAC circuit, the second signal amplification circuit and the phase modulator are sequentially connected.

7. The light source coding driving system for quantum key distribution according to claim 6, wherein the control unit sends out RF _ IN pulse signals sequentially through a third signal delay circuit, the fourth signal delay circuit performs two delay processes and inputs the RF _ IN pulse signals into a third high-speed digital-to-analog conversion DAC circuit, and the third high-speed digital-to-analog conversion DAC circuit randomly outputs pulses with different amplitudes corresponding to signal lights of four phases 0, pi/2, and 3 pi/2 according to the received RF _ IN pulse signals, and then inputs the pulses into a third signal amplification circuit and then inputs the pulses into the phase modulator to drive the phase modulator.

8. The quantum key distributed light source coding driving system according to claim 1, wherein the attenuation control driving unit comprises a fourth low-speed digital-to-analog conversion DAC circuit and a fourth signal amplification circuit;

the input end of the fourth low-speed digital-to-analog conversion DAC circuit is connected with the control unit through a CONFIG port and a DATA DATA port, the output end of the fourth low-speed digital-to-analog conversion DAC circuit is connected with the fourth signal amplification circuit, and the output port of the fourth signal amplification circuit is connected with the controllable attenuator.

9. The light source coding driving system for quantum key distribution as claimed in claim 8, wherein the control unit configures the fourth low speed DAC circuit through CONFIG port, the digital quantity of the DATA port of the control unit is converted into analog signal through the fourth low speed DAC circuit, and the analog signal controls the attenuation value of the attenuator through the fourth signal amplifying circuit.

10. The light source coding driving system for quantum key distribution according to claim 9, wherein the fourth low speed DAC circuit comprises a digital-to-analog conversion chip of AD56X5 series, the control unit configures the digital-to-analog conversion chip through I2C bus, I2C bus is used to set digital value to be converted;

the fourth signal amplifying circuit comprises an operational amplifier and an MEMS chip, and analog signals after digital-to-analog conversion are input to the operational amplifier for equidirectional amplification, and then the MEMS chip is driven to change the optical power attenuation value.

Technical Field

The invention relates to the field of quantum information and optical communication, in particular to a light source coding driving system for quantum key distribution.

Background

In the quantum key distribution system, a light source coding driving system is responsible for regulating, controlling and coding the single photon signal of the Alice terminal and then sending the single photon signal to a quantum channel, and the Bob terminal decodes the received photon information.

The traditional QKD optical coding mode is single-polarization or single-phase, and only one single photon carries 1bit coding information, and the coding mode can cause certain loss in the transmission process of photons, thereby greatly reducing the generation rate of keys.

Therefore, there is a need to improve the existing quantum coding method, and a patent with patent publication No. CN111555863A and patent name "sending end, coding method and quantum key distribution system for time phase-polarization joint coding" provides a high-dimensional joint coding method, which performs time phase modulation and polarization modulation on 1 photon at the same time. The technical scheme is as follows: comprises a light source, an encoding module, a first reflecting unit and a second reflecting unit, wherein,

the light source is used for providing signal light to be coded;

the encoding module comprises a phase modulation unit and is arranged to: dividing the signal light to be encoded into a first signal light component and a second signal light component; performing a first phase modulation on at least one of the first and second signal light components by means of the phase modulation unit; and interfering the first and second signal light components and outputting one or two first interference light signals;

the first reflection unit and the second reflection unit have different optical paths from each other and are arranged to receive the first interference optical signal and reflect it back to the encoding module;

the encoding module is further configured to: receiving a reflected optical signal and separating it into a first reflected optical signal component and a second reflected optical signal component, wherein the reflected optical signal component has time phase encoded information; performing a second phase modulation on at least one of the first and second reflected optical signal components by means of the phase modulation unit; and interfering the first and second reflected optical signal components and outputting a second interference optical signal, wherein the second interference optical signal has the time phase encoded information and polarization encoded information.

In view of the above shortcomings of the prior art, further improvements to the existing encoding technology are needed.

Disclosure of Invention

In order to solve the technical problem, a light source coding driving system of a quantum key distribution system with double coding of polarization phase and high key generation rate is provided.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows: the utility model provides a light source coding drive system of quantum key distribution, includes polarization code drive unit, phase coding drive unit, attenuation control drive unit and control unit, the control unit adopts FPGA the control unit, polarization code drive unit, phase coding drive unit, attenuation control drive unit are all connected with FPGA the control unit respectively, wherein:

the polarization coding driving unit is connected with the polarization modulator and used for driving and controlling the polarization modulator and providing an RF excitation signal and a bias voltage for the polarization modulator;

the phase coding driving unit is connected with the phase modulator, and is used for driving and controlling the phase modulator and providing an RF excitation signal for the polarization modulator;

the attenuation control unit is connected with the attenuator and is used for adjusting the attenuation value of the attenuator and providing an analog quantity adjusting signal for the attenuator;

the FPGA control unit adjusts the magnitude of the bias voltage by adjusting the frequency, amplitude and time delay of the polarization coding driving unit RF; the FPGA control unit adjusts the frequency, amplitude and time delay of the phase coding driving unit RF; the FPGA control unit controls the analog quantity value output by the driving unit by adjusting the attenuation.

Preferably, the polarization coding driving unit includes a first signal delay circuit, a second signal delay circuit, a first high-speed digital-to-analog conversion DAC circuit, a first signal amplification circuit, and a second low-speed digital-to-analog conversion DAC circuit, where:

the first signal delay circuit and the second signal delay circuit are respectively connected with the FPGA control unit through respective input ports, an output port of the first signal delay circuit is connected with the second signal delay circuit, and a port of the second signal delay circuit is connected with the first high-speed digital-to-analog conversion DAC circuit; the first high-speed digital-to-analog conversion DAC circuit, the first signal amplifying circuit and the polarization modulator are sequentially connected;

the input end of the second low-speed digital-to-analog conversion DAC circuit is connected with the FPGA control unit, and the output end of the second low-speed digital-to-analog conversion DAC circuit is connected with the polarization modulator.

Preferably, the FPGA control unit sends out RF _ IN pulse signals, which sequentially pass through the first signal delay circuit, the second signal delay circuit performs two delay processes and inputs the RF _ IN pulse signals into the first high-speed digital-to-analog conversion DAC circuit, the first high-speed digital-to-analog conversion DAC circuit randomly outputs pulses with different amplitudes corresponding to signal lights IN horizontal, vertical, positive 45-degree and negative 45-degree polarization states according to the received RF _ IN pulse signals, and then inputs the pulses into the first signal amplification circuit for amplification, and the RF _ IN pulse signals are input into the polarization modulator to drive the polarization modulator;

and the second low-speed digital-to-analog conversion DAC circuit receives the setting parameters transmitted by the FPGA control unit through the SPI bus and adjusts the bias voltage of the polarization modulator.

Preferably, the first signal delay circuit and the second signal delay circuit are respectively provided with a delay chip adopting NB6L series chips, the two delay chips are serially cascaded, the two chips are respectively connected with the FPGA control unit through a delay configuration port, and the delay time of the delay chips is configured through the connection of the FPGA control unit;

the first high-speed digital-to-analog conversion DAC circuit adopts AD970X series DAC chips, and the FPGA control unit configures the DAC chips through the SPI bus;

preferably, the first signal amplifying circuit comprises an OPA series high-speed operational amplifier chip, and the amplified signal is connected to the polarization modulator after being blocked by a capacitor;

the second low-speed digital-to-analog conversion DAC circuit adopts a 16-bit AD57X1 series DAC chip, the FPGA control unit is configured with the DAC chip of the second low-speed digital-to-analog conversion DAC circuit through an SPI bus, the output analog voltage output value of the second low-speed digital-to-analog conversion DAC circuit is set through the SPI bus, and the output port DC-10/10 is connected to the bias voltage input end of the polarization modulator.

Preferably, the phase coding driving unit comprises a third delay circuit, a fourth delay circuit, a third high-speed digital-to-analog conversion DAC circuit and a third signal amplifying circuit;

the third signal delay circuit and the fourth signal delay circuit are respectively connected with the FPGA control unit through respective input ports, an output port of the third signal delay circuit is connected with the fourth signal delay circuit, and a port of the fourth signal delay circuit is connected with the third high-speed digital-to-analog conversion DAC circuit; and the third high-speed digital-to-analog conversion DAC circuit, the second signal amplification circuit and the phase modulator are sequentially connected.

Preferably, the FPGA control unit sends out RF _ IN pulse signals, which sequentially pass through the third signal delay circuit, the fourth signal delay circuit performs two delay processes and inputs the RF _ IN pulse signals into the third high-speed digital-to-analog conversion DAC circuit, the third high-speed digital-to-analog conversion DAC circuit randomly outputs pulses with different amplitudes corresponding to signal lights with four phases of 0, pi/2 and 3 pi/2 according to the received RF _ IN pulse signals, and then inputs the pulses into the third signal amplification circuit for amplification, and the RF _ IN pulse signals are input into the phase modulator to drive the phase modulator.

Preferably, the attenuation control driving unit comprises a fourth low-speed digital-to-analog conversion DAC circuit and a fourth signal amplifying circuit;

the input end of the fourth low-speed digital-to-analog conversion DAC circuit is connected with the control unit through a CONFIG port and a DATA DATA port, the output end of the fourth low-speed digital-to-analog conversion DAC circuit is connected with the fourth signal amplification circuit, and the fourth signal amplification circuit is connected with the controllable attenuator;

preferably, the FPGA control unit configures the fourth low-speed digital-to-analog converter DAC circuit through a CONFIG port, the digital quantity of the DATA port is converted into an analog signal through the fourth low-speed digital-to-analog converter DAC circuit, and the analog signal controls the attenuation value of the attenuator through the fourth signal amplifying circuit.

Preferably, the fourth low-speed digital-to-analog converter DAC circuit includes a digital-to-analog conversion chip, the digital-to-analog conversion chip is an AD56X5 series chip, the FPGA configures the digital-to-analog conversion chip through an I2C bus, and the I2C bus is used to set a digital value to be converted;

the fourth signal amplifying circuit comprises an operational amplifier and an MEMS chip, and after the digital-to-analog conversion and the same-direction amplification of the operational amplifier, the MEMS chip changes the optical power attenuation value.

The invention has the beneficial effects that:

the invention adopts phase polarization combined modulation, and the code rate is 2 times of that of the traditional BB84 protocol;

the invention adopts the mode of combining the laser narrow pulse with the RF modulation signal, and compared with the traditional laser for continuous light emitting, the invention reduces the energy consumption of the laser and prolongs the service life of the light source.

Drawings

FIG. 1 is a block diagram of the overall principle of the present invention;

FIG. 2 is a hardware block diagram of a polarization encoded driving unit according to the present invention;

FIG. 3 is a schematic diagram showing the phase relationship between RF _ IN and the laser narrow pulse IN the present invention;

FIG. 4 is a block diagram of the hardware of the phase-encoding driving unit of the present invention;

FIG. 5 is a hardware schematic block diagram of the attenuation control drive unit of the present invention;

fig. 6 is a schematic diagram of a signal amplifying circuit according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments, but the scope of the present invention is not limited to the following embodiments.

As shown in fig. 1 to 6, a light source coding driving system of a quantum key distribution system includes a polarization coding driving unit, a phase coding driving unit, an attenuation control driving unit and a control unit, where the control unit employs an FPGA control unit, and the polarization coding driving unit, the phase coding driving unit and the attenuation control driving unit are respectively connected with the FPGA control unit, where:

the polarization coding driving unit is connected with the polarization modulator and used for driving and controlling the polarization modulator and providing an RF excitation signal and a bias voltage for the polarization modulator;

the phase coding driving unit is connected with the phase modulator, and is used for driving and controlling the phase modulator and providing an RF excitation signal for the polarization modulator;

the attenuation control unit is connected with the attenuator and is used for adjusting the attenuation value of the attenuator and providing an analog quantity adjusting signal for the attenuator;

the FPGA control unit enables the RF Frequency to be the same as the laser narrow pulse Frequency and adjusts the RF amplitude by adjusting the Frequency of a Radio Frequency (RF) of a polarization coding driving unit, so that four different amplitudes are generated and correspond to four quantum polarization states; the RF delay is adjusted to align the RF signal with the laser narrow pulse while the polarization modulator bias voltage DC _ IN is adjusted. The magnitude of DC _ IN IN relation to the half-wave voltage of the polarization modulator determines the mode of operation of the polarization modulator.

The FPGA control unit adjusts the analog quantity value output by the attenuation control driving unit, different values of the analog quantity correspond to the attenuation value of the controllable attenuator, and the optical signal energy is attenuated to a single photon state through attenuation.

The polarization coding driving unit comprises a first signal delay circuit, a second signal delay circuit, a first high-speed digital-to-analog conversion DAC circuit, a first signal amplification circuit and a second low-speed digital-to-analog conversion DAC circuit, wherein:

the first signal delay circuit and the second signal delay circuit are respectively connected with the FPGA control unit through respective input ports, an output port of the first signal delay circuit is connected with the second signal delay circuit, and an output port of the second signal delay circuit is connected with the first high-speed digital-to-analog conversion DAC circuit; the first high-speed digital-to-analog conversion DAC circuit, the first signal amplifying circuit and the polarization modulator are sequentially connected;

the input end of the second low-speed digital-to-analog conversion DAC circuit is connected with the FPGA control unit, and the output end of the second low-speed digital-to-analog conversion DAC circuit is connected with the polarization modulator.

The FPGA control unit sends an RF _ IN pulse signal to sequentially pass through a first signal delay circuit, a second signal delay circuit carries out delay processing twice and then inputs the RF _ IN pulse signal into a first high-speed digital-to-analog conversion DAC circuit, the first high-speed digital-to-analog conversion DAC circuit randomly outputs pulses with different amplitudes corresponding to signal light IN horizontal, vertical, positive 45-degree and negative 45-degree polarization states according to the received RF _ IN pulse signal, then the RF _ IN signal which is input into a first signal amplification circuit and amplified is input into a polarization modulator to drive the polarization modulator, and the driven polarization modulator generates signal light IN four polarization states of horizontal, vertical, positive 45-degree and negative 45-degree.

The second low-speed digital-to-analog conversion DAC circuit receives the setting parameters of the FPGA control unit, the bias voltage of the polarization modulator is adjusted by changing the voltage value of the second low-speed digital-to-analog conversion DAC circuit DC _ IN, and the FPGA control unit and the second low-speed digital-to-analog conversion DAC circuit are transmitted through the SPI bus.

The first signal delay circuit and the second signal delay circuit are both provided with delay chips, the delay chips are NB6L series chips, the two delay chips are IN serial cascade connection, the two delay chips are respectively connected with the FPGA control unit through delay configuration ports, and the delay time of the delay chips is configured through the FPGA control unit, so that the phase relation between RF _ IN and laser narrow pulse is adjusted, each delay chip can provide delay within 15ns, and the maximum delay of the two cascade connections can reach 30 ns.

The first signal delay circuit and the second signal delay circuit are used for adjusting alignment of an RF _ IN pulse and a laser narrow pulse, an RF _ IN radio frequency signal is modulated onto laser through a polarization modulator, phases of the RF _ IN and the laser narrow pulse are shown IN figure 2, the FPGA control unit controls the first signal delay circuit through a first delay #1 configuration interface, and the second delay #2 configuration interface controls the second signal delay circuit.

The first high-speed digital-to-analog conversion DAC circuit adopts AD970X series DAC chips, and the FPGA control unit configures the first high-speed digital-to-analog conversion DAC circuit through the SPI bus.

The first signal amplifying circuit comprises a high-speed operational amplifier chip, and signals amplified by the first signal amplifying circuit are input to the polarization modulator after being blocked by the capacitor.

The second low-speed digital-to-analog conversion DAC circuit adopts AD57X1 series DAC chips, the FPGA control unit configures the 16-bit DAC chip of the second low-speed digital-to-analog conversion DAC circuit through the SPI bus, the output analog voltage output value of the DAC chip is set through the SPI bus, and the output port DC-10/10 is connected to the bias voltage input end of the polarization modulator.

The phase coding driving unit comprises a third delay circuit, a fourth delay circuit, a third high-speed digital-to-analog conversion DAC circuit and a third signal amplifying circuit;

the third signal delay circuit and the fourth signal delay circuit are respectively connected with the FPGA control unit through respective input ports, an output port of the third signal delay circuit is connected with the fourth signal delay circuit, and a port of the fourth signal delay circuit is connected with the third high-speed digital-to-analog conversion DAC circuit; and the third high-speed digital-to-analog conversion DAC circuit, the second signal amplification circuit and the phase modulator are sequentially connected.

The FPGA control unit sends out RF _ IN pulse signals which sequentially pass through the third signal delay circuit, the fourth signal delay circuit carries out delay processing twice and then inputs the RF _ IN pulse signals into the third high-speed digital-to-analog conversion DAC circuit, the third high-speed digital-to-analog conversion DAC circuit randomly outputs pulses with different amplitudes corresponding to signal lights with four phases of 0, pi/2 and 3 pi/2 according to the received RF _ IN pulse signals, then the pulses are input into the third signal amplification circuit and amplified, the RF _ IN signals are input into the phase modulator to drive the phase modulator, and the phase modulator generates modulated signal lights with four different phases of 0, pi/2 and 3 pi/2 according to the RF _ IN.

The attenuation control driving unit comprises a fourth low-speed digital-to-analog conversion DAC circuit and a fourth signal amplifying circuit;

the input end of the fourth low-speed digital-to-analog conversion DAC circuit is connected with the control unit through a CONFIG port and a DATA DATA port, the output end of the fourth low-speed digital-to-analog conversion DAC circuit is connected with the fourth signal amplification circuit, and the fourth signal amplification circuit is connected with the controllable attenuator;

the FPGA control unit is configured with the fourth low-speed digital-to-analog converter DAC circuit through a CONFIG port, the digital quantity of the DATA DATA port is converted into an analog signal through the fourth low-speed digital-to-analog converter DAC circuit, the analog signal controls the attenuation value of the attenuator through a fourth signal amplifying circuit, and the attenuator attenuates the energy of signal light to a single photon state.

The fourth low-speed digital-to-analog converter DAC circuit comprises a digital-to-analog conversion chip, the model of the digital-to-analog conversion chip is an AD56X5 series chip, the FPGA configures the digital-to-analog conversion chip through an I2C bus, and the I2C bus is used for setting a digital value to be converted.

The fourth signal amplifying circuit comprises an operational amplifier OPA and an MEMS driving chip MEMS, and after the digital-to-analog conversion and the same-direction amplification of the operational amplifier OPA, the MEMS driving chip changes the optical power attenuation value. The amplification of the operational amplifier is equal toThe amplification factor of the operational amplifier OPA can be changed by adjusting the resistance value.

As shown in fig. 1, under the action of the system, a laser narrow pulse first passes through a polarization modulator to modulate a light pulse into a polarized signal light with a polarization state such as horizontal, vertical, positive 45 degrees or negative 45 degrees, then the polarized signal light passes through a phase modulator to modulate the polarized signal light with phase information of 0, pi/2 or 3 pi/2, then the light signal energy is attenuated into a single photon state through an attenuator, and the single photon state is transmitted through a quantum channel.

Variations and modifications to the above-described embodiments may occur to those skilled in the art, which fall within the scope and spirit of the above description. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and variations of the present invention should fall within the scope of the claims of the present invention. Furthermore, although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.