阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 金雄来 于 2018-12-12 设计创作，主要内容包括：本发明提供了一种半导体器件。半导体器件包括列控制电路和核心电路。列控制电路响应于在掩蔽写入操作期间生成的读取锁存脉冲和写入锁存脉冲来从读取存储体地址信号和写入存储体地址信号生成读取列信号和写入列信号。核心电路被配置成包括多个存储体。多个存储体中的任一个通过读取列信号和写入列信号来激活以执行内部读取操作和写入操作。(The invention provides a semiconductor device. The semiconductor device includes a column control circuit and a core circuit. The column control circuit generates a read column signal and a write column signal from a read bank address signal and a write bank address signal in response to a read latch pulse and a write latch pulse generated during a masked write operation. The core circuit is configured to include a plurality of memory banks. Any one of the plurality of banks is activated by the read column signal and the write column signal to perform an internal read operation and a write operation.)

1. A semiconductor device, comprising:

a column control circuit configured to: generating a read column signal and a write column signal from the read bank address signal and the write bank address signal in response to the read latch pulse and the write latch pulse generated during the masked write operation; and

a core circuit comprising a plurality of memory banks, wherein at least one of:

a bank of the plurality of banks is activated by the read column signal to perform an internal read operation,

and

a bank of the plurality of banks is activated by the write column signal to perform a write operation.

2. The semiconductor device of claim 1, wherein the masked-write operation comprises performing the internal read operation and the write operation performed in sequence.

3. The semiconductor device of claim 1, wherein the bank activated during the write operation is the same as the bank activated during the internal read operation.

4. The semiconductor device according to claim 1, wherein the column control circuit interrupts input of the write latch pulse to the column control circuit during the internal read operation.

5. The semiconductor device as set forth in claim 1,

wherein the read latch pulse comprises first and second read latch pulses;

wherein the read bank address signals include first, second, third, and fourth read bank address signals;

wherein the write latch pulse comprises first and second write latch pulses;

wherein the write bank address signals include first, second, third, and fourth write bank address signals;

wherein the read column signals comprise first, second, third and fourth read column signals;

wherein the write column signals include first, second, third, and fourth write column signals; and

wherein the column control circuit comprises:

a bank control circuit configured to generate first, second, third and fourth read latch address signals or first, second, third and fourth internal read latch address signals from the first, second, third and fourth read bank address signals in response to the first and second read latch pulses, and configured to generate first, second, third and fourth write latch address signals or first, second, third and fourth internal write latch address signals from the first, second, third and fourth write bank address signals in response to the first and second write latch pulses;

a signal synthesis circuit configured to generate a read synthesis signal by synthesizing first and second read pulses that are sequentially enabled during the internal read operation, and configured to generate a write synthesis signal by synthesizing first and second write pulses that are sequentially enabled during the write operation; and

a column signal generating circuit configured to output the first, second, third and fourth read latch address signals or the first, second, third and fourth internal read latch address signals as the first, second, third and fourth read column signals in response to the read combining signal, and configured to output the first, second, third and fourth write latch address signals or the first, second, third and fourth internal write latch address signals as the first, second, third and fourth write column signals in response to the write combining signal.

6. The semiconductor device according to claim 5, wherein the bank control circuit comprises:

a first bank control circuit configured to generate the first read latch address signal or the first internal read latch address signal from the first read bank address signal in response to the first and second read latch pulses, and configured to generate the first write latch address signal or the first internal write latch address signal from the first write bank address signal in response to the first and second write latch pulses;

a second bank control circuit configured to generate the second read latch address signal or the second internal read latch address signal from the second read bank address signal in response to the first and second read latch pulses, and configured to generate the second write latch address signal or the second internal write latch address signal from the second write bank address signal in response to the first and second write latch pulses;

a third bank control circuit configured to generate the third read latch address signal or the third internal read latch address signal from the third read bank address signal in response to the first and second read latch pulses, and configured to generate the third write latch address signal or the third internal write latch address signal from the third write bank address signal in response to the first and second write latch pulses; and

a fourth bank control circuit configured to generate the fourth read latch address signal or the fourth internal read latch address signal from the fourth read bank address signal in response to the first and second read latch pulses, and configured to generate the fourth write latch address signal or the fourth internal write latch address signal from the fourth write bank address signal in response to the first and second write latch pulses.

7. The semiconductor device of claim 5, wherein the signal synthesis circuit comprises:

a first combining circuit configured to generate the read combined signal, the read combined signal being enabled when either of the first and second read pulses is input to the first combining circuit; and

a second synthesizing circuit configured to generate the write synthesized signal, the write synthesized signal being enabled when any one of the first and second write pulses is input to the second synthesizing circuit.

8. The semiconductor device according to claim 5, wherein the column signal generation circuit comprises:

a first column signal generating circuit configured to output the first read latch address signal and the first internal read latch address signal as the first read column signal in response to the read synthesis signal, configured to output the first write latch address signal and the first internal write latch address signal as the first write column signal in response to the write synthesis signal, and configured to interrupt input of the first write latch address signal and the first internal write latch address signal in response to a write/read control signal;

a second column signal generating circuit configured to output the second read latch address signal and the second internal read latch address signal as the second read column signal in response to the read combining signal, configured to output the second write latch address signal and the second internal write latch address signal as the second write column signal in response to the write combining signal, and configured to interrupt input of the second write latch address signal and the second internal write latch address signal in response to the write/read control signal;

a third column signal generating circuit configured to output the third read latch address signal and the third internal read latch address signal as the third read column signal in response to the read synthetic signal, configured to output the third write latch address signal and the third internal write latch address signal as the third write column signal in response to the write synthetic signal, and configured to interrupt input of the third write latch address signal and the third internal write latch address signal in response to the write/read control signal; and

a fourth column signal generating circuit configured to output the fourth read latch address signal and the fourth internal read latch address signal as the fourth read column signal in response to the read combining signal, configured to output the fourth write latch address signal and the fourth internal write latch address signal as the fourth write column signal in response to the write combining signal, and configured to interrupt input of the fourth write latch address signal and the fourth internal write latch address signal in response to the write/read control signal.

9. The semiconductor device of claim 1, further comprising:

a read/write control circuit configured to: generating a read control signal and a write control signal that are sequentially enabled in response to a masked-write signal being enabled during the masked-write operation, and configured to: generating a read pulse and a write pulse that are sequentially enabled in response to the masked write signal;

a latch pulse generation circuit configured to latch and delay the read pulse by a predetermined period to generate the read latch pulse, and configured to latch and delay the write pulse by the predetermined period to generate the write latch pulse; and

a bank address generating circuit configured to generate the read bank address signal from a command/address signal in response to the read control signal, and configured to generate the write bank address signal from the command/address signal in response to the write control signal.

10. The semiconductor device as set forth in claim 9,

wherein the command/address signals include first, second, third, and fourth command/address signals;

wherein the read bank address signals include first, second, third, and fourth read bank address signals;

wherein the write bank address signals include first, second, third, and fourth write bank address signals; and

wherein the bank address generating circuit includes:

read bank address generation circuitry configured to generate the first, second, third, and fourth read bank address signals from the first, second, third, and fourth command/address signals in response to the read control signal; and

a write bank address generation circuit configured to generate the first, second, third, and fourth write bank address signals from the first, second, third, and fourth command/address signals in response to the write control signal.

11. The semiconductor device according to claim 10, wherein the read bank address generating circuit comprises:

a first counter configured to: generating first, second, third and fourth read input signals and first, second, third and fourth read output signals that are counted in order in response to the read control signal; and

a first pipeline circuit configured to latch the first, second, third, and fourth command/address signals in response to the first, second, third, and fourth read input signals, and configured to output the latched signals of the first, second, third, and fourth command/address signals as the first, second, third, and fourth read bank address signals in response to the first, second, third, and fourth read output signals.

12. The semiconductor device according to claim 10, wherein the write bank address generating circuit comprises:

a second counter configured to: generating first, second, third and fourth write input signals and first, second, third and fourth write output signals that are counted in order in response to the write control signal; and

a second pipeline circuit configured to latch the first, second, third, and fourth command/address signals in response to the first, second, third, and fourth write input signals, and configured to output the latched signals of the first, second, third, and fourth command/address signals as the first, second, third, and fourth write bank address signals in response to the first, second, third, and fourth write output signals.

13. A semiconductor device, comprising:

a bank control circuit configured to generate first and second read latch address signals or first and second internal read latch address signals from first and second read bank address signals in response to first and second read latch pulses, and configured to generate first and second write latch address signals or first and second internal write latch address signals from first and second write bank address signals in response to first and second write latch pulses;

a signal synthesis circuit configured to generate a read synthesis signal by synthesizing first and second read pulses that are sequentially enabled during an internal read operation of a masked write operation, and configured to generate a write synthesis signal by synthesizing first and second write pulses that are sequentially enabled during a write operation of the masked write operation; and a column signal generating circuit configured to output the first and second read latch address signals or the first and second internal read latch address signals as first and second read column signals in response to the read combining signal, and configured to output the first and second write latch address signals or the first and second internal write latch address signals as first and second write column signals in response to the write combining signal.

14. The semiconductor device of claim 13, wherein the bank control circuit comprises:

a first bank control circuit configured to generate the first read latch address signal or the first internal read latch address signal from the first read bank address signal in response to the first and second read latch pulses, and configured to generate the first write latch address signal or the first internal write latch address signal from the first write bank address signal in response to the first and second write latch pulses; and

a second bank control circuit configured to generate the second read latch address signal or the second internal read latch address signal from the second read bank address signal in response to the first and second read latch pulses, and configured to generate the second write latch address signal or the second internal write latch address signal from the second write bank address signal in response to the first and second write latch pulses.

15. The semiconductor device according to claim 14, wherein the first bank control circuit comprises:

a first pulse generating circuit configured to generate the first read latch address signal from the first read bank address signal in response to the first read latch pulse;

a second pulse generating circuit configured to generate the first internal read latch address signal from the first read bank address signal in response to the second read latch pulse;

a third pulse generating circuit configured to generate the first write latch address signal from the first write bank address signal in response to the first write latch pulse; and

a fourth pulse generating circuit configured to generate the first internal write latch address signal from the first write bank address signal in response to the second write latch pulse.

16. The semiconductor device according to claim 14, wherein the second bank control circuit comprises:

a fifth pulse generating circuit configured to generate the second read latch address signal from the second read bank address signal in response to the first read latch pulse;

a sixth pulse generating circuit configured to generate the second internal read latch address signal from the second read bank address signal in response to the second read latch pulse;

a seventh pulse generating circuit configured to generate the second write latch address signal from the second write bank address signal in response to the first write latch pulse; and

an eighth pulse generating circuit configured to generate the second internal write latch address signal from the second write bank address signal in response to the second write latch pulse.

17. The semiconductor device of claim 13, wherein the signal synthesis circuit comprises:

a first combining circuit configured to generate the read combined signal, the read combined signal being enabled when either of the first and second read pulses is input to the first combining circuit; and

a second synthesizing circuit configured to generate the write synthesized signal, the write synthesized signal being enabled when any one of the first and second write pulses is input to the second synthesizing circuit.

18. The semiconductor device according to claim 13, wherein the column signal generation circuit comprises:

a first column signal generating circuit configured to output the first read latch address signal and the first internal read latch address signal as the first read column signal in response to the read synthesis signal, configured to output the first write latch address signal and the first internal write latch address signal as the first write column signal in response to the write synthesis signal, and configured to interrupt input of the first write latch address signal and the first internal write latch address signal in response to a write/read control signal; and

a second column signal generating circuit configured to output the second read latch address signal and the second internal read latch address signal as the second read column signal in response to the read combining signal, configured to output the second write latch address signal and the second internal write latch address signal as the second write column signal in response to the write combining signal, and configured to interrupt input of the second write latch address signal and the second internal write latch address signal in response to the write/read control signal.

19. The semiconductor device of claim 18, wherein the first column signal generation circuit comprises:

a first control signal generation circuit configured to generate a first control signal that is enabled in response to the first read latch address signal and the first internal read latch address signal, configured to generate the first control signal from the first write latch address signal and the first internal write latch address signal in response to the write/read control signal, or to interrupt input of the first write latch address signal and the first internal write latch address signal in response to the write/read control signal, and configured to generate a second control signal from the first write latch address signal and the first internal write latch address signal;

a first internal read signal generation circuit configured to latch the read resultant signal in response to the first control signal to generate a first internal read signal;

a first internal write signal generation circuit configured to latch the write synthesis signal in response to the second control signal to generate a first internal write signal; and

a first select/transmit circuit configured to output the first internal read signal as the first read column signal or the first internal write signal as the first write column signal in response to a flag signal being enabled during the internal read operation.

20. The semiconductor device of claim 18, wherein the second column signal generation circuit comprises:

a second control signal generation circuit configured to generate a third control signal that is enabled in response to the second read latch address signal and the second internal read latch address signal, configured to generate the third control signal from the second write latch address signal and the second internal write latch address signal in response to the write/read control signal, or interrupt input of the second write latch address signal and the second internal write latch address signal in response to the write/read control signal, and configured to generate a fourth control signal from the second write latch address signal and the second internal write latch address signal;

a second internal read signal generation circuit configured to latch the read resultant signal in response to the third control signal to generate a second internal read signal;

a second internal write signal generation circuit configured to latch the write synthesis signal in response to the fourth control signal to generate a second internal write signal; and

a second select/transmit circuit configured to output the second internal read signal as the second read column signal or the second internal write signal as the second write column signal in response to a flag signal being enabled during the internal read operation.

Technical Field

Embodiments of the present disclosure relate to a semiconductor device performing a masked write operation.

Background

In general, a semiconductor device such as a Dynamic Random Access Memory (DRAM) device may include a plurality of bank groups having a cell array selected by an address. Each of the bank groups may be implemented to include a plurality of banks. The semiconductor device may select any one of a plurality of bank groups, and may perform a column operation for outputting data stored in a cell array included in the selected bank group through an input/output (I/O) line.

Disclosure of Invention

According to one embodiment, a semiconductor device includes a column control circuit and a core circuit. The column control circuit generates a read column signal and a write column signal from a read bank address signal and a write bank address signal in response to a read latch pulse and a write latch pulse generated during a masked write operation. The core circuit is configured to include a plurality of memory banks. Any one of the plurality of banks is activated by a read column signal and a write column signal to perform an internal read operation and a write operation.

According to another embodiment, a semiconductor device includes a bank control circuit, a signal synthesis circuit, and a column signal generation circuit. The bank control circuit is configured to generate first and second read latch address signals, or first and second internal read latch address signals, from first and second read bank address signals in response to first and second read latch pulses. Further, the bank control circuit is configured to generate first and second write latch address signals, or first and second internal write latch address signals, from the first and second write bank address signals in response to the first and second write latch pulses. The signal synthesis circuit is configured to generate a read synthesis signal by synthesizing first and second read pulses that are sequentially enabled during an internal read operation of a masked write operation. Further, the signal synthesizing circuit is configured to generate a write synthesized signal by synthesizing the first and second write pulses that are sequentially enabled during a write operation of the masked-write operation. The column signal generating circuit is configured to output the first and second read latch address signals, or the first and second internal read latch address signals, as the first and second read column signals in response to the read combining signal. Further, the column signal generating circuit is configured to output the first and second write latch address signals, or the first and second internal write latch address signals, as the first and second write column signals in response to the write synthesis signal.

Drawings

Fig. 1 shows a block diagram illustrating a configuration of a semiconductor device according to one embodiment of the present disclosure.

Fig. 2 shows a block diagram illustrating the configuration of a latch pulse generating circuit included in the semiconductor device of fig. 1.

Fig. 3 shows a block diagram illustrating a configuration of a bank address generating circuit included in the semiconductor device of fig. 1.

Fig. 4 shows a circuit diagram illustrating a configuration of a first counter included in the bank address generating circuit of fig. 3.

Fig. 5 shows a block diagram illustrating a configuration of a first pipe circuit included in the bank address generating circuit of fig. 3.

Fig. 6 shows a circuit diagram illustrating a configuration of a second counter included in the bank address generating circuit of fig. 3.

Fig. 7 shows a block diagram illustrating a configuration of a second pipeline circuit included in the bank address generating circuit of fig. 3.

Fig. 8 shows a block diagram illustrating the configuration of a column control circuit included in the semiconductor device of fig. 1.

Fig. 9 shows a block diagram illustrating the configuration of a bank control circuit included in the column control circuit of fig. 8.

Fig. 10 shows a circuit diagram illustrating a configuration of a first bank control circuit included in the bank control circuit of fig. 9.

Fig. 11 shows a circuit diagram illustrating the configuration of a signal synthesizing circuit included in the column control circuit of fig. 8.

Fig. 12 shows a block diagram illustrating the configuration of a column signal generating circuit included in the column control circuit of fig. 8.

Fig. 13 shows a circuit diagram illustrating the configuration of the first column signal generating circuit included in the column signal generating circuit of fig. 12.

Fig. 14 shows a timing diagram illustrating the operation of a semiconductor device according to one embodiment of the present disclosure.

Fig. 15 shows a block diagram illustrating a configuration of an electronic system including the semiconductor device shown in fig. 1 to 14.

Detailed Description

Various embodiments of the present disclosure are described below with reference to the drawings. The described embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

The semiconductor device may provide the bank group mode to include an 8-bank mode and a 16-bank mode. The bank group may include a plurality of banks. For example, a bank group may include four banks. In the bank group mode, a column operation for one bank included in the bank group may be performed by one command. In the 8-bank mode, column operations respectively for two banks included in a single bank group are sequentially performed by one command. In the 16-bank mode, column operations respectively for four banks included in a single bank group are sequentially performed by one command.

As illustrated in fig. 1, a semiconductor device according to one embodiment may include a command decoder 1, a read/write control circuit 2, a latch pulse generation circuit 3, a bank address generation circuit 4, a column control circuit 5, and a core circuit 6.

If the command/address signals CA <1: N > have a logic level combination for performing the masked-write operation, the command decoder 1 may be synchronized with the internal clock signal ICLK and the inverted internal clock signal ICLKB in response to the chip select signal CS to generate the masked-write signal EMWT. The command decoder 1 may decode the command/address signals CA <1: N > in synchronization with the internal clock signal ICLK and the inverted internal clock signal ICLKB in response to the chip select signal CS to generate the masked write signal EMWT. The logic level combination of the command/address signals CA <1: N > for generating the masked write signal EMWT may be set differently for different embodiments. The masked write operation means an operation including an internal read operation and a write operation which are sequentially performed by one command. The number of bits included in the command/address signals CA <1: N > may be different for different embodiments. The command/address signals CA <1: N > may include bits for generating the masked write signal EMWT, bits for generating first to fourth (i.e., first, second, third, and fourth) read bank address signals BA _ MWT <1:4>, and bits for generating first to fourth write bank address signals BA <1:4 >.

The read/write control circuit 2 may generate the read control signal RDTF and the write control signal WTTF that are sequentially enabled in response to the masked write signal EMWT. The read/write control circuit 2 may generate the write control signal after a time for performing the internal read operation has elapsed from a time point at which the read control signal RDTF is generated. The internal read and write operations may be performed with a burst length of 32. With respect to the burst length, '32' means that 32 bits of data are input to the core circuit 6 or output from the core circuit 6 by a single operation performed with one write command or one read command. According to embodiments, the burst length of the internal read and write operations may be set to "4", "8", "16", and so on.

The read/write control circuit 2 may generate a first read pulse RDAYP and a second read pulse IRDAYP that are sequentially enabled in response to the masked write signal EMWT. The read/write control circuit 2 may generate the second read pulse IRDAYP after a time for performing an internal read operation has elapsed from a point in time at which the first read pulse RDAYP is generated in response to the masked write signal EMWT.

The read/write control circuit 2 may generate the first write pulse WTAYP and the second write pulse IWTAYP that are sequentially enabled in response to the masked write signal EMWT. The read/write control circuit 2 may generate the second write pulse IWTAYP after a time for performing a write operation has elapsed from a point in time at which the first write pulse WTAYP is generated in response to the masked write signal EMWT.

The latch pulse generation circuit 3 may latch the first read pulse RDAYP and the second read pulse IRDAYP and may delay latch pulses of the first and second read pulses RDAYP and IRDAYP by a predetermined period to generate a first read latch pulse ADD _ LATP _ MWT and a second read latch pulse IADD _ LATP _ MWT. The term "predetermined", such as a predetermined period of time, as used herein with respect to a parameter, means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm, but before the parameter is used in the process or algorithm.

The latch pulse generation circuit 3 may latch the first write pulse WTAYP and the second write pulse IWTAYP, and may delay latch pulses of the first and second write pulses WTAYP and IWTAYP by a predetermined period to generate a first write latch pulse ADD _ LATP _ BG and a second write latch pulse IADD _ LATP _ BG.

The bank address generating circuit 4 may generate first to fourth read bank address signals BA _ MWT <1:4> from the first to fourth command/address signals CA <1:4> in response to the read control signal RDTF. If the read control signal RDTF is enabled, the bank address generating circuit 4 may latch the first to fourth command/address signals CA <1:4> to output latch signals of the first to fourth command/address signals CA <1:4> as the first to fourth read bank address signals BA _ MWT <1:4 >.

The bank address generating circuit 4 may generate the first to fourth write bank address signals BA <1:4> from the first to fourth command/address signals CA <1:4> in response to the write control signal WTTF. If the write control signal WTTF is enabled, the bank address generating circuit 4 may latch the first to fourth command/address signals CA <1:4> to output latch signals of the first to fourth command/address signals CA <1:4> as the first to fourth write bank address signals BA <1:4 >.

The column control circuit 5 may generate first to fourth read column signals AYP _ MWT <1:4> from the first to fourth read bank address signals BA _ MWT <1:4> in response to the first read latch pulse ADD _ LATP _ MWT and the second read latch pulse IADD _ LATP _ MWT. If the first read latch pulse ADD _ LATP _ MWT is enabled, the column control circuit 5 can generate first to fourth read column signals AYP _ MWT <1:4> from the first to fourth read bank address signals BA _ MWT <1:4 >. If the second read latch pulse IADD _ LATP _ MWT is enabled, the column control circuit 5 may generate first to fourth read column signals AYP _ MWT <1:4> from the first to fourth read bank address signals BA _ MWT <1:4 >.

The column control circuit 5 can generate first to fourth write column signals AYP _ BG <1:4> from the first to fourth write bank address signals BA <1:4> in response to the first write latch pulse ADD _ LATP _ BG and the second write latch pulse IADD _ LATP _ BG. The column control circuit 5 can generate first to fourth write column signals AYP _ BG <1:4> from the first to fourth write bank address signals BA <1:4> if the first write latch pulse ADD _ LATP _ BG is enabled. The column control circuit 5 may generate first to fourth write column signals AYP _ BG <1:4> from the first to fourth write bank address signals BA <1:4> if the second write latch pulse IADD _ LATP _ BG is enabled.

The core circuit 6 may include first to fourth banks BK1 to BK 4. As used herein, the wave number "" denotes the extent of the component. For example, "BK 1 to BK 4" indicate the first BK1, the second BK2, the third BK3, and the fourth BK4 shown in fig. 1. The core circuit 6 may activate one of the first to fourth banks BK1 to BK4 to perform an internal read operation in response to the first to fourth read column signals AYP _ MWT <1:4 >. If the first read column signal AYP _ MWT <1> is enabled, the first bank BK1 may be activated to perform an internal read operation. If the second read column signal AYP _ MWT <2> is enabled, the second bank BK2 may be activated to perform an internal read operation. If the third read column signal AYP _ MWT <3> is enabled, the third bank BK3 may be activated to perform an internal read operation. If the fourth read column signal AYP _ MWT <4> is enabled, the fourth bank BK4 may be activated to perform an internal read operation.

The core circuit 6 may activate one of the first to fourth banks BK 1-BK 4 to perform an internal write operation in response to the first to fourth write column signals AYP _ BG <1:4 >. If the first write column signal AYP _ BG <1> is enabled, the first bank BK1 can be activated to perform a write operation. If the second write column signal AYP _ BG <2> is enabled, the second bank BK2 can be activated to perform a write operation. If the third write column signal AYP _ BG <3> is enabled, the third bank BK3 may be activated to perform a write operation. If the fourth write column signal AYP _ BG <4> is enabled, the fourth bank BK4 may be activated to perform a write operation.

Although the core circuit 6 is configured to include the first to fourth banks BK1 to BK4, the number of banks included in the core circuit 6 may be different for different embodiments. Two or more banks in the core circuit 6 may constitute one bank group.

Referring to fig. 2, the latch pulse generating circuit 3 may include a first delay circuit 31 and a second delay circuit 32.

The first delay circuit 31 may latch the first read pulse RDAYP and the second read pulse IRDAYP and may delay latch pulses of the first and second read pulses RDAYP and IRDAYP by a predetermined period to generate a first read latch pulse ADD _ LATP _ MWT and a second read latch pulse IADD _ LATP _ MWT. The first delay circuit 31 may latch the first read pulse RDAYP and may delay a latch pulse of the first read pulse RDAYP by a predetermined period to generate a first read latch pulse ADD _ LATP _ MWT. The first delay circuit 31 may latch the second read pulse IRDAYP and may delay a latch pulse of the second read pulse IRDAYP by a predetermined period to generate a second read latch pulse IADD _ LATP _ MWT. In different embodiments, the predetermined period corresponding to the delay time of the first delay circuit 31 may be set differently.

The second delay circuit 32 may latch the first write pulse WTAYP and the second write pulse IWTAYP, and may delay latch pulses of the first and second write pulses WTAYP and IWTAYP for a predetermined period of time to generate a first write latch pulse ADD _ LATP _ BG and a second write latch pulse IADD _ LATP _ BG. The second delay circuit 32 may latch the first write pulse WTAYP and may delay a latch pulse of the first write pulse WTAYP by a predetermined period to generate a first write latch pulse ADD _ LATP _ BG. The second delay circuit 32 may latch the second write pulse IWTAYP and may delay a latch pulse of the second write pulse IWTAYP by a predetermined period to generate a second write latch pulse IADD _ LATP _ BG. The predetermined period corresponding to the delay time of the second delay circuit 32 may be set differently for different embodiments.

Referring to fig. 3, the bank address generating circuit 4 may include a read bank address generating circuit 41 and a write bank address generating circuit 42.

The read bank address generating circuit 41 may include a first counter 410 and a first pipeline circuit (pipeline) 420.

The first counter 410 may generate first to fourth read input signals RPIN <1:4> and first to fourth read output signals RPOUT <1:4> that are sequentially counted in response to the read control signal RDTF. The first counter 410 may generate first to fourth read input signals RPIN <1:4> and first to fourth read output signals RPOUT <1:4> that are counted in order if the read control signal RDTF is enabled.

The first pipe circuit 420 may latch the first to fourth command/address signals CA <1:4> in response to the first to fourth read input signals RPIN <1:4 >. The first pipe circuit 420 may output latch signals of the first to fourth command/address signals CA <1:4> as first to fourth read bank address signals BA _ MWT <1:4> in response to the first to fourth read output signals RPOUT <1:4 >.

As described above, the read bank address generating circuit 41 may generate the first to fourth read bank address signals BA _ MWT <1:4> from the first to fourth command/address signals CA <1:4> in response to the read control signal RDTF.

Write bank address generation circuitry 42 may include a second counter 430 and a second pipeline circuit 440.

The second counter 430 may generate first to fourth write input signals WPIN <1:4> and first to fourth write output signals WPOUT <1:4> that are sequentially counted in response to the write control signal WTTF. The second counter 430 may generate first to fourth write input signals WPIN <1:4> and first to fourth write output signals WPOUT <1:4> that are counted in order if the write control signal WTTF is enabled.

The second pipeline circuit 440 may latch the first to fourth command/address signals CA <1:4> in response to the first to fourth write input signals WPIN <1:4 >. The second pipe circuit 440 may output latch signals of the first to fourth command/address signals CA <1:4> as the first to fourth write bank address signals BA <1:4> in response to the first to fourth write output signals WPOUT <1:4 >.

As described above, the write bank address generation circuit 42 may generate the first to fourth write bank address signals BA <1:4> from the first to fourth command/address signals CA <1:4> in response to the write control signal WTTF.

Referring to fig. 4, the first counter 410 may include a read input signal generation circuit 411 and a read output signal generation circuit 412.

The read input signal generation circuit 411 may generate first to fourth transfer signals TS <1:4> that are sequentially enabled in response to the read control signal RDTF. The read input signal generation circuit 411 may output the first to fourth transfer signals TS <1:4> that are sequentially enabled when the read control signal RDTF is enabled as the first to fourth read input signals RPIN <1:4 >.

The read output signal generation circuit 412 may generate fifth to eighth transfer signals TS <5:8> that are sequentially enabled in response to the read control signal RDTF. The read output signal generation circuit 412 may output the fifth to eighth transfer signals TS <5:8> that are sequentially enabled when the read control signal RDTF is enabled as the first to fourth read output signals RPOUT <1:4 >.

Referring to fig. 5, the first pipe circuit 420 may include a first latch circuit 421, a second latch circuit 422, a third latch circuit 423, and a fourth latch circuit 424.

The first latch circuit 421 may latch the first command/address signal CA <1> in response to the first read input signal RPIN <1 >. The first latch circuit 421 may output a latch signal of the first command/address signal CA <1> as the first read bank address signal BA _ MWT <1> in response to the first read output signal RPOUT <1 >.

The second latch circuit 422 may latch the second command/address signal CA <2> in response to the second read input signal RPIN <2 >. The second latch circuit 422 may output a latch signal of the second command/address signal CA <2> as the second read bank address signal BA _ MWT <2> in response to the second read output signal RPOUT <2 >.

The third latch circuit 423 may latch the third command/address signal CA <3> in response to the third read input signal RPIN <3 >. The third latch circuit 423 may output a latch signal of the third command/address signal CA <3> as the third read bank address signal BA _ MWT <3> in response to the third read output signal RPOUT <3 >.

The fourth latch circuit 424 may latch the fourth command/address signal CA <4> in response to the fourth read input signal RPIN <4 >. The fourth latch circuit 424 may output a latch signal of the fourth command/address signal CA <4> as the fourth read bank address signal BA _ MWT <4> in response to the fourth read output signal RPOUT <4 >.

Referring to fig. 6, the second counter 430 may include a write input signal generation circuit 431 and a write output signal generation circuit 432.

The write input signal generation circuit 431 may generate ninth to twelfth transfer signals TS <9:12> that are sequentially enabled in response to the write control signal WTTF. The write input signal generation circuit 431 may output ninth to twelfth transfer signals TS <9:12> that are sequentially enabled when the write control signal WTTF is enabled as the first to fourth write input signals WPIN <1:4 >.

The write output signal generation circuit 432 may generate thirteenth to sixteenth transmission signals TS <13:16> that are sequentially enabled in response to the write control signal WTTF. The write output signal generation circuit 432 may output thirteenth to sixteenth transfer signals TS <13:16> that are sequentially enabled when the write control signal WTTF is enabled as the first to fourth write output signals WPOUT <1:4 >.

Referring to fig. 7, the second pipe circuit 440 may include a fifth latch circuit 441, a sixth latch circuit 442, a seventh latch circuit 443, and an eighth latch circuit 444.

The fifth latch circuit 441 may latch the first command/address signal CA <1> in response to the first write input signal WPIN <1 >. The fifth latch circuit 441 may output a latch signal of the first command/address signal CA <1> as the first write bank address signal BA <1> in response to the first write output signal WPOUT <1 >.

The sixth latch circuit 442 may latch the second command/address signal CA <2> in response to the second write input signal WPIN <2 >. The sixth latch circuit 442 may output a latch signal of the second command/address signal CA <2> as the second write bank address signal BA <2> in response to the second write output signal WPOUT <2 >.

The seventh latch circuit 443 may latch the third command/address signal CA <3> in response to the third write input signal WPIN <3 >. The seventh latch circuit 443 may output a latch signal of the third command/address signal CA <3> as the third write bank address signal BA <3> in response to the third write output signal WPOUT <3 >.

The eighth latch circuit 444 may latch the fourth command/address signal CA <4> in response to the fourth write input signal WPIN <4 >. The eighth latch circuit 444 may output a latch signal of the fourth command/address signal CA <4> as the fourth write bank address signal BA <4> in response to the fourth write output signal WPOUT <4 >.

Referring to fig. 8, the column control circuit 5 may include a bank control circuit 51, a signal synthesis circuit 52, and a column signal generation circuit 53.

The bank control circuit 51 may generate first to fourth read latch address signals LATP _ MWT <1:4> from first to fourth read bank address signals BA _ MWT <1:4> in response to the first read latch pulse ADD _ LATP _ MWT. The bank control circuit 51 may output the first to fourth read bank address signals BA _ MWT <1:4> as the first to fourth read latch address signals LATP _ MWT <14> if the first read latch pulse ADD _ LATP _ MWT is enabled. The bank control circuit 51 may generate the first to fourth internal read latch address signals ILATP _ MWT <1:4> from the first to fourth read bank address signals BA _ MWT <1:4> in response to the second read latch pulse IADD _ LATP _ MWT. If the second read latch pulse IADD _ LATP _ MWT is enabled, the bank control circuit 51 may output the first to fourth read bank address signals BA _ MWT <1:4> as the first to fourth internal read latch address signals ILATP _ MWT <1:4 >.

The bank control circuit 51 may generate first to fourth write latch address signals LATP _ BG <1:4> from the first to fourth write bank address signals BA <1:4> in response to the first write latch pulse ADD _ LATP _ BG. The bank control circuit 51 may output first to fourth write bank address signals BA <1:4> as the first to fourth write latch address signals LATP _ BG <14> if the first write latch pulse ADD _ LATP _ BG is enabled. The bank control circuit 51 may generate first to fourth internal write latch address signals ILATP _ BG <1:4> from the first to fourth write bank address signals BA <1:4> in response to the second write latch pulse IADD _ LATP _ BG. The bank control circuit 51 may output the first to fourth write bank address signals BA <1:4> as the first to fourth internal write latch address signals ILATP _ BG <1:4> if the second write latch pulse IADD _ LATP _ BG is enabled.

The signal synthesizing circuit 52 may synthesize the first read pulse RDAYP and the second read pulse IRDAYP that are sequentially enabled during the internal read operation to generate the read synthesized signal RD _ SUM. The signal synthesizing circuit 52 may synthesize the first write pulse WTAYP and the second write pulse IWTAYP that are sequentially enabled during a write operation to generate a write synthesized signal WT _ SUM.

The column signal generation circuit 53 may generate first to fourth read column signals AYP _ MWT <1:4> from the first to fourth read latch address signals LATP _ MWT <1:4> or the first to fourth internal read latch address signals ILATP _ MWT <1:4> in response to the read synthesis signal RD _ SUM. If the read synthesis signal RD _ SUM is enabled, the column signal generation circuit 53 may output the first to fourth read latch address signals LATP _ MWT <1:4> or the first to fourth internal read latch address signals ILATP _ MWT <1:4> as the first to fourth read column signals AYP _ MWT <1:4 >. The column signal generation circuit 53 may generate first to fourth write column signals AYP _ BG <1:4> from the first to fourth write latch address signals LATP _ BG <1:4> or the first to fourth internal write latch address signals ILATP _ BG <1:4> in response to the write synthesis signal WT _ SUM. If the write synthesis signal WT _ SUM is enabled, the column signal generation circuit 53 may output the first to fourth write latch address signals LATP _ BG <1:4> or the first to fourth internal write latch address signals ILATP _ BG <1:4> as the first to fourth write column signals AYP _ BG <1:4 >.

Referring to fig. 9, the bank control circuit 51 may include a first bank control circuit 511, a second bank control circuit 512, a third bank control circuit 513, and a fourth bank control circuit 514.

The first bank control circuit 511 may generate the first read latch address signal LATP _ MWT <1> or the first internal read latch address signal ILATP _ MWT <1> from the first read bank address signal BA _ WMT <1> in response to the first read latch pulse ADD _ LATP _ WMT and the second read latch pulse IADD _ LATP _ MWT. The first bank control circuit 511 may generate a first write latch address signal LATP _ BG <1> or a first internal write latch address signal ILATP _ BG <1> from the first write bank address signal BA <1> in response to the first write latch pulse ADD _ LATP _ BG and the second write latch pulse IADD _ LATP _ BG.

The second bank control circuit 512 may generate the second read latch address signal LATP _ MWT <2> or the second internal read latch address signal ILATP _ MWT <2> from the second read bank address signal BA _ WMT <2> in response to the first read latch pulse ADD _ LATP _ WMT and the second read latch pulse IADD _ LATP _ MWT. The second bank control circuit 512 may generate a second write latch address signal LATP _ BG <2> or a second internal write latch address signal ILATP _ BG <2> from the second write bank address signal BA <2> in response to the first write latch pulse ADD _ LATP _ BG and the second write latch pulse IADD _ LATP _ BG.

The third bank control circuit 513 may generate a third read latch address signal LATP _ MWT <3> or a third internal read latch address signal ILATP _ MWT <3> from the third read bank address signal BA _ WMT <3> in response to the first read latch pulse ADD _ LATP _ WMT and the second read latch pulse IADD _ LATP _ MWT. The third bank control circuit 513 may generate a third write latch address signal LATP _ BG <3> or a third internal write latch address signal ILATP _ BG <3> from the third write bank address signal BA <3> in response to the first write latch pulse ADD _ LATP _ BG and the second write latch pulse IADD _ LATP _ BG.

The fourth bank control circuit 514 may generate the fourth read latch address signal LATP _ MWT <4> or the fourth internal read latch address signal ILATP _ MWT <4> from the fourth read bank address signal BA _ WMT <4> in response to the first read latch pulse ADD _ LATP _ WMT and the second read latch pulse IADD _ LATP _ MWT. The fourth bank control circuit 514 may generate a fourth write latch address signal LATP _ BG <4> or a fourth internal write latch address signal ILATP _ BG <4> from the fourth write bank address signal BA <4> in response to the first write latch pulse ADD _ LATP _ BG and the second write latch pulse IADD _ LATP _ BG.

Referring to fig. 10, the first bank control circuit 511 may include a first pulse generation circuit 5111, a second pulse generation circuit 5112, a third pulse generation circuit 5113, and a fourth pulse generation circuit 5114.

The first pulse generating circuit 5111 may generate a first read latch address signal LATP _ WMT <1> from a first read bank address signal BA _ WMT <1> in response to a first read latch pulse ADD _ LATP _ WMT. If the first read latch pulse ADD _ LATP _ WMT having a logic "high" level is input to the first pulse generation circuit 5111, the first pulse generation circuit 5111 may generate the first read latch address signal LATP _ WMT <1> from the first read bank address signal BA _ WMT <1 >.

The second pulse generating circuit 5112 may generate the first internal read latch address signal ILATP _ WMT <1> from the first read bank address signal BA _ WMT <1> in response to the second read latch pulse IADD _ LATP _ WMT. If the second read latch pulse IADD _ LATP _ WMT having a logic "high" level is input to the second pulse generation circuit 5112, the second pulse generation circuit 5112 may generate the first internal read latch address signal ILATP _ WMT <1> from the first read bank address signal BA _ WMT <1 >.

The third pulse generation circuit 5113 may generate a first write latch address signal LATP _ BG <1> from the first write bank address signal BA <1> in response to the first write latch pulse ADD _ LATP _ BG. If the first write latch pulse ADD _ LATP _ BG having a logic "high" level is input to the third pulse generation circuit 5113, the third pulse generation circuit 5113 may generate the first write latch address signal LATP _ BG <1> from the first write bank address signal BA <1 >.

The fourth pulse generation circuit 5114 may generate the first internal write latch address signal ILATP _ BG <1> from the first write bank address signal BA <1> in response to the second write latch pulse IADD _ LATP _ BG. If the second write latch pulse IADD _ LATP _ BG having a logic "high" level is input to the fourth pulse generation circuit 5114, the fourth pulse generation circuit 5114 may generate the first internal write latch address signal ILATP _ BG <1> from the first write bank address signal BA <1 >.

Each of the second, third, and fourth bank control circuits 512, 513, and 514 may be implemented to have substantially the same configuration as the first bank control circuit 511 illustrated in fig. 10 except for input/output (I/O) signals thereof. Accordingly, each of the second, third, and fourth bank control circuits 512, 513, and 514 may perform substantially the same operation as the first bank control circuit 511. Therefore, detailed descriptions of the second, third, and fourth bank control circuits 512, 513, and 514 are omitted herein.

Referring to fig. 11, the signal synthesizing circuit 52 may include a first synthesizing circuit 521 and a second synthesizing circuit 522.

The first combining circuit 521 may generate a read combining signal RD _ SUM that is enabled if any one of the first and second read pulses RDAYP and IRDAYP is input to the first combining circuit 521. The first combining circuit 521 may perform a logical or operation of the first and second read pulses RDAYP and IRDAYP to generate the read combined signal RD _ SUM. The first combining circuit 521 may generate a read combining signal RD _ SUM that is enabled to have a logic "high" level if any one of the first and second read pulses RDAYP and IRDAYP input to the first combining circuit 521 has a logic "high" level.

The second combining circuit 522 may generate a write combined signal WT _ SUM that is enabled if any one of the first and second write pulses WTAYP and IWTAYP is input to the second combining circuit 522. The second combining circuit 522 may perform a logical or operation of the first and second write pulses WTAYP and IWTAYP to generate the write combined signal WT _ SUM. The second combining circuit 522 may generate a write combined signal WT _ SUM that is enabled to have a logic "high" level if any one of the first and second write pulses WTAYP and IWTAYP input to the second combining circuit 522 has a logic "high" level.

Referring to fig. 12, the column signal generating circuit 53 may include a first column signal generating circuit 531, a second column signal generating circuit 532, a third column signal generating circuit 533, and a fourth column signal generating circuit 534.

The first column signal generation circuit 531 may output the first read latch address signal LATP _ WMT <1> and the first internal read latch address signal ilapt _ WMT <1> as the first read column signal AYP _ WMT <1> in response to the read synthesis signal RD _ SUM. If the read synthesis signal RD _ SUM is enabled to have a logic "high" level, the first column signal generation circuit 531 may output the first read latch address signal LATP _ WMT <1> and the first internal read latch address signal ilapt _ WMT <1> as the first read column signal AYP _ WMT <1 >. The first column signal generation circuit 531 may output the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1> as the first write column signal AYP _ BG <1> in response to the write synthesis signal WT _ SUM. The first column signal generation circuit 531 may output the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1> as the first write column signal AYP _ BG <1>, if the write synthesis signal WT _ SUM is enabled to have a logic "high" level. The first column signal generation circuit 531 may interrupt the input of the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1> in response to the write/read control signal WTRDB. The first column signal generation circuit 531 may interrupt the input of the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1>, if the write/read control signal WTRDB is enabled to have a logic "high" level. When an internal read operation is performed, the write/read control signal WTRDB may be enabled to have a logic "high" level.

The second column signal generation circuit 532 may output the second read latch address signal LATP _ WMT <2> and the second internal read latch address signal ilapt _ WMT <2> as the second read column signal AYP _ WMT <2> in response to the read resultant signal RD _ SUM. The second column signal generation circuit 532 may output the second read latch address signal LATP _ WMT <2> and the second internal read latch address signal ilapt _ WMT <2> as the second read column signal AYP _ WMT <2> if the read synthesis signal RD _ SUM is enabled to have a logic "high" level. The second column signal generation circuit 532 may output the second write latch address signal LATP _ BG <2> and the second internal write latch address signal ILATP _ BG <2> as the second write column signal AYP _ BG <2> in response to the write synthesis signal WT _ SUM. The second column signal generation circuit 532 may output the second write latch address signal LATP _ BG <2> and the second internal write latch address signal ILATP _ BG <2> as the second write column signal AYP _ BG <2>, if the write synthesis signal WT _ SUM is enabled to have a logic "high" level. The second column signal generation circuit 532 may interrupt the input of the second write latch address signal LATP _ BG <2> and the second internal write latch address signal ILATP _ BG <2> in response to the write/read control signal WTRDB. The second column signal generation circuit 532 may interrupt the input of the second write latch address signal LATP _ BG <2> and the second internal write latch address signal ILATP _ BG <2>, if the write/read control signal WTRDB is enabled to have a logic "high" level.

The third column signal generating circuit 533 may output the third read latch address signal LATP _ WMT <3> and the third internal read latch address signal ilapt _ WMT <3> as the third read column signal AYP _ WMT <3> in response to the read resultant signal RD _ SUM. If the read synthesis signal RD _ SUM is enabled to have a logic "high" level, the third column signal generating circuit 533 may output the third read latch address signal LATP _ WMT <3> and the third internal read latch address signal ilapt _ WMT <3> as the third read column signal AYP _ WMT <3 >. The third column signal generating circuit 533 may output the third write latch address signal LATP _ BG <3> and the third internal write latch address signal ILATP _ BG <3> as the third write column signal AYP _ BG <3> in response to the write synthesis signal WT _ SUM. The third column signal generating circuit 533 may output the third write latch address signal LATP _ BG <3> and the third internal write latch address signal ILATP _ BG <3> as the third write column signal AYP _ BG <3>, if the write synthesis signal WT _ SUM is enabled to have a logic "high" level. The third column signal generating circuit 533 may interrupt the input of the third write latch address signal LATP _ BG <3> and the third internal write latch address signal ILATP _ BG <3> in response to the write/read control signal WTRDB. The third column signal generating circuit 533 may interrupt the input of the third write latch address signal LATP _ BG <3> and the third internal write latch address signal ILATP _ BG <3>, if the write/read control signal WTRDB is enabled to have a logic "high" level.

The fourth column signal generation circuit 534 may output the fourth read latch address signal LATP _ WMT <4> and the fourth internal read latch address signal ilapt _ WMT <4> as the fourth read column signal AYP _ WMT <4> in response to the read resultant signal RD _ SUM. The fourth column signal generation circuit 534 may output the fourth read latch address signal LATP _ WMT <4> and the fourth internal read latch address signal ilapt _ WMT <4> as the fourth read column signal AYP _ WMT <4> if the read synthesis signal RD _ SUM is enabled to have a logic "high" level. The fourth column signal generation circuit 534 may output the fourth write latch address signal LATP _ BG <4> and the fourth internal write latch address signal ILATP _ BG <4> as the fourth write column signal AYP _ BG <4> in response to the write synthesis signal WT _ SUM. The fourth column signal generation circuit 534 may output the fourth write latch address signal LATP _ BG <4> and the fourth internal write latch address signal ILATP _ BG <4> as the fourth write column signal AYP _ BG <4>, if the write synthesis signal WT _ SUM is enabled to have a logic "high" level. The fourth column signal generation circuit 534 may interrupt the input of the fourth write latch address signal LATP _ BG <4> and the fourth internal write latch address signal ILATP _ BG <4> in response to the write/read control signal WTRDB. The fourth column signal generation circuit 534 may interrupt the input of the fourth write latch address signal LATP _ BG <4> and the fourth internal write latch address signal ILATP _ BG <4>, if the write/read control signal WTRDB is enabled to have a logic "high" level.

Referring to fig. 13, the first column signal generating circuit 531 may include a control signal generating circuit 5311, an internal read signal generating circuit 5312, an internal write signal generating circuit 5313, and a selection/transmission circuit 5314.

The control signal generation circuit 5311 may generate a first control signal CON <1> that is enabled in response to the first read latch address signal LATP _ WMT <1> and the first internal read latch address signal ILATP _ WMT <1 >. The control signal generation circuit 5311 may generate the first control signal CON <1>, which is enabled to have a logic "high" level if any one of the first read latch address signal LATP _ WMT <1> and the first internal read latch address signal ilapt _ WMT <1> input to the control signal generation circuit 5311 has a logic "high" level.

The control signal generation circuit 5311 may generate the first control signal CON <1> from the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1> in response to the write/read control signal WTRDB. The control signal generation circuit 5311 may generate the first control signal CON <1> from the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1>, if the write/read control signal WTRDB is disabled to have a logic "low" level. If the write/read control signal WTRDB is enabled to have a logic "high" level, the control signal generation circuit 5311 may interrupt the input of the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1> to generate the first control signal CON <1> having a logic "low" level.

The control signal generation circuit 5311 may generate the second control signal CON <2> from the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1 >. The control signal generation circuit 5311 may generate the second control signal CON <2>, which is enabled to have a logic "high" level if any one of the first write latch address signal LATP _ BG <1> and the first internal write latch address signal ILATP _ BG <1> input to the control signal generation circuit 5311 has a logic "high" level.

The internal read signal generation circuit 5312 may latch the read synthesis signal RD _ SUM in response to the first control signal CON <1> to generate the internal read signal IRD. The internal read signal generation circuit 5312 may latch the read synthesis signal RD _ SUM to generate the internal read signal IRD if the first control signal CON <1> is enabled to have a logic "high" level.

The internal write signal generation circuit 5313 may latch the write synthesis signal WT _ SUM in response to the second control signal CON <2> to generate the internal write signal IWT. If the second control signal CON <2> is enabled to have a logic "high" level, the internal write signal generation circuit 5313 may latch the write synthesis signal WT _ SUM to generate the internal write signal IWT.

The select/transmit circuit 5314 may output the internal read signal IRD (or the internal write signal IWT) as the first read column signal AYP _ WMT <1> (or the first write column signal AYP _ BG <1>) in response to the flag signal MWTF. If the flag signal MWTF is enabled, the select/transmit circuit 5314 may output the internal read signal IRD as the first read column signal AYP _ WMT <1 >. If the flag signal MWTF is disabled, the select/transmit circuit 5314 may output the internal write signal IWT as the first write column signal AYP _ BG <1 >. The flag signal WMTF may be enabled when an internal read operation is performed.

Each of the second, third, and fourth column signal generating circuits 532, 533, and 534 may be implemented to have substantially the same configuration as the first column signal generating circuit 531 illustrated in fig. 13, except for input/output (I/O) signals thereof. Accordingly, each of the second, third, and fourth column signal generating circuits 532, 533, and 534 may perform substantially the same operation as the first column signal generating circuit 531. Therefore, detailed descriptions of the second, third, and fourth column signal generating circuits 532, 533, and 534 are omitted here.

The operation of the semiconductor device according to one embodiment is described below with reference to fig. 14 in conjunction with internal read and write operations performed by the activation of the first and third banks BK1 and BK 3.

At time "T1", command/address signals CA <1: N > having a combination of logic levels for performing a masked-write operation may be input to the command decoder 1.

The command decoder 1 may decode the command/address signals CA <1: N > in synchronization with the internal clock signal ICLK and the inverted internal clock signal ICLKB to generate the masked write signal EMWT.

At time "T2", the read/write control circuit 2 may generate the first read pulse RDAYP in response to the masked write signal EMWT generated at time "T1".

At time "T3", the latch pulse generation circuit 3 may latch the first read pulse RDAYP, and may delay a latch pulse of the first read pulse RDAYP by a predetermined period of time to generate a first read latch pulse ADD _ LATP _ MWT.

The bank control circuit 51 of the column control circuit 5 may generate a first read latch address signal LATP _ MWT <1> from the first read bank address signal BA _ MWT <1> in response to the first read latch pulse ADD _ LATP _ MWT.

The signal synthesizing circuit 52 of the column control circuit 5 may synthesize the first read pulse RDAYP and the second read pulse IRDAYP to generate the read synthesized signal RD _ SUM.

The column signal generation circuit 53 of the column control circuit 5 may generate a first read column signal AYP _ MWT <1> from the first read latch address signal LATP _ MWT <1> in response to the read resultant signal RD _ SUM.

The first bank BK1 of the core circuit 6 may perform an internal read operation in response to the first read column signal AYP _ MWT <1 >. The burst length of data output from the first bank BK1 during the internal read operation may be set to "16". The burst length "16" means that 16 bits of data are output from the first bank BK1 every time an internal read operation is performed.

At time "T4", the read/write control circuit 2 may generate the second read pulse IRDAYP in response to the masked write signal EMWT generated at time "T1".

At time "T5", the latch pulse generation circuit 3 may latch the second read pulse IRDAYP and may delay the latch pulse of the second read pulse IRDAYP by a predetermined period of time to generate the second read latch pulse ADD _ ILATP _ MWT.

The bank control circuit 51 of the column control circuit 5 may generate the third internal read latch address signal ILATP _ MWT <3> from the third read bank address signal BA _ MWT <3> in response to the second read latch pulse IADD _ LATP _ MWT.

The signal synthesizing circuit 52 of the column control circuit 5 may synthesize the first read pulse RDAYP and the second read pulse IRDAYP to generate the read synthesized signal RD _ SUM.

The column signal generation circuit 53 of the column control circuit 5 may generate a third read column signal AYP _ MWT <3> from the third internal read latch address signal ILATP _ MWT <3> in response to the read resultant signal RD _ SUM.

The third bank BK3 of the core circuit 6 may perform an internal read operation in response to the third read column signal AYP _ MWT <3 >. The burst length of data output from the third bank BK3 during the internal read operation may be set to "16". The burst length "16" means that 16 bits of data are output from the third bank BK3 every time an internal read operation is performed.

Meanwhile, the semiconductor device according to one embodiment may perform a 16 burst length operation performed at time "T3" and another 16 burst length operation performed at time "T5" in response to the masked write signal EMWT input at time "T1", thereby performing a 32 burst length operation. The 32-burst length operation means an operation of outputting 32 bits of data from the core circuit 6 every time the masked write signal EMWT is generated once.

At time "T6", the read/write control circuit 2 may generate the first write pulse WTAYP in response to the masked write signal EMWT generated at time "T1".

At time "T7", the latch pulse generation circuit 3 may latch the first write pulse WTAYP and may delay the latch pulse of the first write pulse WTAYP by a predetermined period of time to generate the first write latch pulse ADD _ ILATP _ BG.

The bank control circuit 51 of the column control circuit 5 can generate a first write latch address signal LATP _ BG <1> from the first write bank address signal BA <1> in response to the first write latch pulse ADD _ LATP _ BG.

The signal synthesizing circuit 52 of the column control circuit 5 may synthesize the first write pulse WTP and the second write pulse IWTAYP to generate a write synthesized signal WT _ SUM.

The column signal generation circuit 53 of the column control circuit 5 may generate a first write column signal AYP _ BG <1> from the first write latch address signal LATP _ BG <1> in response to the write synthesis signal WT _ SUM.

The first bank BK1 of the core circuit 6 may perform a write operation in response to the first write column signal AYP _ BG <1 >. The burst length of data input to the first bank BK1 during a write operation may be set to "16". The burst length "16" means that data of 16 bits is input to the first bank BK1 every time a write operation is performed.

At time "T8", the read/write control circuit 2 may generate the second write pulse IWTAYP in response to the masked write signal EMWT generated at time "T1".

At time "T9", the latch pulse generation circuit 3 may latch the second write pulse IWTAYP and may delay the latch pulse of the second write pulse IWTAYP by a predetermined period of time to generate a second write latch pulse IADD _ LATP _ BG.

The bank control circuit 51 of the column control circuit 5 may generate a third internal write latch address signal ILATP _ BG <3> from the third write bank address signal BA <3> in response to the second write latch pulse IADD _ LATP _ BG.

The signal synthesizing circuit 52 of the column control circuit 5 may synthesize the first write pulse WTAYP and the second write pulse IWTAYP to generate a write synthesized signal WT _ SUM.

The column signal generation circuit 53 of the column control circuit 5 may generate a third write column signal AYP _ BG <3> from the third internal write latch address signal ILATP _ BG <3> in response to the write synthesis signal WT _ SUM.

The third bank BK3 of the core circuit 6 may perform a write operation in response to the third write column signal AYP _ BG <3 >. The burst length of data input to the third bank BK3 during a write operation may be set to "16". The burst length "16" means that data of 16 bits is input to the third bank BK3 every time a write operation is performed.

Meanwhile, the semiconductor device according to one embodiment may perform a 16 burst length operation performed at time "T7" and another 16 burst length operation performed at time "T9" in response to the masked write signal EMWT input at time "T1", thereby performing a 32 burst length operation. The 32-burst length operation means an operation of inputting 32 bits of data to the core circuit 6 every time the masked write signal EMWT is generated once.

Further, the semiconductor device according to one embodiment can sequentially perform an internal read operation for outputting 32-bit data from the core circuit 6 and a write operation for storing 32-bit data in the core circuit 6 each time the masked write signal EMWT is generated once.

As described above, the semiconductor device according to one embodiment may sequentially generate the column signal for performing the internal read operation and the column signal for performing the write operation during the masked write operation, thereby preventing the column signal for the internal read operation from colliding with the column signal for the write operation. Therefore, the reliability of the mask write operation of the semiconductor device can be improved.

The semiconductor device described with reference to fig. 1 to 14 may be applied to an electronic system including a memory system, a graphic system, a computing system, a mobile system, and the like. For example, as shown in fig. 15, an electronic system 1000 according to an embodiment may include a data storage circuit 1001, a memory controller 1002, a buffer memory 1003, and an input/output (I/O) interface 1004.

The data storage circuit 1001 may store data output from the memory controller 1002 or may read and output the stored data to the memory controller 1002 according to a control signal output from the memory controller 1002. The data storage circuit 1001 may include the semiconductor device shown in fig. 1. Meanwhile, the data storage circuit 1001 may include a nonvolatile memory capable of retaining its stored data even when its power supply is interrupted. The nonvolatile memory may be a flash memory such as a NOR type flash memory or a NAND type flash memory, a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM), or the like.

The memory controller 1002 may receive a command output from an external device (e.g., a host device) through the I/O interface 1004 and may decode the command output from the host device to control an operation for inputting data into the data storage circuit 1001 or the buffer memory 1003 or an operation for outputting data stored in the data storage circuit 1001 or the buffer memory 1003. Although fig. 15 shows the memory controller 1002 having a single module, the memory controller 1002 may include one controller for controlling the data storage circuit 1001 and another controller for controlling the buffer memory 1003 including a volatile memory.

The buffer memory 1003 may temporarily store data to be processed by the memory controller 1002. That is, the buffer memory 1003 can temporarily store data output from the data storage circuit 1001 or data to be input to the data storage circuit 1001. The buffer memory 1003 may store data output from the memory controller 1002 according to a control signal. The buffer memory 1003 may read the stored data and output it to the memory controller 1002. The buffer memory 1003 may include a volatile memory such as a Dynamic Random Access Memory (DRAM), a mobile DRAM, or a Static Random Access Memory (SRAM).

The I/O interface 1004 may physically and electrically connect the memory controller 1002 to an external device (i.e., a host). Accordingly, the memory controller 1002 may receive control signals and data provided from an external device (i.e., a host) through the I/O interface 1004 and may output data output from the memory controller 1002 to the external device (i.e., the host) through the I/O interface 1004. That is, electronic system 1000 may communicate with a host through I/O interfaces 1004. The I/O interface 1004 may include any of a variety of interface protocols, such as Universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnect-Express (PCI-E), serial attached SCSI (sas), serial AT attachment (SATA), parallel AT attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Integrated Drive Electronics (IDE).

The electronic system 1000 may be used as a secondary storage device for a host or an external storage device. The electronic system 1000 may include a Solid State Disk (SSD), a USB memory, a Secure Digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded multimedia card (eMMC), or a Compact Flash (CF) card, etc.