阅读说明：本技术 半导体封装件 (Semiconductor package ) 是由 金雄来 高福林 金起业 李釉钟 于 2018-12-12 设计创作，主要内容包括：半导体封装件包括第一半导体芯片和第二半导体芯片。第一半导体芯片具有位于第一半导体芯片的第一区域处的第一焊盘区域和位于第一半导体芯片的第二区域处的第二焊盘区域。第二半导体芯片具有位于第二半导体芯片的第一区域的第三焊盘区域和位于第二半导体芯片的第二区域的第四焊盘区域。第二半导体芯片层叠在第一半导体芯片上,以在第一横向方向上相对于第一半导体芯片偏移。(The semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first pad region located at a first region of the first semiconductor chip and a second pad region located at a second region of the first semiconductor chip. The second semiconductor chip has a third pad region located at the first region of the second semiconductor chip and a fourth pad region located at the second region of the second semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip so as to be offset in the first lateral direction with respect to the first semiconductor chip.)

1. A semiconductor package, comprising:

a first semiconductor chip having a first pad region located in a first region of the first semiconductor chip and a second pad region located in a second region of the first semiconductor chip; and

a second semiconductor chip having a third pad region located at a first region of the second semiconductor chip and a fourth pad region located at a second region of the second semiconductor chip,

wherein the second semiconductor chip is stacked on the first semiconductor chip and is offset from the first semiconductor chip in a horizontal direction.

2. The semiconductor package according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are vertically stacked in a zigzag manner to expose the first pad region, the second pad region, the third pad region, and the fourth pad region.

3. The semiconductor package according to claim 1, wherein,

wherein the first region of the first semiconductor chip is a first edge region of the first semiconductor chip;

wherein the second region of the first semiconductor chip is a second edge region adjacent to the first edge region of the first semiconductor chip;

wherein the first region of the second semiconductor chip is a first edge region of the second semiconductor chip; and

wherein the second region of the second semiconductor chip is a second edge region adjacent to the first edge region of the second semiconductor chip.

4. The semiconductor package according to claim 1, wherein,

wherein the first pad region is provided to extend in a first direction, and the second pad region is provided to extend in a second direction that intersects the first direction; and

wherein the third pad region is disposed to extend in the first direction, and the fourth pad region is disposed to extend in the second direction.

5. The semiconductor package according to claim 1, wherein,

wherein the first pad region and the third pad region are point-symmetric with respect to a center point of the first semiconductor chip and the second semiconductor chip; and

wherein the second pad region and the fourth pad region are point-symmetric with respect to a center point of the first semiconductor chip and the second semiconductor chip.

6. The semiconductor package according to claim 1, wherein the first semiconductor chip comprises:

a first control circuit disposed adjacent to the first pad region; configured to decode the command to generate a first write signal and a first read signal; configured to decode the address to generate a first selection address and a second selection address and a first bank group address to a fourth bank group address; and configured to receive or output data;

a first storage region located at a side of the first control circuit facing away from the first pad region and configured to include first to fourth bank groups activated according to the first to fourth bank group addresses if the first selection address is enabled; and

a second storage region located at a side of the first control circuit facing away from the first pad region and configured to include fifth to eighth bank groups activated according to the first to fourth bank group addresses if the second selection address is enabled.

7. The semiconductor package according to claim 6,

wherein the first through eighth bank groups are arranged in a second horizontal direction of the first and second storage regions; and

wherein a plurality of memory banks included in each of the first to eighth memory bank groups are arranged in a first horizontal direction of the first or second memory area.

8. The semiconductor package according to claim 6, wherein the first storage region and the second storage region are disposed adjacent to each other.

9. The semiconductor package according to claim 6, wherein the first to eighth bank groups are configured to receive or output the data through first to eighth input/output lines, respectively.

10. The semiconductor package according to claim 1, wherein the second semiconductor chip comprises:

a second control circuit disposed adjacent to the third pad region; configured to decode the command to generate a second write signal and a second read signal; configured to decode the addresses to generate third and fourth selection addresses and fifth to eighth bank group addresses; and configured to receive or output data;

a third memory region located at a side of the second control circuit facing away from the third pad region and configured to include ninth to twelfth bank groups activated according to the fifth to eighth bank group addresses if the third selection address is enabled; and

a fourth memory region located at a side of the second control circuit facing away from the third pad region and configured to include thirteenth through sixteenth bank groups activated according to the fifth through eighth bank group addresses if the fourth selection address is enabled.

11. The semiconductor package according to claim 10, wherein,

wherein the ninth through sixteenth bank groups are arranged in a second horizontal direction of the third and fourth storage regions; and

wherein a plurality of memory banks included in each of the ninth through sixteenth memory bank groups are arranged in the first horizontal direction of the third or fourth memory area.

12. The semiconductor package according to claim 10, wherein the third and fourth storage regions are disposed adjacent to each other.

13. The semiconductor package according to claim 10, wherein the ninth to sixteenth bank groups are configured to receive or output the data through ninth to sixteenth input/output (I/O) lines, respectively.

14. A semiconductor package, comprising:

a first semiconductor chip configured to include a first pad region extending in a first direction and a second pad region extending in a second direction, the second direction intersecting the first direction; configured to receive commands and addresses through the first pad region; and configured to receive or output data through the first pad region;

a second semiconductor chip configured to include a third pad region extending in the first direction and a fourth pad region extending in the second direction; configured to receive commands and addresses through the third pad region; and configured to receive or output data through the third pad region;

a third semiconductor chip configured to include a fifth pad region extending in the first direction and a sixth pad region extending in the second direction; configured to receive commands and addresses through the fifth pad region; and configured to receive or output data through the fifth pad region; and

a fourth semiconductor chip configured to include a seventh pad region extending in the first direction and an eighth pad region extending in the second direction; configured to receive commands and addresses through the seventh pad region; and configured to receive or output data through the seventh pad region,

wherein the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are sequentially and vertically stacked on the first semiconductor chip in a zigzag manner.

15. The semiconductor package according to claim 14, wherein,

wherein the second semiconductor chip is offset in a first lateral direction relative to the first semiconductor chip;

wherein the third semiconductor chip is offset relative to the second semiconductor chip in a second lateral direction opposite the first lateral direction; and

wherein the fourth semiconductor chip is offset in the first lateral direction relative to the third semiconductor chip.

16. The semiconductor package according to claim 14, wherein,

wherein the second and fourth semiconductor chips are offset in a first lateral direction relative to the first and third semiconductor chips; and

wherein the first and third semiconductor chips are offset relative to the second and fourth semiconductor chips in a second lateral direction opposite the first lateral direction.

17. The semiconductor package according to claim 14, wherein the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are stacked on the first semiconductor chip in a zigzag manner to expose the first to eighth pad regions.

18. The semiconductor package according to claim 14, wherein,

wherein the first pad region is located at a first edge region of the first semiconductor chip, and the second pad region is located at a second edge region of the first semiconductor chip adjacent to the first edge region of the first semiconductor chip;

wherein the third pad region is located at a first edge region of the second semiconductor chip, and the fourth pad region is located at a second edge region of the second semiconductor chip adjacent to the first edge region of the second semiconductor chip;

wherein the fifth pad region is located at a first edge region of the third semiconductor chip, and the sixth pad region is located at a second edge region of the third semiconductor chip adjacent to the first edge region of the third semiconductor chip; and

wherein the seventh pad region is located at a first edge region of the fourth semiconductor chip, and the eighth pad region is located at a second edge region of the fourth semiconductor chip adjacent to the first edge region of the fourth semiconductor chip.

19. The semiconductor package according to claim 14, wherein the first semiconductor chip further comprises:

a first control circuit disposed adjacent to the first pad region; configured to decode the command to generate a first write signal and a first read signal; configured to decode the addresses to generate first and second selection addresses and first to fourth bank group addresses; and configured to receive or output the data;

a first storage region located at a side of the first control circuit facing away from the first pad region and configured to include first to fourth bank groups activated according to the first to fourth bank group addresses if the first selection address is enabled; and

a second storage region located at a side of the first control circuit facing away from the first pad region and configured to include fifth to eighth bank groups activated according to the first to fourth bank group addresses if the second selection address is enabled.

20. The semiconductor package according to claim 14, wherein the second semiconductor chip further comprises:

a second control circuit disposed adjacent to the third pad region; configured to decode the command to generate a second write signal and a second read signal; configured to decode the addresses to generate third and fourth selection addresses and fifth to eighth bank group addresses; and configured to receive or output the data;

a third memory region located at a side of the second control circuit facing away from the third pad region and configured to include ninth to twelfth bank groups activated according to the fifth to eighth bank group addresses if the third selection address is enabled; and

a fourth memory region located at a side of the second control circuit facing away from the third pad region and configured to include thirteenth through sixteenth bank groups activated according to the fifth through eighth bank group addresses if the fourth selection address is enabled.

21. The semiconductor package according to claim 14, wherein the third semiconductor chip further comprises:

a third control circuit disposed adjacent to the fifth pad region; configured to decode the command to generate a third write signal and a third read signal; configured to decode the addresses to generate fifth and sixth selection addresses and ninth to twelfth bank group addresses; and configured to receive or output the data;

a fifth memory region located on a side of the third control circuit opposite to the fifth pad region and configured to include seventeenth to twentieth bank groups activated according to the ninth to twelfth bank group addresses if the fifth selection address is enabled; and

a sixth storage region located on a side of the third control circuit opposite to the fifth pad region and configured to include twenty-first to twenty-fourth bank groups activated according to the ninth to twelfth bank group addresses if the sixth selection address is enabled.

22. The semiconductor package according to claim 14, wherein the fourth semiconductor chip further comprises:

a fourth control circuit disposed adjacent to the seventh pad region; configured to decode the command to generate a fourth write signal and a fourth read signal; configured to decode the addresses to generate seventh and eighth select addresses and thirteenth to sixteenth bank group addresses; and configured to receive or output the data;

a seventh storage region located at a side of the fourth control circuit facing away from the seventh pad region and configured to include twenty-fifth to twenty-eighth bank groups activated according to the thirteenth to sixteenth bank group addresses if the seventh selection address is enabled; and

an eighth storage region located at a side of the fourth control circuit facing away from the seventh pad region and configured to include twenty-ninth to thirty-second bank groups activated according to the thirteenth to sixteenth bank group addresses if an eighth selection address is enabled.

Technical Field

Embodiments of the present disclosure generally relate to a semiconductor package including a plurality of semiconductor chips stacked vertically.

Background

In general, each semiconductor device such as a Dynamic Random Access Memory (DRAM) apparatus may include a plurality of bank groups composed of a cell array selected by an address. Each bank group may be implemented to include a plurality of banks. The semiconductor device may select any one of a plurality of bank groups, and may perform a column operation for outputting data stored in a cell array included in the selected bank group through an input/output (I/O) line. Semiconductor devices (also referred to as semiconductor chips) may be vertically stacked on a package substrate and may be packaged with a molding layer to provide a semiconductor package. Recently, various techniques for stacking semiconductor chips have been proposed to improve the performance of semiconductor packages.

Fig. 1 is a sectional view illustrating a conventional semiconductor package including a plurality of semiconductor chips vertically stacked.

Referring to fig. 1, a conventional semiconductor package may include first to third semiconductor chips 200, 300 and 400 vertically stacked. The first semiconductor chip 200 is stacked on a surface of the package substrate 100. The first semiconductor chip 200 includes a first body and a pad P disposed on a top surface of the first body facing away from the substrate 100, and the pad P is electrically connected to the package substrate 100 through a wire W.

The second semiconductor chip 300 is stacked on the top surface of the first semiconductor chip 200 facing away from the package substrate 100. The second semiconductor chip 300 includes a second body and a pad P disposed on a top surface of the second body facing away from the first semiconductor chip 200, and the pad P of the second semiconductor chip 300 is electrically connected to the package substrate 100 through a wire W.

The third semiconductor chip 400 is stacked on the top surface of the second semiconductor chip 300 facing away from the first semiconductor chip 200. The third semiconductor chip 400 includes a third body and a pad P disposed on a top surface of the third body facing away from the second semiconductor chip 300, and the pad P of the third semiconductor chip 400 is electrically connected to the package substrate 100 through a wire W.

In the conventional semiconductor package shown in fig. 1, since there are wires W provided to electrically connect the first to third semiconductor chips 200, 300, and 400 with the substrate 100, there is a limit to reduce the distance H between the first to third semiconductor chips 200, 300, and 400.

Disclosure of Invention

According to an embodiment, a semiconductor package may include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may have a first pad region located at a first region of the first semiconductor chip and a second pad region located at a second region of the first semiconductor chip. The second semiconductor chip may have a third pad region located at the first region of the second semiconductor chip and a fourth pad region located at the second region of the second semiconductor chip. The second semiconductor chip may be stacked on the first semiconductor chip so as to be offset with respect to the first semiconductor chip in the first lateral direction.

According to an embodiment, a semiconductor package may include a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip. The first semiconductor chip may be configured to include a first pad region extending in a first direction and a second pad region extending in a second direction intersecting the first direction, to receive commands and addresses through the first pad region, and to receive or output data through the first pad region. The second semiconductor chip may be configured to include a third pad region extending in the first direction and a second pad region extending in the second direction, to receive a command and an address through the third pad region, and to receive or output data through the third pad region. The third semiconductor chip may be configured to include a fifth pad region extending in the first direction and a sixth pad region extending in the second direction, to receive a command and an address through the fifth pad region, and to receive or output data through the fifth pad region. The fourth semiconductor chip may be configured to include a seventh pad region extending in the first direction and an eighth pad region extending in the second direction, to receive a command and an address through the seventh pad region, and to receive or output data through the seventh pad region. The second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip may be sequentially and vertically stacked on the first semiconductor chip in a zigzag manner.

Drawings

Fig. 1 is a sectional view showing the structure of a conventional semiconductor package.

Fig. 2 is a sectional view illustrating a structure of a semiconductor package according to an embodiment of the present disclosure.

Fig. 3 is a plan view illustrating a structure of a first semiconductor chip included in the semiconductor package of fig. 2.

Fig. 4 is a plan view illustrating a structure of a second semiconductor chip included in the semiconductor package of fig. 2.

Fig. 5 is a block diagram illustrating a structure of a first memory region included in the first semiconductor chip of fig. 3.

Fig. 6 is a block diagram illustrating a structure of a second memory region included in the first semiconductor chip of fig. 3.

Fig. 7 is a plan view illustrating a stacked state of a first semiconductor chip and a second semiconductor chip included in a semiconductor package according to an embodiment of the present disclosure.

Fig. 8 is a block diagram illustrating a structure of an electronic system including the semiconductor package shown in fig. 1 to 7.

Detailed Description

Various embodiments of the present disclosure will be described below with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

As shown in fig. 2, the semiconductor package 1 according to the embodiment may include a substrate SUB, a first semiconductor CHIP1, a second semiconductor CHIP2, a third semiconductor CHIP3, and a fourth semiconductor CHIP 4.

The substrate SUB may include a plurality of solder balls SB. The substrate SUB may receive a signal from an external device through the solder balls SB or may output a signal to an external device through the solder balls SB.

The first semiconductor CHIP1 may be stacked on a surface of the substrate SUB. The first semiconductor CHIP1 may include a first body and a first pad P1, the first pad P1 being disposed on a top surface of the first body facing away from the substrate SUB. The first pad P1 may be electrically connected to the substrate SUB by a first wire W1. Accordingly, the first semiconductor CHIP1 may receive a signal from the substrate SUB or may output a signal to the substrate SUB through the first pad P1 and the first wire W1.

A second semiconductor CHIP2 may be stacked on the top surface of the first semiconductor CHIP1 facing away from the substrate SUB. The second semiconductor CHIP2 may include a second body and a second pad P2, the second pad P2 being disposed on a top surface of the second body facing away from the first semiconductor CHIP 1. The second pad P2 may be electrically connected to the substrate SUB by a second wire W2. Accordingly, the second semiconductor CHIP2 may receive a signal from the substrate SUB or may output a signal to the substrate SUB through the second pad P2 and the second wire W2.

A third semiconductor CHIP3 may be stacked on the top surface of the second semiconductor CHIP2 facing away from the first semiconductor CHIP 1. The third semiconductor CHIP3 may include a third body and third pads P3, the third pads P3 being disposed on a top surface of the third body facing away from the second semiconductor CHIP 2. The third pad P3 may be electrically connected to the substrate SUB by a third wire W3. Accordingly, the third semiconductor CHIP3 may receive a signal from the substrate SUB or may output a signal to the substrate SUB through the third pad P3 and the third wire W3.

A fourth semiconductor CHIP4 may be stacked on a top surface of the third semiconductor CHIP3 facing away from the second semiconductor CHIP 2. The fourth semiconductor CHIP4 may include a fourth body and fourth pads P4, the fourth pads P4 being disposed on a top surface of the fourth body facing away from the third semiconductor CHIP 3. The fourth pad P4 may be electrically connected to the substrate SUB by a fourth wire W4. Accordingly, the fourth semiconductor CHIP4 may receive a signal from the substrate SUB or may output a signal to the substrate SUB through the fourth pad P4 and the fourth wire W4.

The first to fourth semiconductor CHIPs CHIP1, CHIP2, CHIP3, and CHIP4 may be vertically stacked on the substrate SUB in a zigzag manner to expose the first to fourth pads P1, P2, P3, and P4 disposed on the edges of the first to fourth bodies of the first to fourth semiconductor CHIPs CHIP1, CHIP2, CHIP3, and CHIP 4.

For example, the second semiconductor CHIP2 may be rotated 180 degrees using the first semiconductor CHIP1 as a reference CHIP in a plan view, and the rotated second semiconductor CHIP2 may be stacked on the first semiconductor CHIP1 to be laterally shifted with respect to the first semiconductor CHIP1 such that the first pad P1 of the first semiconductor CHIP1 is exposed. In a plan view, the third semiconductor CHIP3 may be rotated 180 degrees using the second semiconductor CHIP2 as a reference CHIP, and the rotated third semiconductor CHIP3 may be stacked on the second semiconductor CHIP2 to be laterally offset with respect to the second semiconductor CHIP2 such that the second pads P2 of the second semiconductor CHIP2 are exposed. In a plan view, the fourth semiconductor CHIP4 may be rotated 180 degrees using the third semiconductor CHIP3 as a reference CHIP, and the rotated fourth semiconductor CHIP4 may be stacked on the third semiconductor CHIP3 to be laterally offset with respect to the third semiconductor CHIP3 such that the third pads P3 of the third semiconductor CHIP3 are exposed. That is, the second semiconductor CHIP2 may be stacked to be shifted in a first shift direction with respect to the first semiconductor CHIP1 to provide a space for bonding the first conductive wire W1 to the first pad P1, and the third semiconductor CHIP3 may be stacked to be shifted in a second shift direction opposite to the first shift direction with respect to the second semiconductor CHIP2 to provide a space for bonding the second conductive wire W2 to the second pad P2. In addition, the fourth semiconductor CHIP4 may be stacked to be offset in the first offset direction with respect to the third semiconductor CHIP3 to provide a space for bonding the third wire W3 to the third pad P3. Accordingly, the first to fourth semiconductor CHIPs CHIP1, CHIP2, CHIP3, and CHIP4 may be vertically stacked on the substrate SUB in a zigzag manner to expose the first to fourth pads P1, P2, P3, and P4.

Referring to fig. 3, the first semiconductor CHIP1 may include a first pad region 110, a second pad region 120, a first control circuit 130, a first storage region 140, and a second storage region 150.

The first pad region 110 may be located at a first region of the first semiconductor CHIP 1. The first region may correspond to any one of four edge regions of the first semiconductor CHIP1, for example, a first edge region (corresponding to an upper edge region in the plan view of fig. 3) when viewed from a plan view.

The first pad region 110 may include some of the first pads P1, and some of the first pads P1P 1 in the first pad region 110 may be electrically connected to the substrate SUB through some of the first wires W1 of the first wires W1. A command CMD and an address ADD may be input to the first semiconductor CHIP1 through the first pad P1 in the first pad region 110. The DATA may also be input to the first semiconductor CHIP1 or output from the first semiconductor CHIP1 through the first pad P1 in the first pad region 110.

The second pad region 120 may be located at a second region of the first semiconductor CHIP 1. The second region may correspond to another one of the four edge regions of the first semiconductor CHIP1, for example, a second edge region (corresponding to the right edge region in the plan view of fig. 3) when viewed from the plan view. In some other embodiments, the second region may be set as a left edge region in the plan view of fig. 3. When the first pads P1 in the first pad region 110 are aligned in the second horizontal direction in fig. 3, the first pads P1 in the second pad region 120 may be aligned in the first horizontal direction perpendicular to the second horizontal direction.

The second pad region 120 may include some of the first pads P1, and some of the first pads P1P 1 in the second pad region 120 may be electrically connected to the substrate SUB through some of the first wires W1 of the first wires W1. The power supply voltage VDD, the ground voltage VSS, and the option information OPT may be input to the first semiconductor CHIP1 through the first pad P1 in the second pad region 120. The power supply voltage VDD and the ground voltage VSS may be supplied to the first semiconductor CHIP1 through the first pad P1 in the second pad region 120. The optional information OPT corresponding to the operation information of the first semiconductor CHIP1 may be input to the first semiconductor CHIP1 through the first pad P1 in the second pad region 120. The option information OPT may include various information for performing the operation of the first semiconductor CHIP 1. For example, the optional information OPT may include information on a "x 4" mode, information on a "x 8" mode, information on a "x 16" mode, and the like, which are used to set the number of bits included in the DATA input to or output from the first semiconductor CHIP1 or 1 through the first pad region 110.

According to an embodiment, signals transmitted through the first and second pad regions 110 and 120 may be set to be different.

The first pad region 110 and the second pad region 120 may be disposed perpendicular to each other in a plan view. In some embodiments, the first pad region 110 and the second pad region 120 may be disposed substantially perpendicular to each other in a plan view. In some embodiments, the first pad region 110 and the second pad region 120, if extended, may be disposed to intersect each other in a plan view.

The first control circuit 130 may be disposed between the first pad region 110 and a storage region including the first storage region 140 and the second storage region 150.

The first control circuit 130 may receive a command CMD through the first pad area 110, and may decode the command CMD to generate a first write signal WT1 and a first read signal RD 1. The first control circuit 130 may receive an address ADD through the first pad region 110 and may decode the address ADD to generate first and second selection addresses SA <1:2>, first to fourth bank group addresses BGA <1:4>, and first to fourth bank addresses BKA <1:4 >. The first control circuit 130 may receive or output DATA through the first pad area 110.

The first semiconductor CHIP1 may provide a bank group mode, an 8 bank mode, and a 16 bank mode. The bank group may include a plurality of banks. For example, a bank group may include four banks. In the bank group mode, a column operation of one bank included in the bank group may be performed by one command. In the 8-bank mode, column operations of two banks respectively included in two independent bank groups are sequentially performed by one command. In the 16-bank mode, column operations of four banks respectively included in four independent bank groups are sequentially performed by one command.

In the 8-bank mode, the first control circuit 130 may generate two bank group addresses among the first to fourth bank group addresses BGA <1:4 >. For example, the first and third bank group addresses BGA <1> and BGA <3> may be simultaneously enabled in the 8-bank mode. In the 16-bank mode, the first control circuit 130 may generate one bank group address of the first to fourth bank group addresses BGA <1:4 >. For example, the first to fourth bank group addresses BGA <1:4> may be sequentially enabled in the 16 bank mode.

The first storage area 140 may be located at a side of the first control circuit 130 facing away from the first pad area 110 in a plan view.

The first storage region 140 may include first to fourth bank groups (BG 1, BG2, BG3, and BG4 of fig. 5) which are activated according to first to fourth bank group addresses BGA <1:4> if the first selection address SA <1> is enabled. The first to fourth bank groups (BG 1, BG2, BG3, and BG4 of fig. 5) may include first to sixteenth banks (BK 1 to BK16 of fig. 5) activated according to the first to fourth bank addresses BKA <1:4 >. The first storage region 140 may store DATA into first to fourth bank groups (BG 1, BG2, BG3, and BG4 of fig. 5), which are activated according to first to fourth bank group addresses BGA <1:4> if the first write signal WT1 is enabled and the first selection address SA <1> is enabled. The first storage region 140 may output DATA stored in first to fourth bank groups (BG 1, BG2, BG3, and BG4 of fig. 5) which are activated according to first to fourth bank group addresses BGA <1:4> if the first read signal RD1 is enabled and the first selection address SA <1> is enabled.

If the first selection address SA <1> is enabled in the 8 bank mode, the first storage region 140 may activate two bank groups of the first to fourth bank groups (BG 1, BG2, BG3, and BG4 in FIG. 5) according to the first to fourth bank group addresses BGA <1:4> to receive or output DATA DATA. If the first selection address SA <1> is enabled in the 16 bank mode, the first storage region 140 may activate one of the first to fourth bank groups (BG 1, BG2, BG3, and BG4 in FIG. 5) according to the first to fourth bank group addresses BGA <1:4> to receive or output DATA DATA. The number of bits included in the DATA input or output whenever a write operation or a read operation is performed may be set to have a burst length of "16" or "32".

The second storage region 150 may be located at a side of the first control circuit 130 facing away from the first pad region 110 in a plan view.

The second storage region 150 may include fifth to eighth bank groups (BG 5, BG6, BG7, and BG8 of fig. 6) which are activated according to the first to fourth bank group addresses BGA <1:4> if the second selection address SA <2> is enabled. The fifth to eighth bank groups (BG 5, BG6, BG7, and BG8 of fig. 6) may include seventeenth to thirty-second banks (BK 17 to BK32 of fig. 6) activated according to the first to fourth bank addresses BKA <1:4 >. The second memory region 150 may store DATA into fifth to eighth bank groups (BG 5, BG6, BG7, and BG8 of fig. 6), which are activated according to the first to fourth bank group addresses BGA <1:4> if the first write signal WT1 is enabled and the second selection address SA <2> is enabled. If the first read signal RD1 is enabled and the second selection address SA <2> is enabled, the second memory region 150 may output DATA stored in fifth to eighth bank groups (BG 5, BG6, BG7, and BG8 of fig. 6) activated according to the first to fourth bank group addresses BGA <1:4 >.

If the second selection address SA <2> is enabled in the 8 bank mode, the second storage region 150 may activate two bank groups of the fifth to eighth bank groups (BG 5, BG6, BG7, and BG8 in FIG. 6) according to the first to fourth bank group addresses BGA <1:4> to receive or output DATA DATA. If the second selection address SA <2> is enabled in the 16 bank mode, the second storage region 150 may activate one bank group of the fifth to eighth bank groups (BG 5, BG6, BG7, and BG8 of FIG. 6) according to the first to fourth bank group addresses BGA <1:4> to receive or output DATA DATA. The number of bits included in the DATA input or output whenever a write operation or a read operation is performed may be set to have a burst length of "16" or "32".

The first and second storage regions 140 and 150 may be located at a side of the first control circuit 130 facing away from the first pad region 110 to be adjacent to each other in a plan view.

Referring to fig. 4, the second semiconductor CHIP2 may include a third pad region 210, a fourth pad region 220, a second control circuit 230, a third storage region 240, and a fourth storage region 250.

The third pad region 210 may be located at the first region of the second semiconductor CHIP 2. The first region of the second semiconductor CHIP2 may correspond to any one of four edge regions of the second semiconductor CHIP2, for example, a first edge region when viewed from a plan view (corresponding to an upper edge region in a plan view of fig. 3).

The third pad region 210 may include some of the second pads P2, and the second pads P2 in the third pad region 210 may be electrically connected to the substrate SUB through some of the second wires W2. The third pad region 210 may be configured to have substantially the same function as the first pad region 110. Therefore, a description of the third pad region 210 will be omitted hereinafter.

The fourth pad region 220 may be located at a second region of the second semiconductor CHIP 2. The second region of the second semiconductor CHIP2 may correspond to another one of four edge regions of the second semiconductor CHIP2, for example, a second edge region when viewed in a plan view (corresponding to a right edge region in a plan view of fig. 4). When the second pads P2 in the third pad region 210 are aligned in the second horizontal direction in fig. 4, the second pads P2 in the fourth pad region 220 may be aligned in the first horizontal direction perpendicular to the second horizontal direction.

The fourth pad region 220 may include some of the second pads P2, and some of the second pads P2P 2 in the fourth pad region 220 may be electrically connected to the substrate SUB through some of the second wires W2 of the second wires W2. The fourth pad region 220 may be configured to have substantially the same function as the second pad region 120. Therefore, a detailed description of the fourth pad region 220 will be omitted hereinafter.

According to an embodiment, signals transmitted through the third and fourth pad regions 210 and 220 may be set to be different.

The third pad region 210 and the fourth pad region 220 may be disposed to be perpendicular to each other in a plan view. In some embodiments, the third pad region 210 and the fourth pad region 220 may be disposed substantially perpendicular to each other in a plan view. In some embodiments, the third pad region 210 and the fourth pad region 220, if extended, may be disposed to intersect each other in a plan view.

The second control circuit 230 may be disposed between the third pad region 210 and a storage region including the third and fourth storage regions 240 and 250.

The second control circuit 230 may receive a command CMD through the third pad area 210, and may decode the command CMD to generate a second write signal WT2 and a second read signal RD 2. The second control circuit 230 may receive the address ADD through the third pad region 210 and may decode the address ADD to generate third and fourth selection addresses SA <3:4>, fifth to eighth bank group addresses BGA <5:8>, and fifth to eighth bank addresses BKA <5:8 >. The second control circuit 230 may receive or output the DATA through the third pad area 210.

The second control circuit 230 may be implemented to perform substantially the same operations as the first control circuit 130. Therefore, a description of the second control circuit 230 will be omitted hereinafter.

The third storage area 240 may be located at a side of the second control circuit 230 facing away from the third pad area 210 in a plan view.

The third memory region 240 may include ninth through twelfth bank groups (not shown) that are activated according to fifth through eighth bank group addresses BGA <5:8> if the third selection address SA <3> is enabled. The ninth to twelfth bank groups (not shown) may include thirty-third to forty-eighth banks (not shown) that are activated according to the fifth to eighth bank addresses BKA <5:8 >.

The third storage area 240 may be implemented to have substantially the same structure as the first storage area 140 except for input/output (I/O) signals thereof. Therefore, a description of the third storage area 240 will be omitted hereinafter.

The fourth storage region 250 may be located at a side of the second control circuit 230 facing away from the third pad region 210 in a plan view.

The fourth storage region 250 may include thirteenth to sixteenth bank groups (not shown) that are activated according to fifth to eighth bank group addresses BGA <5:8> if the fourth selection address SA <4> is enabled. The thirteenth to sixteenth bank groups (not shown) may include forty-ninth to sixty-fourth banks (not shown) that are activated according to the fifth to eighth bank addresses BKA <5:8 >.

The fourth storage area 250 may be implemented to have substantially the same structure as the second storage area 150 except for input/output (I/O) signals thereof. Therefore, a description of the fourth storage area 250 will be omitted hereinafter.

Referring to fig. 5, the first storage region 140 may include a first bank group BG1, a second bank group BG2, a third bank group BG3, and a fourth bank group BG 4.

The first bank group BG1 may include first to fourth banks BK1, BK2, BK3, and BK 4.

The first bank BK1 may be activated if the first selection address SA <1>, the first bank group address BGA <1>, and the first bank address BKA <1> are enabled. The second bank BK2 may be activated if the first selection address SA <1>, the first bank group address BGA <1>, and the second bank address BKA <2> are enabled. The third bank BK3 may be activated if the first selection address SA <1>, the first bank group address BGA <1>, and the third bank address BKA <3> are enabled. The fourth bank BK4 may be activated if the first selection address SA <1>, the first bank group address BGA <1>, and the fourth bank address BKA <4> are enabled. The first to fourth banks BK1, BK2, BK3 and BK4 may share the first I/O line IO1 with each other, and may receive or output DATA through the first I/O line IO 1. That is, the first bank group BG1 may be coupled to the first I/O line IO1 to receive or output the DATA through the first I/O line IO 1.

The second bank group BG2 may include fifth to eighth banks BK5, BK6, BK7, and BK 8.

If the second bank group address BGA <2> is enabled, the second bank group BG2 may be activated, and the fifth to eighth banks BK5, BK6, BK7 and BK8 may share the second I/O line IO2 with each other so as to receive or output DATA through the second I/O line IO 2. The fifth to eighth banks BK5, BK6, BK7 and BK8 may be configured to perform substantially the same operations as the first to fourth banks BK1, BK2, BK3 and BK 4. Therefore, a description of the second bank group BG2 will be omitted hereinafter.

The third bank group BG3 may include ninth to twelfth banks BK9, BK10, BK11, and BK 12.

If the third bank group address BGA <3> is enabled, the third bank group BG3 may be activated, and the ninth to twelfth banks BK9, BK10, BK11 and BK12 may share the third I/O line IO3 with each other so as to receive or output the DATA through the third I/O line IO 3. The ninth to twelfth banks BK9, BK10, BK11 and BK12 may be configured to perform substantially the same operations as the first to fourth banks BK1, BK2, BK3 and BK 4. Therefore, the description of the third bank group BG3 will be omitted hereinafter.

The fourth bank group BG4 may include thirteenth to sixteenth banks BK13, BK14, BK15, and BK 16.

If the fourth bank group address BGA <4> is enabled, the fourth bank group BG4 may be activated, and the thirteenth to sixteenth banks BK13, BK14, BK15, and BK16 may share the fourth I/O line IO4 with each other so as to receive or output DATA DATA through the fourth I/O line IO 4. The thirteenth to sixteenth banks BK13, BK14, BK15 and BK16 may be configured to perform substantially the same operation as the first to fourth banks BK1, BK2, BK3 and BK 4. Therefore, a description of the fourth bank group BG4 will be omitted hereinafter.

The first memory region 140 may activate two of the first to sixteenth banks BK1 to BK16 to receive or output the DATA in the 8-bank mode. For example, the first and third bank group addresses BGA <1> and BGA <3> may be enabled in the 8-bank mode, and if the first bank address BKA <1> is enabled, the first bank BK1 and the ninth bank BK9 may be activated to receive or output the DATA.

The first to fourth bank groups BG1, BG2, BG3 and BG4 may be arranged in a second horizontal direction of the first storage region 140 in a plan view. The first to fourth banks BK1 to BK4 included in the first bank group BG1 may be arranged in a first horizontal direction of the first storage region 140 in a plan view. The fifth to eighth banks BK5 to BK8 included in the second bank group BG2 may be arranged in the first horizontal direction of the first storage region 140 in a plan view. The ninth to twelfth banks BK9 to BK12 included in the third bank group BG3 may be arranged in the first horizontal direction of the first storage region 140 in a plan view. The thirteenth to sixteenth banks BK13 to BK16 included in the fourth bank group BG4 may be arranged in the first horizontal direction of the first storage region 140 in a plan view.

Referring to fig. 6, the second storage region 150 may include a fifth bank group BG5, a sixth bank group BG6, a seventh bank group BG7, and an eighth bank group BG 8.

The fifth bank group BG5 may include seventeenth to twentieth banks BK17, BK18, BK19, and BK 20.

If the second selection address SA <2>, the first bank group address BGA <1>, and the first bank address BKA <1> are enabled, a seventeenth BK17 may be activated. If the second selection address SA <2>, the first bank group address BGA <1>, and the second bank address BKA <2> are enabled, the eighteenth bank BK18 may be activated. The nineteenth bank BK19 may be activated if the second selection address SA <2>, the first bank group address BGA <1>, and the third bank address BKA <3> are enabled. The twentieth bank BK20 may be activated if the second selection address SA <2>, the first bank group address BGA <1>, and the fourth bank address BKA <4> are enabled. The seventeenth to twentieth banks BK17, BK18, BK19 and BK20 may share the fifth I/O line IO5 with each other, and may receive or output DATA through the fifth I/O line IO 5. That is, the fifth bank group BG5 may be coupled to the fifth I/O line IO5 to receive or output the DATA through the fifth I/O line IO 5.

The sixth bank group BG6 may include twenty-first to twenty-fourth banks BK21, BK22, BK23, and BK 24.

If the second bank group address BGA <2> is enabled, the sixth bank group BG6 may be activated, and the twenty-first to twenty-fourth banks BK21, BK22, BK23, and BK24 may share the sixth I/O line IO6 with each other to receive or output DATA DATA through the sixth I/O line IO 6. The twenty-first to twenty-fourth banks BK21, BK22, BK23 and BK24 may be configured to perform substantially the same operations as the seventeenth to twentieth banks BK17, BK18, BK19 and BK 20. Therefore, a description of the sixth bank group BG6 will be omitted hereinafter.

The seventh bank group BG7 may include twenty-fifth to twenty-eighth banks BK25, BK26, BK27, and BK 28.

If the third bank group address BGA <3> is enabled, the seventh bank group BG7 may be activated, and the twenty-fifth to twenty-eighth banks BK25, BK26, BK27, and BK28 may share the seventh I/O line IO7 with each other to receive or output DATA DATA through the seventh I/O line IO 7. The twenty-fifth to twenty-eighth banks BK25, BK26, BK27 and BK28 may be configured to perform substantially the same operations as the seventeenth to twentieth banks BK17, BK18, BK19 and BK 20. Therefore, a description of the seventh bank group BG7 will be omitted hereinafter.

The eighth bank group BG8 may include twenty ninth to thirty second banks BK29, BK30, BK31, and BK 32.

If the fourth bank group address BGA <4> is enabled, the eighth bank group BG8 may be activated, and the twenty-ninth to thirty-second banks BK29, BK30, BK31, and BK32 may share the eighth I/O line IO8 with each other to receive or output the DATA DATA through the eighth I/O line IO 8. The twenty-ninth to thirty-second banks BK29, BK30, BK31 and BK32 may be configured to perform substantially the same operations as the seventeenth to twentieth banks BK17, BK18, BK19 and BK 20. Therefore, a description of the eighth bank group BG8 will be omitted hereinafter.

The second memory region 150 may activate two of the seventeenth to thirty-second memory banks BK17 to BK32 to receive or output the DATA in the 8-memory mode. For example, the first and third bank group addresses BGA <1> and BGA <3> may be enabled in the 8-bank mode, and if the first storage area address BKA <1> is enabled, the seventeenth bank BK17 and the twenty fifth bank BK25 may be activated to receive or output the DATA.

The fifth to eighth bank groups BG5, BG6, BG7 and BG8 may be arranged in the second horizontal direction of the second storage region 150 in a plan view. The seventeenth to twentieth memory banks BK17 to BK20 included in the fifth memory bank group BG5 may be arranged in the first horizontal direction of the second memory area 150 in a plan view. The twenty-first to twenty-fourth memory banks BK21 to BK24 included in the sixth memory bank group BG6 may be arranged in the first horizontal direction of the second storage area 150 in a plan view. The twenty-fifth to twenty-eighth banks BK25 to BK28 included in the seventh bank group BG7 may be arranged in the first horizontal direction of the second storage area 150 in a plan view. The twenty-ninth to thirty-second memory banks BK29 to BK32 included in the eighth memory bank group BG8 may be arranged in the first horizontal direction of the second storage area 150 in a plan view.

The memory region included in each of the second, third and fourth semiconductor CHIPs CHIP2, CHIP3 and CHIP4 may be implemented to perform substantially the same operation as the first memory region 140 and the second memory region 150 shown in fig. 5 and 6. Therefore, a description of a memory region included in each of the second, third, and fourth semiconductor CHIPs CHIP2, CHIP3, and CHIP4 will be omitted hereinafter.

A stacked structure of the first semiconductor CHIP1 and the second semiconductor CHIP2 included in the semiconductor package 1 of fig. 1 will be described below with reference to fig. 7.

The first semiconductor CHIP1 may be stacked on the substrate SUB such that the first pad region 110 is located at an upper edge region of the first semiconductor CHIP1 in a plan view, and the second pad region 120 is located at a right edge region of the first semiconductor CHIP1 in a plan view.

The second semiconductor CHIP2 may be stacked on the first semiconductor CHIP1 such that the third pad region 210 is located at a lower edge region of the second semiconductor CHIP2 in a plan view and the fourth pad region 220 is located at a left edge region of the second semiconductor CHIP2 in a plan view. In this case, the second semiconductor CHIP2 may be laterally offset with respect to the first semiconductor CHIP1 to expose the first and second pad regions 110 and 120. Accordingly, the first and third pad regions 110 and 210 may be point-symmetrical with respect to center points of the first and second semiconductor CHIPs CHIP1 and CHIP2 when viewed from a plan view. Similarly, the second and fourth pad regions 120 and 220 may also be point-symmetric with respect to the center points of the first and second semiconductor CHIPs CHIP1 and CHIP2 when viewed from a plan view.

As described above, the second semiconductor CHIP2 may be stacked on the first semiconductor CHIP1 so as to be laterally offset in a first direction (i.e., a first lateral direction). In this case, although not shown in fig. 7, the third semiconductor CHIP3 may be stacked on the second semiconductor CHIP2 to be laterally offset in a second direction (i.e., a second lateral direction) opposite to the first direction, such that the third and fourth pad regions 210 and 220 are exposed. That is, the second, third, and fourth semiconductor CHIPs CHIP2, CHIP3, and CHIP4 may be vertically stacked on the first semiconductor CHIP1 in a zigzag manner to expose their pad regions and provide a space sufficient to bond the wires W1 to W4 to the pads P1 to P4, even though any intermediate layered elements disposed between the first to fourth semiconductor CHIPs CHIP1, CHIP2, CHIP3, and CHIP4 are not used. As a result, the total thickness of the semiconductor package 1 can be reduced.

The semiconductor package 1 described with reference to fig. 2 to 7 may be applied to electronic systems including a memory system, a graphic system, a computing system, a mobile system, and the like. For example, as shown in FIG. 8, an electronic system 1000 according to an embodiment may include a data storage circuit 1001, a memory controller 1002, a buffer memory 1003, and an input/output (I/O) interface 1004.

The data storage circuit 1001 may store data output from the memory controller 1002, or may read and output the stored data to the memory controller 1002 according to a control signal output from the memory controller 1002. The data storage circuit 1001 may include a nonvolatile memory that retains their stored data even when power supply thereto is interrupted. The nonvolatile memory may be a flash memory such as a NOR type flash memory or a NAND type flash memory, a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM), or the like.

The memory controller 1002 may receive a command output from an external device (e.g., a host device) through the I/O interface 1004 and may decode the command output from the host device to control an operation for inputting data into the data storage circuit 1001 or the buffer memory 1003 or for outputting data stored in the data storage circuit 1001 or the buffer memory 1003. Although fig. 8 shows the memory controller 1002 having a single block, the memory controller 1002 may include one controller for controlling the data storage circuit 1001 and another controller for controlling the buffer memory 1003 composed of a volatile memory.

The buffer memory 1003 may temporarily store data to be processed by the memory controller 1002. That is, the buffer memory 1003 can temporarily store data output from or input to the data storage circuit 1001. The memory 1003 may store data output from the memory controller 1002 according to the control signal. The buffer memory 1003 may read and output the stored data to the memory controller 1002. The buffer memory 1003 may include the semiconductor package 1 shown in fig. 2. The buffer memory 1003 may include a volatile memory such as a Dynamic Random Access Memory (DRAM), a mobile DRAM, or a Static Random Access Memory (SRAM).

The I/O interface 1004 may physically and electrically connect the memory controller 1002 to an external device (i.e., a host). Accordingly, the memory controller 1002 may receive control signals and data provided from an external device (i.e., a host) through the I/O interface 1004 and may output data output from the memory controller 1002 to the external device (i.e., the host). That is, electronic system 1000 may communicate with a host through I/O interfaces 1004. The I/O interface 1004 may include any of a variety of interface protocols, such as Universal Serial Bus (USB), Multi-media card (MMC), peripheral component interconnect express (PCI-E), Serial Attached SCSI (SAS), Serial AT attachment (SATA), parallel AT attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Integrated Drive Electronics (IDE).

Electronic system 1000 may be used as a secondary storage device to a host or an external storage device. The electronic system 1000 may include a Solid State Disk (SSD), a USB memory, a Secure Digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded multimedia card (eMMC), a Compact Flash (CF) card, and the like.