阅读说明：本技术 光电晶体管、红外探测器和光电晶体管的制作方法 (Phototransistor, infrared detector and method for manufacturing phototransistor ) 是由 汪巍 方青 涂芝娟 曾友宏 蔡艳 王庆 王书晓 余明斌 于 2018-09-12 设计创作，主要内容包括：本发明公开了一种光电晶体管、红外探测器和光电晶体管的制作方法。该光电晶体管包括栅极堆栈；设置于栅极堆栈一侧的有源层；设置于有源层远离栅极堆栈一侧的抗反层；其中,有源层包括沟道区,以及位于沟道区两侧的源极区和漏极区；其中,有源层的材料为锗锡合金。本发明提供的技术方案通过形成上述光电晶体管结构,并设置有源层的材料为锗锡合金,可使光电晶体管具有较高的灵敏度,且光电晶体管结构简单。(The invention discloses a phototransistor, an infrared detector and a manufacturing method of the phototransistor. The phototransistor includes a gate stack; the active layer is arranged on one side of the grid stack; the anti-reflection layer is arranged on one side of the active layer, which is far away from the grid stack; the active layer comprises a channel region, a source region and a drain region, wherein the source region and the drain region are positioned at two sides of the channel region; wherein, the material of the active layer is germanium tin alloy. According to the technical scheme provided by the invention, the phototransistor structure is formed, and the material of the active layer is germanium-tin alloy, so that the phototransistor has high sensitivity and the phototransistor has a simple structure.)

1. A phototransistor, comprising:

a gate stack;

the active layer is arranged on one side of the grid stack;

the anti-reflection layer is arranged on one side, away from the grid electrode stack, of the active layer;

the active layer comprises a channel region, a source region and a drain region, wherein the source region and the drain region are positioned on two sides of the channel region; the active layer is made of germanium tin alloy.

2. The phototransistor as set forth in claim 1, wherein said germanium tin alloy has a chemical formula of Ge_1-xSn_xWherein the value range of x is more than 0 and less than or equal to 0.4.

3. The phototransistor of claim 1, wherein the source and drain regions of the active layer are formed from a doped germanium tin alloy material and the channel region is formed from an intrinsic germanium tin alloy material;

the doping type of the germanium-tin-doped alloy material is P type or N type.

4. The phototransistor of claim 1, wherein the gate stack comprises a heavily doped silicon substrate and a dielectric layer between the heavily doped silicon substrate and the active layer;

wherein the doping concentration D of the heavily doped silicon substrate is in a range of 2 × 10¹⁸cm^-3≤D≤5×10¹⁹cm^-3And the doping type of the heavily doped silicon substrate is P type or N type.

5. The phototransistor of claim 4, wherein the material of the dielectric layer is silicon dioxide or a high dielectric constant dielectric;

wherein the value range of the relative dielectric constant k of the dielectric with high dielectric constant is more than or equal to 8 and less than or equal to 100.

6. The phototransistor of claim 1, wherein the material of the anti-reflective layer is silicon dioxide.

7. The phototransistor of claim 1, wherein the thickness T1 of the active layer ranges from 10nm to T1 to 80 nm.

8. The phototransistor of claim 1, wherein the thickness T2 of the anti-reflective layer ranges from 300nm to T2 to 800 nm.

9. An infrared detector comprising the phototransistor according to any one of claims 1 to 9, further comprising a source electrode and a drain electrode;

the anti-reflection layer is provided with a source through hole and a drain through hole, the source through hole exposes at least part of the source region, and the drain through hole exposes at least part of the drain region;

the source electrode penetrates through a source via hole of the anti-reflection layer and is electrically connected with the source region of the active layer; the drain electrode penetrates through a drain via hole of the anti-reflection layer and is electrically connected with the drain region of the active layer.

10. A method of fabricating a phototransistor used to fabricate the phototransistor as set forth in any one of claims 1 to 8, comprising:

forming the gate stack and the preset layer positioned on one side of the gate stack;

the preset layer is made of germanium-tin alloy;

defining and forming the active layer including a source region, a drain region and a channel region in the preset layer;

and forming an anti-reflection layer on one side of the active layer far away from the gate stack.

11. The method of claim 10, wherein the forming the gate stack and the preset layer on one side of the gate stack comprises:

providing a silicon substrate;

epitaxially forming a germanium buffer layer on one side of the silicon substrate;

forming a germanium tin alloy layer on the side, far away from the silicon substrate, of the germanium buffer layer in an epitaxial manner, namely forming the preset layer;

forming a first silicon dioxide layer on one side of the preset layer far away from the silicon substrate;

providing a heavily doped silicon substrate;

wherein the doping concentration D of the heavily doped silicon substrate is in a range of 2 × 10¹⁸-5×10¹⁹cm^-3；

Epitaxially forming a second silicon dioxide layer on one side of the heavily doped silicon substrate;

bonding the first silicon dioxide layer and the second silicon dioxide layer, wherein the first silicon dioxide layer and the second silicon dioxide layer jointly form a dielectric layer;

and removing the silicon substrate and the germanium buffer layer by adopting a selective etching process until the preset layer is exposed.

12. The method of claim 11, wherein the removing the silicon substrate and the germanium buffer layer by a selective etching process until the pre-set layer is exposed comprises:

selectively etching the silicon substrate by adopting a tetramethyl ammonium hydroxide solution, and staying at the germanium buffer layer;

and selectively etching the germanium buffer layer by adopting a dry etching process to stay on the preset layer.

13. The method of claim 10, wherein defining and forming the active layer including a source region, a drain region and a channel region in the pre-set layer comprises:

patterning the preset layer by adopting a photoetching process to form a phototransistor region;

defining the source region and the drain region in the phototransistor region by adopting a photoetching process;

and forming a germanium-tin-doped alloy by adopting an ion implantation process and a high-temperature annealing process, namely forming the source region and the drain region, and forming the channel region by using an undoped intrinsic germanium-tin alloy positioned between the germanium-tin-doped alloy.

14. The method of claim 13, wherein the ion implantation process comprises the following process conditions: the implantation energy was 20KeV and the implantation dose was 10¹⁵cm^-2；

The process conditions of the high-temperature annealing process are as follows: the annealing temperature was 400 ℃ and the annealing time was 5 minutes.

15. The method of claim 10, wherein the forming an anti-reflective layer on the active layer on a side away from the gate stack comprises:

and forming a silicon dioxide layer on one side of the active layer, which is far away from the gate stack, by adopting a magnetron sputtering process.

Technical Field

The embodiment of the invention relates to the technical field of photoelectrons, in particular to a phototransistor, an infrared detector and a manufacturing method of the phototransistor.

Background

Germanium tin alloy (GeSn) is a novel IV-group material, and has a larger absorption coefficient from short wave infrared to middle infrared because the band gap of the germanium tin alloy can be adjusted along with the Sn component, so that the germanium tin alloy is an ideal material for preparing an infrared detector. Therefore, in recent years, research on application of GeSn alloys to infrared detectors has been widely conducted.

However, the conventional p-i-n type photodetector has a limited detection sensitivity due to a lack of internal optical gain, and has a low light sensitivity. The avalanche photodiode can realize photocurrent amplification through an avalanche multiplication effect, thereby realizing high-sensitivity detection. However, the avalanche multiplication effect requires a large bias voltage to be applied, resulting in a limitation in the application of avalanche photodiodes in portable infrared detectors. The authors of Wei Wang et al disclose a GeSn bipolar phototransistor in its published "flowing-base germanium-heterojunction phototransistor for high-efficiency photodetection in short-wave isolated range". Compared with the traditional p-i-n type GeSn photoelectric detector, the GeSn photoelectric transistor has 10 times of photoelectric current gain, and the light responsivity reaches 1.8A/W at 1.55 um.

Disclosure of Invention

The invention provides a photoelectric transistor based on an MOS structure, an infrared detector and a manufacturing method of the photoelectric transistor, which can realize larger photoelectric gain by adjusting grid voltage, thereby realizing that the photoelectric transistor has higher sensitivity and simpler structure, and further realizing portable application of the infrared detector.

In a first aspect, an embodiment of the present invention provides a phototransistor including:

a gate stack;

the active layer is arranged on one side of the grid stack;

the anti-reflection layer is arranged on one side, away from the grid electrode stack, of the active layer;

the active layer comprises a channel region, a source region and a drain region, wherein the source region and the drain region are positioned on two sides of the channel region;

the active layer is made of germanium tin alloy.

Further, the chemical formula of the germanium tin alloy is Ge_1-xSn_xWherein the value range of x is more than 0 and less than or equal to 0.4.

Furthermore, the source region and the drain region of the active layer are made of a doped germanium-tin alloy material, and the channel region is made of an intrinsic germanium-tin alloy material;

the doping type of the germanium-tin-doped alloy material is P type or N type.

Further, the gate stack comprises a heavily doped silicon substrate and a dielectric layer, wherein the dielectric layer is positioned between the heavily doped silicon substrate and the active layer;

wherein the doping concentration D of the heavily doped silicon substrate is in a range of 2 × 10¹⁸cm^-3≤D≤5×10¹⁹cm^-3And the doping type of the heavily doped silicon substrate is P type or N type.

Further, the material of the dielectric layer is silicon dioxide or a dielectric with a high dielectric constant;

wherein the value range of the relative dielectric constant k of the dielectric with high dielectric constant is more than or equal to 8 and less than or equal to 100.

Further, the material of the anti-reflection layer is silicon dioxide.

Furthermore, the value range of the thickness T1 of the active layer is more than or equal to 10nm and less than or equal to T1 and less than or equal to 80 nm.

Furthermore, the value range of the thickness T2 of the anti-reflection layer is more than or equal to 300nm and less than or equal to T2 and less than or equal to 800 nm.

In a second aspect, an embodiment of the present invention provides an infrared detector, including any one of the phototransistors provided in the first aspect, and further including a source electrode and a drain electrode;

the anti-reflection layer is provided with a source through hole and a drain through hole, the source through hole exposes at least part of the source region, and the drain through hole exposes at least part of the drain region;

the source electrode penetrates through a source via hole of the anti-reflection layer and is electrically connected with the source region of the active layer; the drain electrode penetrates through a drain via hole of the anti-reflection layer and is electrically connected with the drain region of the active layer.

In a third aspect, an embodiment of the present invention further provides a method for manufacturing a phototransistor, where the method is used to prepare any one of the phototransistors provided in the first aspect, and the method includes:

forming the gate stack and the preset layer positioned on one side of the gate stack;

the preset layer is made of germanium-tin alloy;

defining and forming the active layer including a source region, a drain region and a channel region in the preset layer;

and forming an anti-reflection layer on one side of the active layer far away from the gate stack.

Further, the forming the gate stack and the preset layer located at one side of the gate stack includes:

providing a silicon substrate;

epitaxially forming a germanium buffer layer on one side of the silicon substrate;

forming a germanium tin alloy layer on the side, far away from the silicon substrate, of the germanium buffer layer in an epitaxial manner, namely forming the preset layer;

forming a first silicon dioxide layer on one side of the preset layer far away from the silicon substrate;

providing a heavily doped silicon substrate;

wherein the doping concentration D of the heavily doped silicon substrate is in a range of 2 × 10¹⁸cm^-3≤D≤5×10¹⁹cm^-3；

Epitaxially forming a second silicon dioxide layer on one side of the heavily doped silicon substrate;

bonding the first silicon dioxide layer and the second silicon dioxide layer, wherein the first silicon dioxide layer and the second silicon dioxide layer jointly form a dielectric layer;

and removing the silicon substrate and the germanium buffer layer by adopting a selective etching process until the preset layer is exposed.

Further, the removing the silicon substrate and the germanium buffer layer by using a selective etching process until the preset layer is exposed includes:

selectively etching the silicon substrate by adopting a tetramethyl ammonium hydroxide solution, and staying at the germanium buffer layer;

and selectively etching the germanium buffer layer by adopting a dry etching process to stay on the preset layer.

Further, in the preset layer, defining and forming the active layer including a source region, a drain region and a channel region includes:

patterning the preset layer by adopting a photoetching process to form a phototransistor region;

defining the source region and the drain region in the phototransistor region by adopting a photoetching process;

and forming a germanium-tin-doped alloy by adopting an ion implantation process and a high-temperature annealing process, namely forming the source region and the drain region, and forming the channel region by using an undoped intrinsic germanium-tin alloy positioned between the germanium-tin-doped alloy.

Further, the process conditions of the ion implantation process are as follows: the implantation energy was 20KeV and the implantation dose was 10¹⁵cm^-2；

The process conditions of the high-temperature annealing process are as follows: the annealing temperature was 400 ℃ and the annealing time was 5 minutes.

Further, the forming an anti-reflection layer on the side of the active layer away from the gate stack includes:

and forming a silicon dioxide layer on one side of the active layer, which is far away from the gate stack, by adopting a magnetron sputtering process.

The embodiment of the invention provides a phototransistor which comprises a grid stack; the active layer is arranged on one side of the grid stack; the anti-reflection layer is arranged on one side of the active layer, which is far away from the grid stack; the active layer comprises a channel region, a source region and a drain region, wherein the source region and the drain region are positioned at two sides of the channel region; wherein, the material of the active layer is germanium tin alloy. Firstly, the germanium-tin alloy material has photoelectric characteristics, and can realize amplification of photocurrent when applied to a phototransistor; the injection efficiency of the current carrier can be adjusted by adjusting the voltage applied to the gate stack, so that the optical gain with different degrees is realized, namely, when the light with the same intensity irradiates a channel region, the photocurrent fed back by the phototransistor can be different by adjusting the voltage applied to the gate stack; and because the higher the optical gain, the higher the sensitivity of the phototransistor and thus the higher the detection sensitivity of the infrared detector, the detection sensitivity of the infrared detector can be improved by increasing the voltage applied to the gate stack of the phototransistor. Secondly, the sensitivity of the phototransistor can be adjusted through the voltage change of the grid stack, so that the sensitivity of the infrared detector can be adjusted, and the infrared detector is suitable for different sensitivity requirements. And thirdly, light rays are incident to the channel region through the anti-reflection layer, and the anti-reflection layer has the effects of reducing reflected light rays and increasing transmitted light rays, so that the intensity of the light rays incident to the channel region can be increased, and the detection accuracy of the infrared detector can be increased. Finally, the phototransistor has a simple structure and light overall weight, and is convenient for realizing portable application of the infrared detector.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a phototransistor according to an embodiment of the present invention;

fig. 2 is a schematic flow chart illustrating a method for fabricating a phototransistor according to an embodiment of the present invention;

fig. 3 is a schematic flow chart of a method for manufacturing an infrared detector according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the structure of the film layer before step S313 in FIG. 3;

FIG. 5 is a schematic diagram of the structure of the film layer after step S313 in FIG. 3;

FIG. 6 is a schematic diagram of the structure of the film layer after step S314 in FIG. 3;

fig. 7 is a schematic diagram of the structure of the film layer after step S323 in fig. 3;

fig. 8 is a schematic diagram of the structure of the film layer after step 341 in fig. 3.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a phototransistor according to an embodiment of the present invention. Referring to fig. 1, the phototransistor 10 includes: a gate stack 11; an active layer 12 disposed on one side of the gate stack 11; an anti-reflection layer 13 disposed on a side of the active layer 12 away from the gate stack 11; the active layer 12 includes a channel region 122, and a source region 121 and a drain region 123 located at two sides of the channel region 122; the active layer 12 is made of germanium-tin alloy.

In order to form an infrared detector using the phototransistor, a source via 131 and a drain via 132 are further disposed on the anti-reflection layer 13, the source via 131 exposes at least a portion of the source region 121, and the drain via 132 exposes at least a portion of the drain region 123; a source electrode 141 and a drain electrode 142, the source electrode 141 passing through the source via 131 of the anti-reflection layer 13 and electrically connected to the source region 121 of the active layer 12; the drain electrode 142 passes through the drain via 132 of the anti-reflection layer 13 and is electrically connected to the drain region 123 of the active layer 12;

the germanium-tin alloy material has photoelectric characteristics, and when light (for example, infrared rays) irradiates the channel region 122 of the active layer 12, due to a photoelectric effect of the channel region 122, photogenerated carriers can be generated, and the generation of the photogenerated carriers lowers a potential barrier between the gate stack 11 and the source region 121, and the carriers are injected from the source electrode 141, so that amplification of photocurrent is achieved. The injection efficiency of the carriers can be adjusted by adjusting the voltage applied to the gate stack 11, so that different optical gains can be realized, that is, when the light with the same intensity irradiates the channel region 122, the photocurrent fed back by the phototransistor 10 can be different by adjusting the voltage applied to the gate stack 11. Illustratively, the larger the voltage applied at the gate stack 11, the larger the photocurrent fed back by the phototransistor 10, i.e., the higher the optical gain of the phototransistor 10. Since the higher the optical gain of the phototransistor 10, the higher the sensitivity of the phototransistor 10 and the higher the detection sensitivity of the infrared detector, the detection sensitivity of the infrared detector can be improved by increasing the voltage applied to the gate stack 11 of the phototransistor 10.

Secondly, through the voltage variation of the gate stack 11, the sensitivity of the phototransistor 10 can be adjusted, so that the sensitivity of the infrared detector can be adjusted, and the infrared detector can meet different sensitivity requirements.

Again, light is incident on the channel region 122 through the anti-reflection layer 13, and since the anti-reflection layer 13 has the effects of reducing reflected light and increasing transmitted light, the intensity of light incident on the channel region 122 can be increased, and thus the detection accuracy of the infrared detector can be increased.

Finally, the phototransistor 10 has a simple structure and a light overall weight, and when the phototransistor is applied to an infrared detector, the infrared detector can be made to have a light overall weight, which is convenient for realizing portable application of the infrared detector.

Optionally, the chemical formula of the germanium tin alloy is Ge_1-xSn_xWherein the value range of x is more than 0 and less than or equal to 0.4.

The germanium is an IV-group indirect band gap material, the tin is an IV-group semi-metal material, and the germanium-tin alloy is formed by introducing tin into germanium, so that the band gap of the germanium-tin alloy can be adjusted by adjusting the proportion of two elements in the germanium-tin alloy, and the detection of light rays with different wavelength ranges can be realized.

It should be noted that the ratio of the germanium element and the tin element in the germanium-tin alloy can be set according to the actual requirements of the phototransistor and the infrared detector, which is not limited in the embodiment of the present invention.

Optionally, the source region 121 and the drain region 123 of the active layer 12 are made of a doped germanium-tin alloy material, and the channel region 122 is made of an intrinsic germanium-tin alloy material; the doping type of the germanium-tin alloy material is P type or N type.

The doping types of the source region 121 and the drain region 123 are both P-type, or the doping types of the source region 121 and the drain region 123 are both N-type.

Illustratively, P-type doping can be achieved by doping the intrinsic germanium tin alloy material with boron (B) element, and N-type doping can be achieved by doping the intrinsic germanium tin alloy material with phosphorus (P) element. Alternatively, other elements known to those skilled in the art may be used to dope the intrinsic ge-sn alloy material to implement P-type doping or N-type doping, which is not limited in the embodiment of the present invention.

With such an arrangement, the intrinsic ge-sn alloy material can be formed in the same process step, and then the doped ge-sn alloy material is formed by doping at the corresponding positions of the source region 121 and the drain region 123, i.e., the source region 121 and the drain region 123 are formed, so as to complete the fabrication of the active layer 12.

Optionally, the gate stack 11 includes a heavily doped silicon substrate 111 and a dielectric layer 112, and the dielectric layer 112 is located between the heavily doped silicon substrate 111 and the active layer 12; wherein the doping concentration D of the heavily doped silicon substrate 111 is in a range of 2 × 10¹⁸cm^-3≤D≤5×10¹⁹cm^-3The doping type of the heavily doped silicon substrate 111 is P-type or N-type.

The arrangement is that the silicon material substrate which is the same as the group IV element is used as the substrate of the phototransistor 10, so that the manufacturing process of the phototransistor of the present invention is compatible with the conventional metal complementary Oxide Semiconductor (CMOS) process, and thus the phototransistor of the present invention can be manufactured by using the existing mainstream CMOS process widely used, which is beneficial to reducing the manufacturing cost of the phototransistor, and is beneficial to reducing the manufacturing cost of the infrared detector.

It should be noted that, instead of the heavily doped silicon substrate, the substrate may also be formed by using other conductive materials, which is not limited in the embodiment of the present invention.

Optionally, the material of the dielectric layer 112 is silicon dioxide or a high-k dielectric; wherein the value range of the relative dielectric constant k of the dielectric with high dielectric constant is more than or equal to 8 and less than or equal to 100.

The dielectric constant of the silicon dioxide is between 3 and 8, and the silicon dioxide is used as the material of the dielectric layer 112, and the process is mature, so the process difficulty is small.

The dielectric layer 112 is made of a dielectric material with a high dielectric constant, so that the physical thickness of the dielectric layer 112 can be significantly increased, the leakage current of the gate stack 11 can be reduced, and the static power consumption can be reduced on the premise that the process cost is not increased and the thickness of the dielectric layer is satisfied, thereby improving the overall performance of the phototransistor 10.

Exemplary high-k dielectric materials may include lanthanum oxide (La2O3), lanthanum aluminate (LaAlO3), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), titanium aluminate (TiAlO3), gallium oxide (Ga2O3), or other high-k dielectric materials known to those skilled in the art, and the embodiments of the present invention are not limited thereto.

Optionally, the material of the anti-reflection layer 13 is silicon dioxide.

So set up, usable silicon dioxide forms anti-layer 13 to increase the intensity of shining the light of channel region 122, thereby increase light absorption efficiency, promote infrared detector's detection accuracy. Meanwhile, the silicon dioxide material is widely applied in the prior art, the preparation technology is mature, and the cost is lower, so that the manufacturing cost of the phototransistor can be reduced, and the manufacturing cost of the infrared detector can be reduced.

Illustratively, the anti-reflection layer 13 may be a silica coating having a vesicle structure.

It should be noted that the material of the anti-reflection layer 13 may also be other materials known to those skilled in the art, and the structure of the anti-reflection layer 13 may also be other structures known to those skilled in the art, which are not limited by the embodiment of the present invention.

Alternatively, the material of the source electrode 141 and the drain electrode 142 is a conductive metal.

With such an arrangement, the internal resistance of the phototransistor 10 can be reduced, which facilitates the carrier transmission, thereby ensuring that the phototransistor 10 has a higher optical gain.

For example, the conductive metal may be aluminum (Al), silver (Ag), copper (Cu), gold (Au), a conductive metal alloy, or other conductive metals or alloys known to those skilled in the art, and the embodiment of the invention is not limited thereto.

Optionally, the thickness T1 of the active layer 12 is in a range of T1 equal to or less than 10nm and equal to or less than 80 nm.

The thickness of the active layer 12 generally affects, among other things, the turn-on voltage and field-effect mobility of the phototransistor 10. By setting the thickness range of the active layer 12, the phototransistor 10 has a smaller turn-on voltage and a larger field effect mobility, so that carrier transmission is facilitated, a larger optical gain of the phototransistor 10 is facilitated, and a higher optical sensitivity of the infrared detector is facilitated.

Optionally, the thickness T2 of the anti-reflection layer 13 is in a range of T2 to 800nm from 300nm to 300 nm.

With such an arrangement, the anti-reflection effect (i.e., reducing reflected light and increasing transmitted light) of the anti-reflection layer 13 is better, so that more light irradiates the channel region 122, which is beneficial to improving the detection accuracy of the infrared detector.

On the basis of the foregoing embodiments, an embodiment of the present invention further provides an infrared detector, where the infrared detector includes the phototransistor provided in the foregoing embodiments, and therefore, the infrared detector provided in the embodiment of the present invention also has the advantages of high and adjustable detection sensitivity, high detection accuracy, light weight, and convenience for carrying, and the like.

Based on the same inventive concept, embodiments of the present invention further provide a method for manufacturing a phototransistor, which is used to manufacture any one of the phototransistors provided in the above embodiments, and reference may be made to the description of the phototransistor herein where no detailed explanation is provided. For example, fig. 2 is a schematic flowchart of a method for manufacturing a phototransistor according to an embodiment of the present invention. Referring to fig. 2, the manufacturing method includes:

and S21, forming a gate stack and a preset layer positioned on one side of the gate stack.

The material of the preset layer is germanium-tin alloy, and the proportion of germanium element and tin element in the germanium-tin alloy can be set according to the actual requirement of the phototransistor.

S22, in the preset layers, an active layer including a source region, a drain region and a channel region is defined and formed.

And S23, forming an anti-reflection layer on the side of the active layer far away from the gate stack.

The anti-reflection layer is provided with a source electrode through hole and a drain electrode through hole, the source electrode through hole exposes at least part of the source electrode area, and the drain electrode through hole exposes at least part of the drain electrode area, so that preparation is made for forming a source electrode and a drain electrode subsequently.

Therefore, the phototransistor manufactured by the above method and the infrared detector including the phototransistor have the same beneficial effects as the phototransistor and the infrared detector provided by the above embodiment, and further description is omitted here.

In addition, the manufacturing method of the photoelectric transistor has fewer process steps and is simple.

In order to form an infrared detector to which the phototransistor is applied, a source electrode may be formed in the source via hole of the anti-reflection layer, and a drain electrode may be formed in the drain via hole of the anti-reflection layer. Wherein the source electrode is electrically connected with the source region, and the drain electrode is electrically connected with the drain region. Optionally, fig. 3 is a schematic flowchart of a manufacturing method of an infrared detector according to an embodiment of the present invention, where the manufacturing method includes a manufacturing process of a phototransistor. Referring to fig. 3, the manufacturing method may include 4 steps, wherein step S31 may include:

s3111, providing a silicon substrate.

The silicon substrate may be formed by any method known to those skilled in the art, and is not described in detail nor limited in the embodiments of the present invention.

S3112, epitaxially forming a germanium buffer layer on one side of the silicon substrate.

Wherein the thickness of the germanium buffer layer may be 1 μm. The epitaxial process parameters of the step can be set according to the actual requirements of the manufacturing methods of the phototransistor and the infrared detector, which is not limited in the embodiment of the invention.

S3113, forming a germanium-tin alloy layer on the germanium buffer layer far away from the silicon substrate in an epitaxial manner, namely forming a preset layer.

The thickness of the preset layer can be 50nm, and the proportion of tin element in the germanium-tin alloy layer can be 8%. The epitaxial parameters of this step may also be set according to the actual requirements of the manufacturing methods of the phototransistor and the infrared detector, which is not limited in this embodiment of the present invention.

S3114, forming a first silicon dioxide layer on the side, far away from the silicon substrate, of the preset layer.

The thickness of the first silicon dioxide layer may be 10nm, and the formation method may be any physical formation method or chemical formation method known to those skilled in the art, which is not described in detail nor limited in the embodiments of the present invention.

S3121, providing a heavily doped silicon substrate.

Wherein, the doping type of the heavily doped silicon substrate can be P type or N type, and the value range of the doping concentration D can be 2 multiplied by 10¹⁸cm^-3≤D≤5×10¹⁹cm^-3(ii) a The heavily doped silicon substrate may be formed by any method known to those skilled in the art, and will not be described in detail or limited herein.

And S3122, forming a second silicon dioxide layer on the extension of one side of the heavily doped silicon substrate.

The thickness of the second silicon dioxide layer may be 10nm, and the formation method thereof may be any physical formation method or chemical formation method known to those skilled in the art, which is not described in detail nor limited in the embodiments of the present invention.

For example, fig. 4 is a schematic diagram of a film structure before step S313 in fig. 3. At this time, corresponding film layers are respectively formed on the two substrates (the heavily doped silicon substrate 111 and the silicon substrate 011), specifically: forming a second silicon dioxide layer 1122 on one side of the heavily doped silicon substrate 111; a germanium buffer layer 012, a pre-set layer 120, and a first silicon oxide layer 1121 are sequentially formed on one side of a silicon substrate 011. The first silicon dioxide layer 1121 and the second silicon dioxide layer 1122 are disposed opposite to each other in preparation for subsequent bonding (wafer bonding).

Step S3111, step S3112, step S3113, and step S3114 are sequentially performed to form step S311; step S3121 and step S3122 are performed sequentially to form step S312; in the actual manufacturing process, step S311 may be executed first, step S312 may be executed first, or step S311 and step S312 may be executed simultaneously, and the execution sequence of step S311 and step S312 is not limited in the embodiment of the present invention.

S313, bonding the first silicon dioxide layer and the second silicon dioxide layer, wherein the first silicon dioxide layer and the second silicon dioxide layer jointly form a dielectric layer.

The bonding is a technique in which the first silica layer and the second silica layer are directly bonded under a bonding condition, and the first silica layer and the second silica layer are integrated by van der waals force, molecular force, or atomic force. The bonding conditions may be set according to actual requirements of the manufacturing methods of the phototransistor and the infrared detector, which is not limited in the embodiment of the present invention.

For example, fig. 5 is a schematic view of the film structure after step S313 in fig. 3. Referring to fig. 5, after step S313, the first silicon dioxide layer 1121 and the second silicon dioxide layer 1122 are integrated, i.e., the dielectric layer 112 is formed.

It should be noted that the first silicon dioxide layer 1121 and the second silicon dioxide layer 1122 are only exemplarily distinguished by a dotted line in fig. 5, and in an actual structure, the dotted line does not exist, and the first silicon dioxide layer 1121 and the second silicon dioxide layer 1122 together form a single complete dielectric layer 112.

And S314, removing the silicon substrate and the germanium buffer layer by adopting a selective etching process until the preset layer is exposed.

Wherein selective etching is understood to mean etching away only the silicon substrate and the germanium buffer layer, but not the pre-layer.

Optionally, step S314 may include two steps, which are sequentially:

step one, adopting a tetramethyl ammonium hydroxide solution to selectively etch the silicon substrate and stay in the germanium buffer layer.

Wherein, the tetramethylammonium hydroxide (TMAH) solution reacts only with the silicon substrate and not with the germanium buffer layer, and the concentration and the etching time thereof can be set according to the actual requirements of the manufacturing methods of the phototransistor and the infrared detector, which is not limited in the embodiment of the present invention.

It should be noted that this step may also be performed in other ways known to those skilled in the art that only the silicon substrate is etched, and the germanium buffer layer is not etched, which is not limited by the embodiment of the present invention.

And step two, selectively etching the germanium buffer layer by adopting a dry etching process, and staying at the preset layer.

The dry etching process may include etching the germanium buffer layer using a fluorine (F) -based gas that does not react with the pre-set layer, thereby etching only the germanium buffer layer.

It should be noted that this step may also be performed in other ways known to those skilled in the art that only the germanium buffer layer is etched, and the preset layer is not etched, which is not limited by the embodiment of the present invention.

For example, fig. 6 is a schematic diagram of the film structure after step S314 in fig. 3. Referring to fig. 6, after step S314, a GeSnOI (GeSn-on-insulator) substrate is formed, that is, the dielectric layer 112 and the preset layer 120 are sequentially formed on one side of the heavily doped silicon substrate 111, where the preset layer 120 is a germanium-tin alloy layer.

Optionally, step S32 may include:

s321, patterning the preset layer by adopting a photoetching process to form a phototransistor region.

The photolithography process may include forming a photoresist layer on a side of the pre-set layer 120 away from the dielectric layer 112; illuminating the photoresist layer through a mask plate, only reserving the photoresist layer at the corresponding position of the phototransistor area, and removing the photoresist layer at other positions; removing the preset layer which is not covered by the light resistance layer through wet etching or dry etching; and removing the photoresist layer at the corresponding position of the phototransistor region, thereby only reserving the preset layer of the phototransistor region.

It should be noted that, in this step, the process parameters of forming the photoresist layer, irradiating the photoresist layer, removing the photoresist layer, wet etching and dry etching to remove the preset layer may all be set according to the actual requirements of the manufacturing methods of the phototransistor and the infrared detector, which is not limited in the embodiment of the present invention.

And S322, defining a source region and a drain region in the phototransistor region by adopting a photoetching process.

The photolithography process may include forming a photoresist layer on a side of the phototransistor region (the preserved pre-layer) away from the dielectric layer 112; and irradiating the photoresist layer through another mask plate, removing the photoresist layer at the corresponding positions of the source region and the drain region, and reserving the photoresist layer at other positions.

It should be noted that, the photoresist layer in step S321 and step S322 may be the same photoresist layer material, or may be different photoresist layer materials, which is not limited in the embodiment of the invention. In addition, the mask openings in step S321 and step S322 are different, and the positions of the openings can be set according to the actual requirements of the manufacturing methods of the phototransistor and the infrared detector, which is not limited in the embodiment of the present invention.

S323, forming the doped germanium-tin alloy by adopting an ion implantation process and a high-temperature annealing process, namely forming a source region and a drain region, and forming a channel region by using the undoped intrinsic germanium-tin alloy positioned between the doped germanium-tin alloy.

Optionally, the process conditions of the ion implantation process are as follows: injection ofEnergy of 20KeV and implantation dose of 10¹⁵cm^-2(ii) a The technological conditions of the high-temperature annealing process are as follows: the annealing temperature was 400 ℃ and the annealing time was 5 minutes. This is merely an exemplary illustration, and in other embodiments, the process parameters of the ion implantation process and the high temperature annealing process may also be set according to actual requirements of the manufacturing methods of the phototransistor and the infrared detector, which is not limited in this embodiment of the present invention.

In addition, in step S323, other processes known to those skilled in the art may be used to form the doped ge-sn alloy, which is not limited in the embodiment of the present invention.

For example, fig. 7 is a schematic diagram of the structure of the film layer after step S323 in fig. 3. Referring to fig. 7, through the above-described step S32, the active layer 12 (including the source region 121, the channel region 122, and the drain region 123) is formed.

And S33, forming a silicon dioxide layer on the side of the active layer far away from the gate stack by adopting a magnetron sputtering process.

The thickness of the silicon dioxide layer can be 400nm, and the technological parameters of magnetron sputtering can be set according to the actual requirements of the manufacturing methods of the photoelectric transistor and the infrared detector; in addition, the step may also form the silicon dioxide layer in other ways known to those skilled in the art, which is not limited by the embodiments of the present invention.

Thus, a phototransistor structure is formed. To form the infrared detector, step S34 is further performed.

Optionally, step S34 may include:

and S341, etching the silicon dioxide layer by adopting a photoetching process to form a source electrode through hole and a drain electrode through hole.

Wherein, the photoetching process can comprise forming a light resistance layer on one side of the silicon dioxide layer far away from the active layer; illuminating the light resistance layer through another mask plate, only removing the light resistance layer at the corresponding positions of the source electrode through hole and the drain electrode through hole, and reserving the light resistance layer at other positions; removing the silicon dioxide layer which is not covered by the light resistance layer by wet etching or dry etching; and removing the light resistance layer at other positions, thereby forming a source through hole and a drain through hole in the silicon dioxide layer.

Illustratively, fig. 8 is a schematic diagram of the structure of the film layer after step 341 in fig. 3. Referring to fig. 8, the source via 131 exposes a portion of the surface of the source region 121, and the drain via 132 exposes a portion of the surface of the drain region 123.

It should be noted that the positions and sizes of the source via and the drain via may be set according to actual requirements of the infrared detector, which is not limited in the embodiment of the present invention.

And S342, forming a conductive metal layer on one side of the anti-reflection layer, which is far away from the gate stack, by adopting a magnetron sputtering process.

Wherein, the technological parameters of magnetron sputtering can be set according to the actual requirements of the manufacturing method of the infrared detector; in addition, the step may also form the conductive metal layer in other ways known to those skilled in the art, which is not limited by the embodiment of the present invention.

And S343, etching the conductive metal layer by adopting a photoetching process, reserving the conductive metal layers in the source through hole and the drain through hole of the anti-reflection layer, and removing the conductive metal layers at other positions to form a source electrode and a drain electrode.

The photoetching process can comprise forming a light resistance layer on one side of the conductive metal layer far away from the active layer; illuminating the light resistance layer through another mask plate, only reserving the light resistance layers at the positions corresponding to the source electrode through hole and the drain electrode through hole, and removing the light resistance layers at other positions; removing the conductive metal layer which is not covered by the light resistance layer by wet etching or dry etching; and removing the photoresist layer at the corresponding positions of the source through hole and the drain through hole, thereby forming a source electrode and a drain electrode.

To this end, an infrared detector structure is formed, as can be seen in fig. 1.

It should be noted that the photoresist layers in step S321, step S322, step 341 and step S342 may use the same photoresist layer material, or may use different photoresist layer materials, which is not limited in the embodiment of the invention. In addition, the openings of the mask in step S321, step S322, step 341 and step S342 are different, and the positions of the openings can be set according to the actual requirements of the manufacturing method of the phototransistor, which is not limited in the embodiment of the present invention.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations, and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.