阅读说明：本技术 一种背接触异质结太阳能电池制作方法 (Manufacturing method of back contact heterojunction solar cell ) 是由 谢志刚 张超华 王树林 林朝晖 于 2018-09-12 设计创作，主要内容包括：本发明公开了一种背接触异质结太阳能电池制作方法,其包括：提供N型硅片；在所述硅片的正面依次镀钝化膜层、增透层；在所述硅片的背面依次镀本征非晶硅层、P型非晶硅层；在所述硅片的背面形成蚀刻区域,移除蚀刻区域的本征非晶硅和P型非晶硅层；在硅片背面依次镀本征非晶硅层、N型非晶硅和绝缘层；在所述硅片的背面移除蚀刻区域的绝缘层、N型非晶硅层、本征非晶硅层；在所述硅片的背面移除蚀刻区域的绝缘层；在所述硅片的背面镀透明导电膜层；在所述硅片的背面去除印刷区域的透明导电膜层；在所述硅片的背面镀种子金属层；在所述硅片的背面栅线图案区域电镀铜,形成铜栅线电极；在铜栅线电极上镀金属锡层；去除耐电镀油墨及种子金属层。(The invention discloses a method for manufacturing a back contact heterojunction solar cell, which comprises the following steps: providing an N-type silicon wafer; plating a passivation film layer and an anti-reflection layer on the front surface of the silicon wafer in sequence; plating an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back of the silicon wafer in sequence; forming an etching area on the back surface of the silicon wafer, and removing the intrinsic amorphous silicon and the P-type amorphous silicon layer in the etching area; plating an intrinsic amorphous silicon layer, N-type amorphous silicon and an insulating layer on the back of the silicon wafer in sequence; removing the insulating layer, the N-type amorphous silicon layer and the intrinsic amorphous silicon layer in the etching area on the back surface of the silicon wafer; removing the insulating layer of the etching area on the back of the silicon wafer; plating a transparent conductive film layer on the back of the silicon wafer; removing the transparent conductive film layer in the printing area on the back of the silicon wafer; plating a seed metal layer on the back of the silicon wafer; electroplating copper on the back grid line pattern area of the silicon wafer to form a copper grid line electrode; plating a metal tin layer on the copper grid electrode; and removing the electroplating-resistant ink and the seed metal layer.)

1. A method for manufacturing a back contact heterojunction solar cell is characterized by comprising the following steps:

providing an N-type silicon wafer with a suede formed by texturing and cleaning;

plating a passivation film layer and an anti-reflection layer on the front surface of the silicon wafer in sequence;

plating an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back of the silicon wafer in sequence;

determining an etching area by screen printing a first layer of pattern on the back surface of the silicon wafer, and removing intrinsic amorphous silicon and a P-type amorphous silicon layer in the etching area by at least one of a protective ink and chemical corrosion combination method and a corrosive ink reaction method until the silicon wafer is exposed;

after being cleaned by cleaning solution, the back of the silicon wafer is plated with an intrinsic amorphous silicon layer, N-type amorphous silicon and an insulating layer in sequence, wherein the insulating layer is manufactured in a full-area covering mode;

printing a second layer of pattern on the back surface of the silicon wafer, determining an etching area, and removing the insulating layer, the N-type amorphous silicon layer and the intrinsic amorphous silicon layer in the etching area by at least one of a protective ink and chemical corrosion combination method and a corrosive ink reaction method until the P-type amorphous silicon layer is exposed;

printing a third layer of pattern on the back surface of the silicon wafer, determining an etching area in a local area of the insulating layer, and removing the insulating layer in the etching area by at least one of a chemical corrosion combination method and a corrosive ink reaction method through protective ink until the N-type amorphous silicon layer is exposed;

plating a transparent conductive film layer on the back of the silicon wafer in a full-area covering mode;

determining an etching area in a local area of a back insulating layer of the silicon wafer, and removing the transparent conductive film layer in the printing area by at least one of a chemical corrosion bonding method and a corrosive ink reaction method through protective ink;

plating a seed metal layer on the back of the silicon wafer;

printing electroplating-resistant ink on the back of the silicon wafer to form a grid line pattern;

electroplating copper on the back grid line pattern area of the silicon wafer to form a copper grid line electrode;

plating a metal tin layer on the surface of the copper grid electrode through a chemical displacement reaction or an electroplating method;

and removing the electroplating-resistant ink and the seed metal layer on the back surface of the silicon wafer by using a stripping solution.

2. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the passivation film layer on the front side of the silicon wafer is an intrinsic amorphous silicon layer formed by a PECVD method, a hot wire method or N-type doping diffusion deposition, or a combination of the intrinsic amorphous silicon layer and the N-type amorphous silicon layer, wherein the thickness of the intrinsic amorphous silicon layer is 1-15 nm, and the thickness of the N-type amorphous silicon layer is 0-15 nm.

3. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, magnesium fluoride, ITO, silicon oxide, aluminum oxide and zinc oxide, the thickness of the anti-reflection layer is 40-200 nm, and the anti-reflection layer is formed through PECVD or PVD deposition.

4. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the insulating layer is at least one of silicon nitride, silicon oxynitride, silicon oxide and amorphous silicon, the thickness of the insulating layer is 20-200 nm, and the insulating layer is formed by PECVD or PVD deposition, heating and curing of water glass sol, or spraying or printing of ink.

5. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the transparent conductive film layer is made of metal oxide and is at least one of an indium tin oxide film, an indium oxide film, a titanium-doped indium oxide film, an aluminum-doped zinc oxide film and a tungsten-doped indium oxide film, the thickness of the transparent conductive film layer is 10-200 nm, and the transparent conductive film layer is formed through PVD deposition.

6. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the corrosive ink reaction method corrodes the transparent conductive film layer, wherein the reaction temperature is 80-220 ℃, and the reaction time is 2-60 minutes.

7. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the cleaning mode is at least one of soaking, spraying, ultrasonic wave and bubbling.

8. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the metal seed layer is a seed copper layer, and the thickness of the seed copper layer is 70-300 nm.

9. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the width of the copper grid line is 10-400um, and the thickness is 5-100 um.

10. The method of fabricating a back contact heterojunction solar cell of claim 1, wherein: the film removing solution is alkaline etching solution.

Technical Field

The invention relates to the technical field of solar cells, in particular to a method for manufacturing a back contact heterojunction solar cell.

Background

The solar cell is a semiconductor device which can convert solar energy into electric energy, and photo-generated current is generated in the solar cell under the illumination condition, and the electric energy is output through an electrode. In recent years, solar cell production technology is continuously improved, production cost is continuously reduced, conversion efficiency is continuously improved, and solar cell power generation is increasingly widely applied and becomes an important energy source for power supply.

The high efficiency solar cell is a trend of future industry because the high efficiency solar cell not only improves the generating wattage per unit area, but also can reduce the cost, namely can improve the added value of the module generating.

Among them, the back contact cell is a cell in which the electrodes of the light receiving surface are all moved to the back surface, so that the area of the light receiving surface is maximized, thereby improving the conversion efficiency of the cell, and is typically SUN POWER in the united states.

Another type of heterojunction solar cell is typically a passivation layer of amorphous silicon (a-Si) grown on a silicon wafer with amorphous silicon electrodes, which have a very low surface recombination rate and therefore possess a very high open circuit voltage. Representative of this is the HIT technology of Panasonic, Japan.

However, the back contact heterojunction solar cell technology inevitably has the condition that an N-type electron collecting layer (an intrinsic amorphous silicon and an N-type amorphous silicon laminated layer) and a P-type hole collecting layer (an intrinsic amorphous silicon and a P-type amorphous silicon laminated layer) are overlapped, and if an N-type electrode (a transparent conductive film and a metal seed layer) or a P-type electrode (a transparent conductive film and a metal seed layer) is contacted with the overlapped region, an internal short circuit mechanism of the cell is triggered, so that the conversion efficiency of the back contact cell is seriously reduced. Therefore, there is a need to develop a new back contact heterojunction solar cell to solve the shortcomings of the current back contact heterojunction solar cell.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a method for manufacturing a back contact heterojunction solar cell, which is beneficial to the yield and stability of large-scale mass production and simultaneously improves the conversion efficiency of the cell.

In order to achieve the above purpose, the invention adopts the following design scheme,

providing an N-type silicon wafer with a suede formed by texturing and cleaning;

plating a passivation film layer and an anti-reflection layer on the front surface of the silicon wafer in sequence;

plating an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back of the silicon wafer in sequence;

determining an etching area by screen printing a first layer of pattern on the back surface of the silicon wafer, and removing intrinsic amorphous silicon and a P-type amorphous silicon layer in the etching area by at least one of a protective ink and chemical corrosion combination method and a corrosive ink reaction method until the silicon wafer is exposed;

after being cleaned by cleaning solution, the back of the silicon wafer is plated with an intrinsic amorphous silicon layer, N-type amorphous silicon and an insulating layer in sequence, wherein the insulating layer is manufactured in a full-area covering mode;

printing a second layer of pattern on the back surface of the silicon wafer, determining an etching area, and removing the insulating layer, the N-type amorphous silicon layer and the intrinsic amorphous silicon layer in the etching area by at least one of a protective ink and chemical corrosion combination method and a corrosive ink reaction method until the P-type amorphous silicon layer is exposed;

printing a third layer of pattern on the back surface of the silicon wafer, determining an etching area in a local area of the insulating layer, and removing the insulating layer in the etching area by at least one of a chemical corrosion combination method and a corrosive ink reaction method through protective ink until the N-type amorphous silicon layer is exposed;

plating a transparent conductive film layer on the back of the silicon wafer in a full-area covering mode;

printing an etching ink layer on a local area of the back insulating layer of the silicon wafer, and cleaning to remove the transparent conductive film layer in the printing area after reaction;

plating a seed metal layer on the back of the silicon wafer;

printing electroplating-resistant ink on the back of the silicon wafer to form a grid line pattern;

electroplating copper on the back grid line pattern area of the silicon wafer to form a copper grid line electrode;

plating a metal tin layer on the surface of the copper grid electrode through a chemical displacement reaction or an electroplating method;

and removing the electroplating-resistant ink and the seed metal layer on the back surface of the silicon wafer by using a stripping solution.

Preferably, the passivation film layer on the front surface of the silicon wafer is an intrinsic amorphous silicon layer formed by a PECVD method, a hot wire method or N-type doping diffusion deposition, or a combination of the intrinsic amorphous silicon layer and the N-type amorphous silicon layer, wherein the thickness of the intrinsic amorphous silicon layer is 1-15 nm, and the thickness of the N-type amorphous silicon layer is 0-15 nm.

Preferably, the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, magnesium fluoride, ITO, silicon oxide, aluminum oxide and zinc oxide, the thickness of the anti-reflection layer is 40-200 nm, and the anti-reflection layer is formed through PECVD or PVD deposition.

Preferably, the insulating layer is at least one of silicon nitride, silicon oxynitride, silicon oxide and amorphous silicon, the thickness of the insulating layer is 20-200 nm, and the insulating layer is formed by PECVD or PVD deposition, heating and curing of water glass sol, or spraying or printing of ink.

Preferably, the transparent conductive film layer is made of metal oxide and is at least one of an indium tin oxide film, an indium oxide film, a titanium-doped indium oxide film, an aluminum-doped zinc oxide film and a tungsten-doped indium oxide film, the thickness of the transparent conductive film layer is 10-200 nm, and the transparent conductive film layer is formed through PVD deposition.

Preferably, the transparent conductive film layer is corroded by the corrosive ink reaction method, the reaction temperature is 80-220 ℃, and the reaction time is 2-60 minutes.

Preferably, the cleaning method is at least one of soaking, spraying, ultrasonic wave and bubbling.

Preferably, the metal seed layer is a seed copper layer, and the thickness of the seed copper layer is 70-300 nm.

Preferably, the width of the copper grid line is 10-400um, and the thickness is 5-100 um.

Preferably, the film removing solution is an alkaline etching solution.

By adopting the technical scheme, the solar device prepared by the method has a simple process flow, the anti-reflection layer and the insulating layer are adopted, the anti-reflection layer and the insulating layer are insulated and isolated by adopting silicon nitride as a main material, and the transparent conductive film electrically connected with the N-type amorphous silicon is separated from the transparent conductive film electrically connected with the P-type amorphous silicon in a direct screen printing mode, so that a short circuit mechanism between the inside and the outside of the back contact battery is eliminated, the yield and the stability of large-scale mass production are greatly facilitated, and the conversion efficiency of the battery is improved.

Drawings

The invention is further illustrated with reference to the accompanying drawings:

FIG. 1 is a schematic structural diagram of a silicon wafer with a passivation layer and an anti-reflection layer plated on the front surface and an intrinsic amorphous silicon layer and a P-type amorphous silicon layer plated on the back surface according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a silicon wafer with a first layer of pattern formed on its back surface by a screen printing method according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a silicon wafer with an intrinsic amorphous silicon layer, an N-type amorphous silicon layer and an insulating film layer plated on the back side in sequence according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a silicon wafer with a second layer of patterns formed on the back surface by a screen printing method according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a silicon wafer according to an embodiment of the present invention after a third layer of patterns is printed on the back surface of the silicon wafer and after the insulating layer in the etching region is removed after chemical reaction;

FIG. 6 is a schematic structural diagram of a silicon wafer with a transparent conductive film layer formed on the back surface thereof by a thin film deposition method according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a transparent conductive film formed by printing etching ink on a local area of a back surface insulating layer of a silicon wafer and cleaning the printed area after reaction according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a silicon wafer with a metal seed layer formed on the back surface thereof according to an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a silicon wafer according to an embodiment of the present invention after printing plating-resistant ink on a local region of a backside insulating layer;

FIG. 10 is a schematic view of a back side of a silicon wafer electroplated to form a gate line structure according to an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a silicon wafer according to an embodiment of the present invention, in which plating-resistant ink on the back surface of the silicon wafer is removed by a stripping solution;

FIG. 12 is a schematic structural diagram of the silicon wafer according to the embodiment of the present invention, which is formed by removing the seed layer continuously through a chemical reaction by spraying or immersing.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The invention discloses a method for manufacturing a back contact heterojunction solar cell, which comprises the following steps:

providing an N-type silicon wafer with a suede formed by texturing and cleaning;

plating a passivation film layer and an anti-reflection layer on the front surface of the silicon wafer in sequence;

plating an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back of the silicon wafer in sequence;

determining an etching area by screen printing a first layer of pattern on the back surface of the silicon wafer, and removing intrinsic amorphous silicon and a P-type amorphous silicon layer in the etching area by at least one of a protective ink and chemical corrosion combination method and a corrosive ink reaction method until the silicon wafer is exposed;

after being cleaned by cleaning solution, the back of the silicon wafer is plated with an intrinsic amorphous silicon layer, N-type amorphous silicon and an insulating layer in sequence, wherein the insulating layer is manufactured in a full-area covering mode;

printing a second layer of pattern on the back surface of the silicon wafer, determining an etching area, and removing the insulating layer, the N-type amorphous silicon layer and the intrinsic amorphous silicon layer in the etching area by at least one of a protective ink and chemical corrosion combination method and a corrosive ink reaction method until the P-type amorphous silicon layer is exposed;

printing a third layer of pattern on the back surface of the silicon wafer, determining an etching area in a local area of the insulating layer, and removing the insulating layer in the etching area by at least one of a chemical corrosion combination method and a corrosive ink reaction method through protective ink until the N-type amorphous silicon layer is exposed;

plating a transparent conductive film layer on the back of the silicon wafer in a full-area covering mode;

printing an etching ink layer on a local area of the back insulating layer of the silicon wafer, and cleaning to remove the transparent conductive film layer in the printing area after reaction;

plating a seed metal layer on the back of the silicon wafer;

printing electroplating-resistant ink on the back of the silicon wafer to form a grid line pattern;

electroplating copper on the back grid line pattern area of the silicon wafer to form a copper grid line electrode;

plating a metal tin layer on the surface of the copper grid electrode through a chemical displacement reaction or an electroplating method;

and removing the electroplating-resistant ink and the seed metal layer on the back surface of the silicon wafer by using a stripping solution.

Specifically, the following embodiments may be adopted:

as shown in fig. 1, a textured and cleaned N-type silicon wafer 1 with a textured surface is provided, and the thickness of the N-type silicon wafer 1 may be between 50 micrometers and 500 micrometers. A passivation layer 2 is formed on the front surface, i.e. the light facing surface, of the silicon wafer 1, and the passivation layer 2 is a laminated layer of intrinsic amorphous silicon 21 and N-type amorphous silicon 22. And growing an antireflection layer 3 on the passivation layer 2 by a PVD or CVD film deposition method. The anti-reflection layer 3 can also be a combination of several films, and the total thickness of the anti-reflection layer is 40nm-300nm on the suede surface. The anti-reflection layer 3 is at least one of silicon nitride, silicon oxynitride, magnesium fluoride, ITO, silicon oxide, aluminum oxide and zinc oxide. And an intrinsic amorphous silicon layer 4 and a P-type amorphous silicon layer 5 are plated on the back surface of the silicon wafer 1 in sequence.

As shown in fig. 2, a first layer of pattern is defined on the back side of the silicon wafer 1 by covering protective ink by screen printing or by printing photosensitive ink and then exposing, and after reaction, the intrinsic amorphous silicon layer 4 and the P-type amorphous silicon layer 5 in the printing and etching region 41 are removed by cleaning, and the regions can also be directly printed with acid etching ink to remove 4 and 5. The etching ink can simultaneously corrode metal oxide, silicon nitride, silicon oxide and amorphous silicon, and is heated and baked to react at the temperature of 80-220 ℃ for 5-60 minutes, and the printing width is 0.03-0.9 mm.

As shown in fig. 3, after being cleaned by the cleaning solution, the back surface of the silicon wafer 1 is sequentially plated with an amorphous silicon layer 6, an N-type amorphous silicon layer 7 and an insulating layer 8. The insulating layer may be one or more of metal oxide, silicon nitride, and silicon oxynitride, preferably silicon nitride formed by a CVD process. This insulating layer may also be an organic coating.

As shown in fig. 4, a protective ink is covered on the back surface of the silicon wafer 1 by a screen printing method, or a second layer of pattern is defined by a method of printing photosensitive ink and then exposing, after reaction, the insulating layer 8 of the printing etching area 81 is removed by chemical cleaning, and the insulating layer 8 can also be removed by directly printing an acid etching ink on the area 81. The etching ink can be subjected to heating and baking reaction at room temperature or at a heating and baking temperature of 20-220 ℃, the reaction time is 5-60 minutes, and the printing width is 0.03-0.9 mm. Using the mask formed by the above reaction, the amorphous silicon layer 6 and the N-type amorphous silicon layer 7 may be removed with the weak alkaline solution in the etching region 81 until the P-type amorphous silicon layer 5 is exposed.

As shown in fig. 5, a third layer of patterns is defined on the back surface of the silicon wafer 1 by covering protective ink by a screen printing method or by printing photosensitive ink and then exposing, and after reaction, the insulating layer 8 of the printed etching area 71 is removed by chemical cleaning.

As shown in fig. 6, a transparent conductive film layer 9 is plated on the back surface of the silicon wafer 1.

As shown in fig. 7, etching ink is printed on the back surface area of the silicon wafer 1, the transparent conductive film layer 9 in the printed area is removed by cleaning after reaction, and an isolation strip 91 is formed, wherein the etching ink only corrodes metal oxide, the reaction temperature is 10-220 ℃, the reaction time is 5-60 minutes, and the printing width is 0.03-0.20 mm.

As shown in FIG. 8, a metal seed layer 10, preferably a PVD seed copper layer, is plated on the back surface of the silicon wafer 1, and the thickness is 50-300 nm. The metal layer may be a combination of nickel Ni and copper Cu, a combination of titanium Ti and copper Cu, or a combination of titanium nitride TiN and copper Cu. This seed layer 10 can also be formed by means of silver paste printing.

As shown in FIG. 9, a layer of electroplating-resistant ink 11 is printed on the back surface of the silicon wafer 1 to form a grid line pattern, the printing width of the electroplating-resistant ink 11 is 0.1-0.8 mm, and the printing thickness is 3-50 um.

As shown in fig. 10, copper is electroplated on the back gate line pattern region of the silicon wafer 1 to form copper gate line electrodes 12 and 13, the copper gate lines 12 and 13 include a copper gate line layer and a copper gate line protection layer, the copper gate line protection layer is a tin layer, the widths of the copper gate lines 80a and 80b are 10-400um, and the thicknesses of the copper gate lines are 5-50 um.

As shown in FIG. 11, plating resist ink 11 on the back surface of the silicon wafer 1 is removed by a stripping solution

As shown in fig. 12, the seed layer material 10 outside the gate line region is removed.

The thicknesses of the intrinsic amorphous silicon layer 4, the P-type amorphous silicon layer 5 and the N-type amorphous silicon layer 22 are 1-20 nm, and the amorphous silicon film layer is formed through PECVD deposition. The transparent conductive film layer 50 is made of metal oxide, is one of an indium tin oxide film, an aluminum-doped zinc oxide film and a tungsten-doped indium oxide film, has a thickness of 10-200 nm, and is deposited by PVD sputtering, RPD or ion plating. The cleaning mode after the protection or etching ink reaction is at least one of soaking, spraying, ultrasonic wave and bubbling.

Due to the existence of the insulating layer, except for the amorphous silicon layer with weaker conductivity, the hole collector material and the electron collector material do not have surface contact, so that an internal short circuit mechanism is eliminated.

In addition, by adopting the technical scheme, the invention forms the carrier collecting layers in the finger-shaped crossed arrangement by adopting the printing technology, thereby being suitable for large-scale mass production.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.