Image pickup device
阅读说明：本技术 摄像元件 (Image pickup device ) 是由 佐藤好弘 于 2020-04-13 设计创作，主要内容包括：本公开的一个方式所涉及的摄像元件具备多个像素。多个像素中的各个像素包括第1光电转换层、第1像素电极、第2光电转换层、第2像素电极、第3光电转换层、第3像素电极、第1对置电极及第2对置电极。第1像素电极、第1光电转换层、第1对置电极、第2光电转换层、第2像素电极、第2对置电极、第3光电转换层及第3像素电极按照该顺序配置。(An image pickup element according to one embodiment of the present disclosure includes a plurality of pixels. Each of the plurality of pixels includes a 1 st photoelectric conversion layer, a 1 st pixel electrode, a 2 nd photoelectric conversion layer, a 2 nd pixel electrode, a 3 rd photoelectric conversion layer, a 3 rd pixel electrode, a 1 st counter electrode, and a 2 nd counter electrode. The 1 st pixel electrode, the 1 st photoelectric conversion layer, the 1 st counter electrode, the 2 nd photoelectric conversion layer, the 2 nd pixel electrode, the 2 nd counter electrode, the 3 rd photoelectric conversion layer, and the 3 rd pixel electrode are arranged in this order.)
1. An image pickup element includes a plurality of pixels,
each of the plurality of pixels includes:
a 1 st photoelectric conversion layer converting light into 1 st electric charges;
a 1 st pixel electrode collecting the 1 st charge;
a 2 nd photoelectric conversion layer which is disposed below the 1 st photoelectric conversion layer and converts light into a 2 nd electric charge;
a 2 nd pixel electrode collecting the 2 nd charge;
a 3 rd photoelectric conversion layer which is disposed below the 2 nd photoelectric conversion layer and converts light into a 3 rd electric charge;
a 3 rd pixel electrode collecting the 3 rd charge;
a 1 st counter electrode disposed between the 1 st photoelectric conversion layer and the 2 nd photoelectric conversion layer; and
a 2 nd counter electrode disposed between the 2 nd photoelectric conversion layer and the 3 rd photoelectric conversion layer,
the 1 st pixel electrode, the 1 st photoelectric conversion layer, the 1 st counter electrode, the 2 nd photoelectric conversion layer, the 2 nd pixel electrode, the 2 nd counter electrode, the 3 rd photoelectric conversion layer, and the 3 rd pixel electrode are arranged in this order.
2. The image pickup element according to claim 1,
the 1 st counter electrode is thicker than the 2 nd counter electrode.
3. The image pickup element according to claim 1,
the 2 nd counter electrode is thicker than the 1 st counter electrode.
4. The image pickup element according to claim 1,
the 1 st counter electrode is thicker than the 1 st pixel electrode.
5. The image pickup element according to claim 1,
the 1 st counter electrode is thicker than the 2 nd pixel electrode.
6. The image pickup element according to claim 1,
the 2 nd counter electrode is thicker than the 3 rd pixel electrode.
7. The image pickup element according to any one of claims 1 to 6,
the image pickup element further includes a semiconductor substrate,
the 1 st pixel electrode includes:
a 1 st accumulation electrode for accumulating the 1 st charge in the 1 st photoelectric conversion layer; and
a 1 st readout electrode electrically connected to the semiconductor substrate,
the 2 nd pixel electrode includes:
a 2 nd accumulation electrode for accumulating the 2 nd charge in the 2 nd photoelectric conversion layer; and
a 2 nd readout electrode electrically connected to the semiconductor substrate,
the 3 rd pixel electrode includes:
a 3 rd accumulation electrode for accumulating the 3 rd charge in the 3 rd photoelectric conversion layer; and
and a 3 rd readout electrode electrically connected to the semiconductor substrate.
8. An image pickup element includes a plurality of pixels,
each of the plurality of pixels includes:
a 1 st photoelectric conversion layer converting light into 1 st electric charges;
a 1 st pixel electrode collecting the 1 st charge;
a 2 nd photoelectric conversion layer which is disposed below the 1 st photoelectric conversion layer and converts light into a 2 nd electric charge;
a 2 nd pixel electrode collecting the 2 nd charge;
a 3 rd photoelectric conversion layer which is disposed below the 2 nd photoelectric conversion layer and converts light into a 3 rd electric charge;
a 3 rd pixel electrode collecting the 3 rd charge;
a 1 st counter electrode disposed between the 1 st photoelectric conversion layer and the 2 nd photoelectric conversion layer; and
a 2 nd counter electrode disposed between the 2 nd photoelectric conversion layer and the 3 rd photoelectric conversion layer,
the 1 st pixel electrode, the 1 st photoelectric conversion layer, the 1 st counter electrode, the 2 nd pixel electrode, the 2 nd photoelectric conversion layer, the 2 nd counter electrode, the 3 rd photoelectric conversion layer, and the 3 rd pixel electrode are arranged in this order.
9. The image pickup element according to claim 8,
the 1 st counter electrode is thicker than the 2 nd counter electrode.
10. The image pickup element according to claim 8,
the 2 nd counter electrode is thicker than the 1 st counter electrode.
11. The image pickup element according to claim 8,
the 1 st counter electrode is thicker than the 1 st pixel electrode.
12. The image pickup element according to claim 8,
the 2 nd counter electrode is thicker than the 2 nd pixel electrode.
13. The image pickup element according to claim 8,
the 2 nd counter electrode is thicker than the 3 rd pixel electrode.
14. The image pickup element according to any one of claims 8 to 13,
the image pickup element further includes a semiconductor substrate,
the 1 st pixel electrode includes:
a 1 st accumulation electrode for accumulating the 1 st charge in the 1 st photoelectric conversion layer; and
a 1 st readout electrode electrically connected to the semiconductor substrate,
the 2 nd pixel electrode includes:
a 2 nd accumulation electrode for accumulating the 2 nd charge in the 2 nd photoelectric conversion layer; and
a 2 nd readout electrode electrically connected to the semiconductor substrate,
the 3 rd pixel electrode includes:
a 3 rd accumulation electrode for accumulating the 3 rd charge in the 3 rd photoelectric conversion layer; and
and a 3 rd readout electrode electrically connected to the semiconductor substrate.
Technical Field
The present disclosure relates to an image pickup element.
Background
Conventionally, image pickup devices using photoelectric conversion have been widely used.
Patent document 1 discloses an image pickup element having a plurality of photoelectric conversion films.
Prior art documents
Patent document
Patent document 1 Japanese patent laid-open No. 2005-268471
Disclosure of Invention
Problems to be solved by the invention
The image pickup device has 1 problem of improving image quality.
Means for solving the problems
An image pickup element according to one embodiment of the present disclosure includes a plurality of pixels.
Each of the plurality of pixels includes:
a 1 st photoelectric conversion layer converting light into 1 st electric charges;
a 1 st pixel electrode collecting the 1 st charge;
a 2 nd photoelectric conversion layer which is disposed below the 1 st photoelectric conversion layer and converts light into a 2 nd electric charge;
a 2 nd pixel electrode collecting the 2 nd charge;
a 3 rd photoelectric conversion layer which is disposed below the 2 nd photoelectric conversion layer and converts light into a 3 rd electric charge;
a 3 rd pixel electrode collecting the 3 rd charge;
a 1 st counter electrode disposed between the 1 st photoelectric conversion layer and the 2 nd photoelectric conversion layer; and
and a 2 nd counter electrode disposed between the 2 nd photoelectric conversion layer and the 3 rd photoelectric conversion layer.
The 1 st pixel electrode, the 1 st photoelectric conversion layer, the 1 st counter electrode, the 2 nd photoelectric conversion layer, the 2 nd pixel electrode, the 2 nd counter electrode, the 3 rd photoelectric conversion layer, and the 3 rd pixel electrode are arranged in this order.
Effects of the invention
According to the technology disclosed by the invention, the image quality can be improved.
Drawings
Fig. 1 is a configuration diagram of an imaging device according to embodiment 1 of the present disclosure.
Fig. 2A is a sectional view of the image pickup element shown in fig. 1.
Fig. 2B is a cross-sectional view of an image pickup element having another configuration with a plurality of counter electrodes.
Fig. 2C is a cross-sectional view of an image pickup element having still another configuration with a plurality of counter electrodes.
Fig. 3 is a cross-sectional view of an image pickup device according to embodiment 2 of the present disclosure.
Fig. 4 is a cross-sectional view of an image pickup device according to embodiment 3 of the present disclosure.
Fig. 5 is a sectional view of the image pickup device according to embodiment 4.
Detailed Description
(knowledge as a basis for the present disclosure)
The present inventors have studied the cause of hindering the image quality improvement of the image pickup device of patent document 1. As a result, the following problems were found to exist.
In the image pickup element of patent document 1, pixel electrodes for taking out signals from the photoelectric conversion films are adjacent in the up-down direction. Specifically, the common electrode film corresponding to the counter electrode is disposed at the uppermost layer, and the photoelectric conversion film is disposed between the common electrode film and the counter electrode film corresponding to the pixel electrode. The columnar electrode corresponding to the plug does not penetrate the photoelectric conversion film in the uppermost layer, and therefore this configuration has an advantage in manufacturing. However, since the counter electrode film and the counter electrode film face each other with the insulating layer interposed therebetween, capacitive coupling is likely to occur, and electrical color mixing is likely to occur. It is advantageous to suppress electric color mixing due to capacitive coupling and improve image quality.
The present disclosure provides a technique for reducing coupling capacitance between pixel electrodes and suppressing electrical color mixing.
(summary of one embodiment according to the present disclosure)
The imaging element according to claim 1 of the present disclosure includes a plurality of pixels.
Each of the plurality of pixels includes:
a 1 st photoelectric conversion layer converting light into 1 st electric charges;
a 1 st pixel electrode collecting the 1 st charge;
a 2 nd photoelectric conversion layer which is disposed below the 1 st photoelectric conversion layer and converts light into a 2 nd electric charge;
a 2 nd pixel electrode collecting the 2 nd charge;
a 3 rd photoelectric conversion layer which is disposed below the 2 nd photoelectric conversion layer and converts light into a 3 rd electric charge;
a 3 rd pixel electrode collecting the 3 rd charge;
a 1 st counter electrode disposed between the 1 st photoelectric conversion layer and the 2 nd photoelectric conversion layer; and
and a 2 nd counter electrode disposed between the 2 nd photoelectric conversion layer and the 3 rd photoelectric conversion layer.
The 1 st pixel electrode, the 1 st photoelectric conversion layer, the 1 st counter electrode, the 2 nd photoelectric conversion layer, the 2 nd pixel electrode, the 2 nd counter electrode, the 3 rd photoelectric conversion layer, and the 3 rd pixel electrode are arranged in this order.
According to the first aspect, the image quality can be improved. Specifically, the coupling capacitance between the pixel electrodes can be reduced, and the electrical color mixture can be suppressed.
The voltage applied to the 1 st photoelectric conversion layer and the voltage applied to the 2 nd photoelectric conversion layer may be set by the 1 st counter electrode.
The imaging element according to claim 2 of the present disclosure includes a plurality of pixels.
Each of the plurality of pixels includes:
a 1 st photoelectric conversion layer converting light into 1 st electric charges;
a 1 st pixel electrode collecting the 1 st charge;
a 2 nd photoelectric conversion layer which is disposed below the 1 st photoelectric conversion layer and converts light into a 2 nd electric charge;
a 2 nd pixel electrode collecting the 2 nd charge;
a 3 rd photoelectric conversion layer which is disposed below the 2 nd photoelectric conversion layer and converts light into a 3 rd electric charge;
a 3 rd pixel electrode collecting the 3 rd charge;
a 1 st counter electrode disposed between the 1 st photoelectric conversion layer and the 2 nd photoelectric conversion layer; and
and a 2 nd counter electrode disposed between the 2 nd photoelectric conversion layer and the 3 rd photoelectric conversion layer.
The 1 st pixel electrode, the 1 st photoelectric conversion layer, the 1 st counter electrode, the 2 nd pixel electrode, the 2 nd photoelectric conversion layer, the 2 nd counter electrode, the 3 rd photoelectric conversion layer, and the 3 rd pixel electrode are arranged in this order.
According to the 2 nd aspect, the image quality can be improved. Specifically, the coupling capacitance between the pixel electrodes can be reduced, and the electrical color mixture can be suppressed.
The voltage applied to the 2 nd photoelectric conversion layer and the voltage applied to the 3 rd photoelectric conversion layer may be set by the 2 nd counter electrode.
In the 3 rd aspect of the present disclosure, for example, in the image pickup element according to the 1 st or 2 nd aspect, the 1 st counter electrode may be thicker than the 2 nd counter electrode. According to the 3 rd aspect, a level difference in the upper surface of the insulating layer formed when the image pickup element is manufactured can be alleviated.
In the 4 th aspect of the present disclosure, for example, in the image pickup element according to the 1 st or 2 nd aspect, the 2 nd counter electrode may be thicker than the 1 st counter electrode. According to the 4 th mode, the parasitic sensitivity can be reduced.
In the 5 th aspect of the present disclosure, for example, in the image pickup element according to the 1 st aspect, the 1 st counter electrode may be thicker than the 1 st pixel electrode. According to the 5 th aspect, an effect of suppressing a decrease in the bias voltage due to the resistance value of the 1 st counter electrode can be obtained.
In the 6 th aspect of the present disclosure, for example, in the image pickup element according to the 1 st aspect, the 1 st counter electrode may be thicker than the 2 nd pixel electrode. According to the 6 th aspect, an effect of suppressing a decrease in the bias voltage due to the resistance value of the 1 st counter electrode can be obtained.
In the 7 th aspect of the present disclosure, for example, in the image pickup element according to the 1 st aspect, the 2 nd counter electrode may be thicker than the 3 rd pixel electrode. According to the 7 th aspect, an effect of suppressing a decrease in the bias voltage due to the resistance value of the 2 nd counter electrode can be obtained.
In the 8 th aspect of the present disclosure, for example, in the image pickup element according to the 2 nd aspect, the 1 st counter electrode may be thicker than the 1 st pixel electrode. According to the 8 th aspect, an effect of suppressing a decrease in the bias voltage due to the resistance value of the 1 st counter electrode can be obtained.
In a 9 th aspect of the present disclosure, for example, in the image pickup element according to the 2 nd aspect, the 2 nd counter electrode may be thicker than the 2 nd pixel electrode. According to the 9 th aspect, an effect of suppressing a decrease in the bias voltage due to the resistance value of the 2 nd counter electrode can be obtained.
In the 10 th aspect of the present disclosure, for example, in the image pickup element according to the 2 nd aspect, the 2 nd counter electrode may be thicker than the 3 rd pixel electrode. According to the 10 th aspect, an effect of suppressing a decrease in the bias voltage due to the resistance value of the 2 nd counter electrode can be obtained.
In an 11 th aspect of the present disclosure, for example, the imaging element according to any one of 1 st to 10 th aspects may further include a semiconductor substrate, and the 1 st pixel electrode may include: a 1 st accumulation electrode for accumulating the 1 st charge in the 1 st photoelectric conversion layer; and a 1 st readout electrode electrically connected to the semiconductor substrate, the 2 nd pixel electrode may include: a 2 nd accumulation electrode for accumulating the 2 nd charge in the 2 nd photoelectric conversion layer; and a 2 nd readout electrode electrically connected to the semiconductor substrate, the 3 rd pixel electrode may include: a 3 rd accumulation electrode for accumulating the 3 rd charge in the 3 rd photoelectric conversion layer; and a 3 rd readout electrode electrically connected to the semiconductor substrate.
The imaging element according to claim 12 of the present disclosure includes a plurality of pixels,
each of the plurality of pixels has:
a 1 st photoelectric conversion layer;
a 1 st pixel electrode collecting charges generated by the 1 st photoelectric conversion layer;
a 2 nd photoelectric conversion layer disposed below the 1 st photoelectric conversion layer;
a 2 nd pixel electrode collecting charges generated by the 2 nd photoelectric conversion layer;
a 3 rd photoelectric conversion layer disposed below the 2 nd photoelectric conversion layer;
a 3 rd pixel electrode collecting charges generated by the 3 rd photoelectric conversion layer;
a shared 1 st counter electrode disposed between the 1 st photoelectric conversion layer and the 2 nd photoelectric conversion layer; and
and a 2 nd counter electrode disposed between the 2 nd photoelectric conversion layer and the 3 rd photoelectric conversion layer.
According to the 12 th aspect, the image quality can be improved. Specifically, the coupling capacitance between the pixel electrodes can be reduced, and the electrical color mixture can be suppressed.
The imaging element according to claim 13 of the present disclosure includes a plurality of pixels,
each of the plurality of pixels has:
a 1 st photoelectric conversion layer;
a 1 st pixel electrode collecting charges generated by the 1 st photoelectric conversion layer;
a 2 nd photoelectric conversion layer disposed below the 1 st photoelectric conversion layer;
a 2 nd pixel electrode collecting charges generated by the 2 nd photoelectric conversion layer;
a 3 rd photoelectric conversion layer disposed below the 2 nd photoelectric conversion layer;
a 3 rd pixel electrode collecting charges generated by the 3 rd photoelectric conversion layer;
a 1 st counter electrode disposed between the 1 st photoelectric conversion layer and the 2 nd photoelectric conversion layer; and
and a 2 nd counter electrode shared between the 2 nd photoelectric conversion layer and the 3 rd photoelectric conversion layer.
According to the 13 th aspect, the image quality can be improved. Specifically, the coupling capacitance between the pixel electrodes can be reduced, and the electrical color mixture can be suppressed.
Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments.
(embodiment 1)
Fig. 1 shows a configuration of an imaging apparatus 100A according to embodiment 1 of the present disclosure. The imaging device 100A includes an imaging element 100. The imaging element 100 includes a semiconductor substrate 1 and a plurality of pixels 10. A plurality of pixels 10 are disposed over the semiconductor substrate 1. Each pixel 10 is supported by the semiconductor substrate 1. A part of the pixel 10 may be formed of the semiconductor substrate 1.
The semiconductor substrate 1 may be a circuit substrate including various electronic circuits. The semiconductor substrate 1 is made of, for example, an Si substrate.
Each pixel 10 includes a photoelectric conversion portion 12. The photoelectric conversion portion 12 receives light incidence and generates positive and negative charges, typically hole-electron pairs. The photoelectric conversion portion 12 includes at least 1 photoelectric conversion layer disposed above the semiconductor substrate 1. In fig. 1, the photoelectric conversion portions 12 of the respective pixels 10 are shown spatially separated from each other. However, this is merely for convenience of explanation. The photoelectric conversion portions 12 of the plurality of pixels 10 may be arranged continuously on the semiconductor substrate 1 without any space therebetween.
In fig. 1, the pixels 10 are arranged in a plurality of rows and a plurality of columns of m rows and n columns. m and n are independent of each other and represent an integer of 1 or more. The pixels 10 are arranged, for example, in 2 dimensions on the semiconductor substrate 1, thereby forming an imaging region. When the image pickup apparatus 100A is viewed in a plan view, the image pickup element 100 may be defined as a region where a photoelectric conversion layer exists.
The number and arrangement of the pixels 10 are not particularly limited. In fig. 1, the center of each pixel 10 is located on a lattice point of a square lattice. The plurality of pixels 10 may be arranged such that the center of each pixel 10 is located on a lattice point such as a triangular lattice, a hexagonal lattice, or the like. By arranging the pixels 10 in 1-dimension, the image pickup element 100 can be used as a line sensor.
The imaging device 100A has a peripheral circuit formed on the semiconductor substrate 1.
The peripheral circuits include a vertical scanning circuit 52 and a horizontal signal readout circuit 54. The peripheral circuit may additionally include a control circuit 56 and a voltage supply circuit 58. The peripheral circuit may further include a signal processing circuit, an output circuit, and the like. Each circuit is provided over the semiconductor substrate 1. A part of the peripheral circuit may be disposed on a different substrate from the semiconductor substrate 1 on which the pixels 10 are formed.
The vertical scanning circuit 52 is also referred to as a row scanning circuit. The address signal lines 44 are provided corresponding to the respective rows of the plurality of pixels 10, and the address signal lines 44 are connected to the vertical scanning circuit 52. The signal lines provided corresponding to the respective rows of the plurality of pixels 10 are not limited to the address signal lines 44, and a plurality of types of signal lines may be connected to the vertical scanning circuit 52 for each of the respective rows of the plurality of pixels 10. The horizontal signal readout circuit 54 is also referred to as a column scanning circuit. Vertical signal lines 45 are provided corresponding to respective columns of the plurality of pixels 10, and the vertical signal lines 45 are connected to a horizontal signal readout circuit 54.
The control circuit 56 receives command data, a clock, and the like given from the outside of the imaging apparatus 100A, and controls the entire imaging apparatus 100A. Typically, the control circuit 56 has a timing generator, and supplies drive signals to the vertical scanning circuit 52, the horizontal signal reading circuit 54, the voltage supply circuit 58, and the like. The control circuit 56 may be implemented, for example, by a microcontroller containing more than 1 processor. The function of the control circuit 56 may be realized by a combination of general-purpose processing circuits and software, or may be realized by hardware specialized for such processing.
The voltage supply circuit 58 supplies a predetermined voltage to each pixel 10 via the voltage line 48. The voltage supply circuit 58 is not limited to a specific power supply circuit, and may be a circuit that converts a voltage supplied from a power supply such as a battery into a predetermined voltage, or may be a circuit that generates a predetermined voltage. The voltage supply circuit 58 may be a part of the vertical scanning circuit 52 described above. These circuits constituting the peripheral circuit may be arranged in the peripheral region R2 outside the image pickup element 100.
Fig. 2A shows a cross section of the image pickup element 100.
Each pixel 10 has a plurality of photoelectric conversion layers 121, 122, and 123. The plurality of photoelectric conversion layers 121, 122, and 123 include a 1 st photoelectric conversion layer 121, a 2 nd photoelectric conversion layer 122, and a 3 rd photoelectric conversion layer 123. The 1 st photoelectric conversion layer 121 may be a single layer common to the plurality of pixels 10. The 2 nd photoelectric conversion layer 122 may be a single layer common to the plurality of pixels 10. The 3 rd photoelectric conversion layer 123 may be a single layer common to the plurality of pixels 10. However, each of the photoelectric conversion layers 121, 122, and 123 may be divided for each pixel. "shared by a plurality of pixels" means shared between a specific pixel and at least 1 pixel adjacent to the specific pixel.
The following structure can be employed regardless of whether the photoelectric conversion layer is a single layer or is divided for each pixel. Between adjacent pixels, the 1 st photoelectric conversion layer 121 is electrically connected. Between adjacent pixels, the 2 nd photoelectric conversion layer 122 is electrically connected. Between adjacent pixels, the 3 rd photoelectric conversion layer 123 is electrically connected. That is, a part of the 1 st photoelectric conversion layer 121 in a specific pixel 10 (1 st pixel) arbitrarily selected from the plurality of pixels 10 is electrically connected to a part of the 1 st photoelectric conversion layer 121 in a pixel 10 adjacent to the specific pixel 10 among the plurality of pixels 10. A part of the 2 nd photoelectric conversion layer 122 in a specific pixel 10 (2 nd pixel) arbitrarily selected from the plurality of pixels 10 is electrically connected to a part of the 2 nd photoelectric conversion layer 122 in a pixel 10 adjacent to the specific pixel 10 among the plurality of pixels 10. A part of the 3 rd photoelectric conversion layer 123 in a specific pixel 10 (3 rd pixel) arbitrarily selected from the plurality of pixels 10 is electrically connected to a part of the 3 rd photoelectric conversion layer 123 in a pixel 10 adjacent to the specific pixel 10 among the plurality of pixels 10. If the technique of the present disclosure is applied to such a structure, an effect of suppressing color mixture between pixels can be obtained.
The photoelectric conversion layers 121, 122, and 123 are made of a photoelectric conversion material. The photoelectric conversion material is typically an organic material.
The 1 st photoelectric conversion layer 121 collects charges (1 st charges) corresponding to the 1 st wavelength band of light. The 2 nd photoelectric conversion layer 122 collects charges (2 nd charges) corresponding to the 2 nd wavelength band of light. The 3 rd photoelectric conversion layer 123 collects charges (3 rd charges) corresponding to the 3 rd band light. The 1 st wavelength band is, for example, a wavelength band of blue light. The 1 st photoelectric conversion layer 121 is made of a material having sensitivity to blue light. The 2 nd wavelength band is, for example, a wavelength band of green light. The 2 nd photoelectric conversion layer 122 is made of a material having sensitivity to green light. The 3 rd wavelength band is, for example, a wavelength band of red light. The 3 rd photoelectric conversion layer 123 is made of a material having sensitivity to red light.
In the present embodiment, the 1 st photoelectric conversion layer 121, the 2 nd photoelectric conversion layer 122, the 3 rd photoelectric conversion layer 123, and the semiconductor substrate 1 are arranged in this order. A 2 nd photoelectric conversion layer 122 is disposed below the 1 st photoelectric conversion layer 121. A 33 nd photoelectric conversion layer 123 is disposed below the 2 nd photoelectric conversion layer 122. A 2 nd photoelectric conversion layer 122 is disposed between the 1 st photoelectric conversion layer 121 and the semiconductor substrate 1 in the normal direction of the semiconductor substrate 1. A 3 rd photoelectric conversion layer 123 is disposed between the 2 nd photoelectric conversion layer 122 and the semiconductor substrate 1 in the normal direction of the semiconductor substrate 1. The order of arrangement of the photoelectric conversion layers 121, 122, and 123 is not limited to this order. In general, the photoelectric conversion material that absorbs blue light has low sensitivity, and therefore it is advantageous that a layer having sensitivity to blue light is located on the uppermost layer.
In the present specification, "upper" and "lower" are determined with reference to the traveling direction of light. The side close to the light entrance surface is "upper" and the side far from the light entrance surface is "lower".
Each pixel 10 also has a plurality of pixel electrodes 13, 14, and 15. The plurality of pixel electrodes 13, 14 and 15 include a 1 st pixel electrode 13, a 2 nd pixel electrode 14 and a 3 rd pixel electrode 15. The 1 st pixel electrode 13 is electrically connected to the 1 st photoelectric conversion layer 121. The 2 nd pixel electrode 14 is electrically connected to the 2 nd photoelectric conversion layer 122. The 3 rd pixel electrode 15 is electrically connected to the 3 rd photoelectric conversion layer 123.
The 1 st pixel electrode 13 and the 2 nd pixel electrode 14 are transparent electrodes having transparency to visible light and/or near-infrared light. The transparent electrode is made of a transparent conductive Oxide such as ITO (Indium Tin Oxide). The 3 rd pixel electrode 15 is a non-transparent electrode having no optical transparency to visible light and/or near-infrared light. Examples of the material of the non-transparent electrode include a metal, a metal oxide, a metal nitride, conductive polysilicon, and the like.
In the present specification, "having light transmittance" means that the transmittance of light in a specific wavelength band is 40% or more. The wavelength band of visible light is, for example, 400nm to 780 nm. The wavelength band of the near infrared light is, for example, 780nm to 2000 nm. The transmittance can be calculated by the method specified in japanese industrial standard JIS R3106 (1998).
Each pixel 10 further includes a plurality of counter electrodes 17 and 18. The plurality of counter electrodes 17 and 18 include a 1 st counter electrode 17 and a 2 nd counter electrode 18. The counter electrodes 17 and 18 may be transparent electrodes having transparency to visible light and/or near-infrared light, respectively.
The 1 st counter electrode 17 may be a single layer common to a plurality of pixels 10. The 2 nd counter electrode 18 may be a single layer common to a plurality of pixels 10. However, the counter electrodes 17 and 18 may be divided for each pixel.
The following structure can be adopted regardless of whether the counter electrode is a single layer or is divided for each pixel. That is, a part of the 1 st counter electrode 17 in a specific pixel 10 arbitrarily selected from the plurality of pixels 10 is electrically connected to a part of the 1 st counter electrode 17 in a pixel 10 adjacent to the specific pixel 10. A part of the 2 nd counter electrode 18 in a specific pixel 10 arbitrarily selected from the plurality of pixels 10 is electrically connected to a part of the 2 nd counter electrode 18 in a pixel 10 adjacent to the specific pixel 10.
Fig. 2B shows an image pickup device 100B having another configuration including a plurality of counter electrodes 17 and 18. Fig. 2C shows an image pickup device 100C having still another configuration with a plurality of counter electrodes 17 and 18. As shown in fig. 2B and 2C, the plurality of counter electrodes 17 and 18 may have different thicknesses.
For example, as shown in fig. 2B, the 1 st counter electrode 17 may be thicker than the 2 nd counter electrode 18. That is, the thickness of the counter electrode may be increased as the distance from the semiconductor substrate 1 to the light incident surface is increased. This can alleviate a step in the upper surface of the insulating layer formed when the image pickup element 100 is manufactured.
Alternatively, as shown in fig. 2C, the 2 nd counter electrode 18 may be thicker than the 1 st counter electrode 17. That is, the thickness of the counter electrode may be increased as the light enters from the light entrance surface toward the semiconductor substrate 1. This can further suppress photoelectric conversion caused by light incident on the semiconductor substrate 1, thereby reducing the parasitic sensitivity.
The thickness of the pixel electrode may be determined by the following method. A cross section parallel to the normal direction of the semiconductor substrate 1 is formed. The cross section is observed by an electron microscope (e.g., a scanning electron microscope). The thickness of the pixel electrode is measured at an arbitrary plurality of positions (for example, 5 positions) included in the obtained image. The average value of the measured values can be regarded as the thickness of the pixel electrode. The "thickness" is a dimension in a direction parallel to the normal direction of the semiconductor substrate 1. The thickness of the counter electrode can be determined by the same method as that for the pixel electrode.
As shown in fig. 2A, the insulating layer 8 is provided between the 2 nd pixel electrode 14 and the 2 nd counter electrode 18. An insulating layer 9 is provided between the 3 rd pixel electrode 15 and the semiconductor substrate 1. The insulating layers 8 and 9 are made of SiO2Etc. of an insulating material.
The insulating layers 8 and 9 may have different dielectric constants from each other. For example, the dielectric constant of the insulating layer 8 may be lower than that of the insulating layer 9. This can expect an effect of suppressing capacitive coupling between the 3 rd pixel electrode 15 and the 2 nd pixel electrode 14. To make the dielectric constants different, it is possible to select from SiO2An appropriate material is selected from materials such as SiOF and SiOC. The same material may be used to make the dielectric constants different.
Each pixel 10 also has a plurality of plugs 31, 32 and 33. Each of the plugs 31, 32, and 33 extends in the normal direction of the semiconductor substrate 1. The plurality of plugs 31, 32, and 33 include the 1 st plug 31, the 2 nd plug 32, and the 3 rd plug 33. The 1 st plug 31 electrically connects the semiconductor substrate 1 and the 1 st pixel electrode 13. The 2 nd plug 32 electrically connects the semiconductor substrate 1 and the 2 nd pixel electrode 14. The 3 rd plug 33 electrically connects the semiconductor substrate 1 and the 3 rd pixel electrode 15.
The plugs 31, 32 and 33 are made of a conductive material. Examples of the conductive material include a metal, a metal oxide, a metal nitride, conductive polysilicon, and the like.
The semiconductor substrate 1 has a plurality of charge accumulation regions 3, 4, and 5. The charge accumulation regions 3, 4, and 5 may be part of the pixel 10. Each of the charge accumulating regions 3, 4, and 5 is an n-type or p-type impurity region. The plurality of charge accumulation regions 3, 4, and 5 include a 1 st charge accumulation region 3, a 2 nd charge accumulation region 4, and a 3 rd charge accumulation region 5. The 1 st plug 31 electrically connects the 1 st charge accumulation region 3 and the 1 st pixel electrode 13. The 2 nd plug 32 electrically connects the 2 nd charge accumulation region 4 and the 2 nd pixel electrode 14. The 3 rd plug 33 electrically connects the 3 rd charge accumulation region 5 and the 3 rd pixel electrode 15.
Each pixel 10 may be provided with a microlens. The microlens may be configured to constitute a surface of the image pickup element 100. The number of microlenses may be 1 or more for each 1 pixel 10. The microlens may be disposed so as to converge on an overlapping region of the 1 st pixel electrode 13 and the 2 nd pixel electrode 14 when the image pickup element 100 is viewed in a plan view.
The semiconductor substrate 1 may have a plurality of transistors for reading out the charges accumulated in the charge accumulation regions 3, 4, and 5 or resetting the accumulated charges.
The pixel electrode may be electrically connected to the charge accumulation region via a plug penetrating the semiconductor substrate and a wiring layer below the semiconductor substrate.
When light is irradiated to the image pickup element 10, electron-hole pairs are generated in the respective photoelectric conversion layers 121, 122, and 123.
For example, if a voltage is applied between the 1 st counter electrode 17 and the 1 st pixel electrode 13 so that the potential of the 1 st counter electrode 17 is higher than the potential of the 1 st pixel electrode 13, holes that are positive charges are collected to the 1 st pixel electrode 13, and electrons that are negative charges are collected to the 1 st counter electrode 17. Holes collected in the 1 st pixel electrode 13 are accumulated in the 1 st plug 31 and the 1 st charge accumulation region 3.
When a voltage is applied between the 1 st counter electrode 17 and the 2 nd pixel electrode 14 so that the potential of the 1 st counter electrode 17 is higher than the potential of the 2 nd pixel electrode 14, holes that are positive charges are collected in the 2 nd pixel electrode 14, and electrons that are negative charges are collected in the 1 st counter electrode 17. Holes collected in the 2 nd pixel electrode 14 are accumulated in the 2 nd plug 32 and the 2 nd charge accumulation region 4.
The thickness of the 1 st counter electrode 17 may be different from the thickness of the 1 st pixel electrode 13. As shown in fig. 2B, the 1 st counter electrode 17 may be thicker than the 1 st pixel electrode 13. By making the 1 st counter electrode 17 thicker, the resistance value of the 1 st counter electrode 17 can be made smaller. This can provide an effect of suppressing a decrease in the bias voltage due to the resistance value of the 1 st counter electrode 17.
The thickness of the 1 st counter electrode 17 may be different from the thickness of the 2 nd pixel electrode 14. As shown in fig. 2B, the 1 st counter electrode 17 may be thicker than the 2 nd pixel electrode 14. By making the 1 st counter electrode 17 thicker, the resistance value of the 1 st counter electrode 17 can be made smaller. This can provide an effect of suppressing a decrease in the bias voltage due to the resistance value of the 1 st counter electrode 17.
When a voltage is applied between the 2 nd counter electrode 18 and the 3 rd pixel electrode 15 so that the potential of the 2 nd counter electrode 18 is higher than the potential of the 3 rd pixel electrode 15, holes that are positive charges are collected in the 3 rd pixel electrode 15, and electrons that are negative charges are collected in the 2 nd counter electrode 18. Holes collected in the 3 rd pixel electrode 15 are accumulated in the 3 rd plug 33 and the 3 rd charge accumulation region 5.
The thickness of the 2 nd counter electrode 18 may be different from the thickness of the 3 rd pixel electrode 15. As shown in fig. 2C, the 2 nd counter electrode 18 may be thicker than the 3 rd pixel electrode 15. By making the 2 nd counter electrode 18 thicker, the resistance value of the 2 nd counter electrode 18 can be reduced. This can provide an effect of suppressing a decrease in the bias voltage due to the resistance value of the 2 nd counter electrode 18.
A blocking layer that blocks the inflow of dark-time electric charges to the pixel electrode may be provided between the pixel electrode and the photoelectric conversion layer.
The image pickup element 100 of the present embodiment has a multilayer structure. "multilayer" means that a plurality of photoelectric conversion layers are present in the normal direction of the semiconductor substrate 1. The multilayer structure can sufficiently secure the area of the pixel electrode, and is advantageous for improving the sensitivity of the pixel. In this embodiment, since there are 3 photoelectric conversion layers 121, 122, and 123, the image pickup element 100 can be said to have a 3-layer structure. The photoelectric conversion layers 121, 122, and 123 typically have mutually different photoelectric conversion characteristics.
According to the image pickup element 100 having the 3-layer configuration, the 3-layer photoelectric conversion layer may include a photoelectric conversion layer having sensitivity to blue light, a photoelectric conversion layer having sensitivity to green light, and a photoelectric conversion layer having sensitivity to red light. Therefore, the 3-layer configuration is suitable for forming a full-color image.
In this embodiment, the 1 st counter electrode 17 is disposed between the 1 st photoelectric conversion layer 121 and the 2 nd photoelectric conversion layer 122. The 2 nd counter electrode 18 is disposed between the 2 nd photoelectric conversion layer 122 and the 3 rd photoelectric conversion layer 123. The 1 st counter electrode 17 is an electrode shared by the 1 st photoelectric conversion layer 121 and the 2 nd photoelectric conversion layer 122. Between the 2 nd photoelectric conversion layer 121 and the 3 rd photoelectric conversion layer 123, the 2 nd counter electrode 18 and the 3 rd photoelectric conversion layer 123 are electrically in contact with each other. The "shared electrode" means that the same voltage is applied to the 1 st photoelectric conversion layer 121 and the 2 nd photoelectric conversion layer 122 from the 1 st counter electrode 17.
That is, the 1 st pixel electrode 13, the 1 st photoelectric conversion layer 121, the 1 st counter electrode 17, the 2 nd pixel electrode 14, the 2 nd photoelectric conversion layer 122, the 2 nd counter electrode 18, the 3 rd photoelectric conversion layer 123, and the 3 rd pixel electrode 15 are arranged in this order. This positional relationship is also established in other embodiments.
Since a predetermined voltage (for example, +10V) is applied to the 1 st counter electrode 17 and the 2 nd counter electrode 18, the 1 st counter electrode 17 and the 2 nd counter electrode 18 can function as an electric shield. The 1 st pixel electrode 13 and the 2 nd pixel electrode 14 are electrically shielded by the 1 st counter electrode 17. Thereby, capacitive coupling between the 1 st pixel electrode 13 and the 2 nd pixel electrode 14 is suppressed. Since the 2 nd counter electrode 18 is disposed between the 2 nd pixel electrode 14 and the 3 rd pixel electrode 15, the 2 nd pixel electrode 14 and the 3 rd pixel electrode 15 are electrically shielded by the 2 nd counter electrode 18. Thereby, the capacitive coupling between the 2 nd pixel electrode 14 and the 3 rd pixel electrode 13 is suppressed.
According to the present embodiment, the 1 st pixel electrode 13, the 1 st counter electrode 17, and the 2 nd pixel electrode 14 are arranged in this order above the semiconductor substrate 1. This configuration is advantageous from the viewpoint of suppressing color mixing due to electrical causes.
The following describes other embodiments. The same reference numerals are given to elements common to embodiment 1 and other embodiments, and descriptions thereof may be omitted. The descriptions related to the respective embodiments can be applied to each other as long as they are not technically contradictory. The embodiments may be combined with each other as long as technical contradictions are not present.
(embodiment 2)
Fig. 3 shows a cross section of an image pickup device 200 according to embodiment 2 of the present disclosure. In this embodiment, the 2 nd counter electrode 18 is an electrode shared by the 2 nd photoelectric conversion layer 122 and the 3 rd photoelectric conversion layer 123. Between the 1 st photoelectric conversion layer 121 and the 2 nd photoelectric conversion layer 122, the 1 st counter electrode 17 is in contact with the 1 st photoelectric conversion layer 121.
The 1 st pixel electrode 13 and the 2 nd pixel electrode 14 are electrically shielded by the 1 st counter electrode 17. Thereby, capacitive coupling between the 1 st pixel electrode 13 and the 2 nd pixel electrode 14 is suppressed. Since the 2 nd counter electrode 18 is disposed between the 2 nd pixel electrode 14 and the 3 rd pixel electrode 15, the 2 nd pixel electrode 14 and the 3 rd pixel electrode 15 are electrically shielded by the 2 nd counter electrode 18. Thereby, the capacitive coupling between the 2 nd pixel electrode 14 and the 3 rd pixel electrode 15 is suppressed.
The 1 st counter electrode 17 may be thicker than the 1 st pixel electrode 13. As described in embodiment 1 with reference to fig. 2B, the effect of suppressing a decrease in the bias voltage due to the resistance value of the 1 st counter electrode 17 can be obtained.
The 2 nd counter electrode 18 may be thicker than the 2 nd pixel electrode 14. As described in embodiment 1 with reference to fig. 2C, the effect of suppressing the decrease in the bias voltage due to the resistance value of the 2 nd counter electrode 18 can be obtained.
The 2 nd counter electrode 18 may be thicker than the 3 rd pixel electrode 15. As described in embodiment 1 with reference to fig. 2C, the effect of suppressing the decrease in the bias voltage due to the resistance value of the 2 nd counter electrode 18 can be obtained.
(embodiment 3)
Fig. 4 shows a cross section of an image pickup device 300 according to embodiment 3 of the present disclosure. Each pixel 10 of the imaging element 300 further includes a 3 rd counter electrode 19, a 4 th photoelectric conversion layer 124, a 4 th pixel electrode 16, a 4 th plug 34, and a 4 th charge accumulation region 6.
The 4 th photoelectric conversion layer 124 is disposed between the 3 rd photoelectric conversion layer 123 and the semiconductor substrate 1. Specifically, the 4 th pixel electrode 16 is disposed between the 4 th photoelectric conversion layer 124 and the semiconductor substrate 1. The 4 th pixel electrode 16 is electrically connected to the 4 th photoelectric conversion layer 124. The 4 th pixel electrode 16 collects charges corresponding to the 4 th band of light. The 4 th wavelength band is, for example, a wavelength band of near infrared light. That is, the 1 st photoelectric conversion layer 121, the 2 nd photoelectric conversion layer 122, and the 3 rd photoelectric conversion layer 123 are layers for forming a full-color image, and the 4 th photoelectric conversion layer 124 is a layer for forming an image based on near-infrared light. The 3 rd counter electrode 19 is disposed between the 3 rd pixel electrode 15 and the 4 th photoelectric conversion layer 124. An insulating layer 7 is provided between the 3 rd pixel electrode 15 and the 4 th photoelectric conversion layer 124.
In this embodiment, the 1 st counter electrode 17 is an electrode shared by the 1 st photoelectric conversion layer 121 and the 2 nd photoelectric conversion layer 122. Between the 2 nd photoelectric conversion layer 122 and the 3 rd photoelectric conversion layer 123, the 2 nd counter electrode 18 and the 3 rd photoelectric conversion layer 123 are electrically in contact with each other. Between the 3 rd photoelectric conversion layer 123 and the 4 th photoelectric conversion layer 124, the 3 rd counter electrode 19 and the 4 th photoelectric conversion layer 124 are electrically in contact with each other.
The 1 st pixel electrode 13 and the 2 nd pixel electrode 14 are electrically shielded by the 1 st counter electrode 17. Thereby, capacitive coupling between the 1 st pixel electrode 13 and the 2 nd pixel electrode 14 is suppressed. The 2 nd pixel electrode 14 and the 3 rd pixel electrode 15 are electrically shielded by the 2 nd counter electrode 18. Thereby, the capacitive coupling between the 2 nd pixel electrode 14 and the 3 rd pixel electrode 15 is suppressed. The 3 rd pixel electrode 15 and the 4 th pixel electrode 16 are electrically shielded by the 3 rd counter electrode 19. Thereby, capacitive coupling between the 3 rd pixel electrode 15 and the 4 th pixel electrode 16 is suppressed.
(embodiment 4)
Fig. 5 shows a cross section of an image pickup device 400 according to embodiment 4 of the present disclosure. The image pickup element 400 is different from the image pickup element of the previous embodiment in the configuration of the electrodes. In the imaging element 400, the 1 st pixel electrode 13 includes a 1 st accumulation electrode 13a, a 1 st readout electrode 13b, and a 1 st transfer electrode 13 c. The 2 nd pixel electrode 14 includes a 2 nd accumulation electrode 14a, a 2 nd readout electrode 14b, and a 2 nd transfer electrode 14 c. The 3 rd pixel electrode 15 includes a 3 rd accumulation electrode 15a, a 3 rd readout electrode 15b, and a 3 rd transfer electrode 15 c. The transfer electrodes 13c, 14c and 15c may be omitted.
An insulating layer 11 is provided above the 1 st photoelectric conversion layer 121. A 1 st semiconductor layer 27 is provided between the 1 st pixel electrode 13 and the 1 st photoelectric conversion layer 121. A part of the insulating layer 11 exists between the 1 st semiconductor layer 27 and the 1 st pixel electrode 13. The 2 nd semiconductor layer 28 is provided between the 2 nd pixel electrode 14 and the 2 nd photoelectric conversion layer 122. A portion of the insulating layer 8 is present between the 2 nd semiconductor layer 28 and the 2 nd pixel electrode 14. A 3 rd semiconductor layer 29 is disposed between the 3 rd pixel electrode 15 and the 3 rd photoelectric conversion layer 123. A part of the insulating layer 9 exists between the 3 rd semiconductor layer 29 and the 3 rd pixel electrode 15. The semiconductor layers 27, 28, and 29 are provided for more efficient charge accumulation, and are made of a light-transmitting semiconductor material.
The 1 st accumulation electrode 13a and the 1 st transfer electrode 13c face the 1 st photoelectric conversion layer 121 through a part of the insulating layer 11 or through a part of the insulating layer 11 and the 1 st semiconductor layer 27. At least a part of the 1 st readout electrode 13b is in contact with the 1 st photoelectric conversion layer 121 directly or through the 1 st semiconductor layer 27. A 1 st plug 31 is connected to the 1 st readout electrode 13 b. The 1 st accumulation electrode 13a, the 1 st readout electrode 13b, and the 1 st transfer electrode 13c are electrically connected to wiring lines not shown. Desired voltages can be applied to the 1 st accumulation electrode 13a, the 1 st readout electrode 13b, and the 1 st transfer electrode 13c, respectively. The 1 st accumulation electrode 13a can function as an electrode for accumulating electric charges generated in the 1 st photoelectric conversion layer 121 by attracting the electric charges generated in the 1 st photoelectric conversion layer 121 in accordance with the applied voltage, and accumulate the electric charges in the 1 st photoelectric conversion layer 121. When the image pickup device 400 is viewed in plan, the 1 st transfer electrode 13c is disposed between the 1 st accumulation electrode 13a and the 1 st readout electrode 13 b. The 1 st transfer electrode 13c functions to block the accumulated electric charges or control the transfer of the electric charges. By controlling the voltages applied to the 1 st storage electrode 13a, the 1 st readout electrode 13b, and the 1 st transfer electrode 13c, it is possible to store the electric charges generated in the 1 st photoelectric conversion layer 121 or at the interface of the 1 st photoelectric conversion layer 121, or to extract the generated electric charges from the 1 st electric charge storage region 3. These descriptions regarding the 1 st pixel electrode 13 can also be applied to the 2 nd pixel electrode 14 and the 3 rd pixel electrode 15 by replacing "1 st" with "2 nd" or "3 rd".
According to the structure of the electrode of the present embodiment, the electric charges generated in the photoelectric conversion layer can be effectively collected and transferred, which contributes to improvement of sensitivity. The structure of the electrode of the present embodiment can be applied to all the embodiments described above.
Industrial applicability
The technique disclosed in the present specification is useful for an image pickup device. The image pickup element can be applied to an image pickup device, an optical sensor, and the like. Examples of the imaging device include a digital camera, a medical camera, a monitoring camera, a robot camera, and a vehicle camera.
Description of reference numerals:
1 semiconductor substrate
3 st 1 charge accumulation region
4 nd 2 nd charge accumulation region
5 3 rd charge accumulation region
6 th 4 charge accumulation region
10 pixels
12 photoelectric conversion part
13 1 st pixel electrode
14 nd 2 nd pixel electrode
15 No. 3 pixel electrode
16 th pixel electrode
17 st counter electrode
18 nd 2 nd counter electrode
19 rd 3 opposite electrode
31 st plug
32 nd 2 nd plug
33 rd 3 plug
34 th plug
100. 100b, 100c, 200, 300, 400 image pickup element
100A image pickup apparatus
121 st photoelectric conversion layer
122 nd photoelectric conversion layer
123 rd 3 photoelectric conversion layer
124 th photoelectric conversion layer