阅读说明：本技术 开关的驱动装置 (Driving device of switch ) 是由 丹羽雅之 蘭明文 于 2020-02-27 设计创作，主要内容包括：驱动装置进行互相并联连接的多个开关(SW1、SW2)的驱动控制。多个开关包括具有不同的短路容限的开关。驱动装置包括：判断部(91、92),该判断部对多个开关中的至少一个开关有过电流流过的情况进行判断；以及过电流保护部(60),在由判断部判断为有过电流流过的情况下,该过电流保护部将多个开关切换为断开状态。过电流保护部将多个开关中的短路容限最小的开关即最小容限开关(SW1)首先切换为断开状态。(The drive device performs drive control of a plurality of switches (SW1, SW2) connected in parallel with each other. The plurality of switches includes switches having different short circuit tolerances. The drive device includes: determination units (91, 92) that determine that an overcurrent has flowed through at least one of the plurality of switches; and an overcurrent protection unit (60) that switches the plurality of switches to an off state when the determination unit determines that an overcurrent has flowed. The overcurrent protection unit switches a minimum-tolerance switch (SW1), which is the switch having the smallest short-circuit tolerance among the plurality of switches, to an off state first.)

1. A driving device of switches which performs driving control of a plurality of switches (SW1, SW2) connected in parallel with each other,

a plurality of said switches comprising switches having different short circuit tolerances,

the driving device of the switch comprises:

determination units (91, 92) that determine that an overcurrent has flowed through at least one of the plurality of switches; and

an overcurrent protection unit (60) that switches the plurality of switches to an off state when the determination unit determines that an overcurrent has flowed,

the overcurrent protection unit switches a minimum-tolerance switch (SW1), which is a switch having the smallest short-circuit tolerance among the plurality of switches, to an off state first.

2. The drive device of a switch according to claim 1,

when the plurality of switches are switched to the off state, the overcurrent protection unit increases the switching speed of the minimum-margin switch among the plurality of switches to be higher than the switching speed of the remaining switches (SW 2).

3. The drive device of a switch according to claim 1 or 2,

the overcurrent protection unit switches the minimum-margin switch of the plurality of switches to an off state, and then switches the remaining switches to the off state.

4. A drive device of a switch according to any one of claims 1 to 3,

when the determination unit determines that an overcurrent flows through any of the plurality of switches, the overcurrent protection unit switches the minimum-margin switch to the off state first.

Technical Field

The present disclosure relates to a driving apparatus of a switch.

Background

Conventionally, as described in patent document 1, for example, a driving device for driving an IGBT formed of an Si device is known. When it is determined that an overcurrent flows through the IGBT, the drive device switches the IGBT to the off state, thereby protecting the IGBT.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open No. 2012-65530

Disclosure of Invention

As the driving device, there is a device that: the IGBT and the MOSFET connected in parallel to the IGBT and composed of a SiC device are driven. Here, the short-circuit tolerance of the MOSFET is lower than that of the IGBT. Therefore, a technique is desired which can appropriately protect a MOSFET having a low short-circuit tolerance when an overcurrent flows through a parallel connection body of the MOSFET and the IGBT.

In addition, a technique is desired that is not limited to the MOSFET and the IGBT connected in parallel to each other, but can also appropriately protect a plurality of switches connected in parallel to each other and including switches having different short-circuit tolerances from an overcurrent.

A primary object of the present disclosure is to provide a driving apparatus of a switch capable of appropriately protecting a switch with a minimum short-circuit margin among a plurality of switches connected in parallel with each other from an overcurrent.

Disclosed is a switch driving device for performing drive control of a plurality of switches connected in parallel,

a plurality of the above switches include switches having different short circuit tolerances,

the method comprises the following steps: a determination unit that determines whether an overcurrent flows through at least one of the plurality of switches; and

an overcurrent protection unit configured to switch the plurality of switches to an off state when the determination unit determines that an overcurrent flows,

the overcurrent protection unit switches the minimum-tolerance switch, which is the switch with the smallest short-circuit tolerance among the plurality of switches, to the off state first.

In the present disclosure, since the minimum-margin switch among the plurality of switches is first switched to the off state, the time during which the overcurrent flows in the minimum-margin switch can be shortened. Thus, the energy generated in the minimum-margin switch can be reduced from the time when it is determined that the overcurrent has flowed until the minimum-margin switch is switched to the off state, and the energy can be made to be equal to or less than the short-circuit margin of the minimum-margin switch. As a result, the minimum-margin switch can be appropriately protected from the overcurrent.

Drawings

The above objects, other objects, features and advantages of the present disclosure will become more apparent with reference to the accompanying drawings and the following detailed description. The drawings are as follows.

Fig. 1 is an overall configuration diagram of a control system according to a first embodiment.

Fig. 2 is a diagram showing current-voltage characteristics of the first switch and the second switch.

Fig. 3 is a diagram showing a drive circuit and its peripheral structure.

Fig. 4 is a flowchart showing a processing procedure of cutting off the circuit.

Fig. 5 is a timing chart showing an example of the overcurrent protection operation.

Fig. 6 is a timing chart showing an example of the overcurrent protection operation.

Fig. 7 is a timing chart showing an example of the overcurrent protection operation in comparative example 1.

Fig. 8 is a timing chart showing an example of the overcurrent protection operation in comparative example 2.

Fig. 9 is a flowchart showing the processing procedure of the disconnection circuit according to the second embodiment.

Fig. 10 is a flowchart showing the processing procedure of the disconnection circuit according to the third embodiment.

Detailed Description

< first embodiment >

Hereinafter, a first embodiment embodying the driving device of the present disclosure will be described with reference to the drawings.

As shown in fig. 1, the control system includes a dc power supply 10, an inverter 20, a rotating electric machine 30, and a control device 40. The rotating electrical machine 30 is, for example, an in-vehicle main unit. The rotating electric machine 30 is electrically connected to the dc power supply 10 via the inverter 20. In the present embodiment, a three-phase structure is used as the rotating electric machine 30. As the rotating electric machine 30, for example, a permanent magnet synchronous rotating electric machine can be used. The dc power supply 10 is a battery having a terminal voltage of 100V or more, for example. The dc power supply 10 is, for example, a secondary battery such as a lithium ion battery or a nickel hydrogen battery. Further, the capacitor 11 is connected in parallel with the dc power supply 10.

Inverter 20 includes an upper arm switch unit 20H and a lower arm switch unit 20L corresponding to each other. In each phase, upper arm switch 20H and lower arm switch 20L are connected in series. In each phase, a first end of a winding 31 of the rotating electric machine 30 is connected to a connection point of the upper arm switch portion 20H and the lower arm switch portion 20L. The second ends of the windings 31 of the respective phases are connected at a neutral point.

Each of the switch sections 20H and 20L includes a parallel connection body of a first switch SW1 and a second switch SW 2. In each phase, the high-potential-side terminal of each of the first switch SW1 and the second switch SW2 of the upper arm switch unit 20H is connected to the positive electrode side of the dc power supply 10. In each phase, the negative side of the dc power supply 10 is connected to the low-potential-side terminal of each of the first switch SW1 and the second switch SW2 of the lower arm switch unit 20L. In each phase, the low-potential-side terminal of each of the first switch SW1 and the second switch SW2 of the upper arm switch unit 20H is connected to the high-potential-side terminal of each of the first switch SW1 and the second switch SW2 of the lower arm switch unit 20L.

In the present embodiment, the first switch SW1 is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as a SiC device. Therefore, in the first switch SW1, the low-potential-side terminal is a source, and the high-potential-side terminal is a drain. The second switch SW2 is an IGBT (Insulated Gate Bipolar Transistor) as a Si device. Therefore, in the second switch SW2, the low-potential-side terminal is an emitter and the high-potential-side terminal is a collector. A freewheeling diode is connected in reverse parallel to the second switch SW2, and a body diode is formed in the first switch SW 1.

The reason why the switching units 20H and 20L are formed by parallel connection bodies of IGBTs and MOSFETs is as follows: the loss in the small current region is reduced by causing a large amount of current to flow through the MOSFET having a low on-resistance in the small current region. The reduction of the loss will be described below with reference to fig. 2. Fig. 2 is a diagram showing a relationship between a current flowing through the switch and a voltage Von between a high-potential-side terminal and a low-potential-side terminal of the switch. In detail, fig. 2 shows voltage-current characteristics of the drain-source voltage Vds and the drain current Id of the MOSFET, and voltage-current characteristics of the collector-emitter voltage Vce and the collector current Ic of the IGBT.

As shown in fig. 2, in a small current region where the current is smaller than the predetermined current I α, the drain-source voltage Vds corresponding to the drain current Id is lower than the collector-emitter voltage Vce corresponding to the collector current Ic. That is, in a small current region, the on resistance of the MOSFET is smaller than the on resistance of the IGBT. Therefore, in a small current region, a large amount of current flows through the MOSFETs and the MOSFETs in the IGBTs connected in parallel to each other. On the other hand, in a large current region where the current is larger than the predetermined current I α, the collector-emitter voltage Vce corresponding to the collector current Ic is lower than the drain-source voltage Vds corresponding to the drain current Id. That is, in the large current region, the on resistance of the IGBT is smaller than the on resistance of the MOSFET. Therefore, in the large current region, a large amount of current flows through the MOSFETs and the IGBTs connected in parallel to each other.

The short tolerance of the first switch SW1 is lower than the short tolerance of the second switch SW 2. Taking the first switch SW1 as an example, the short-circuit margin is the time from when the overcurrent starts flowing to the first switch SW1 until the first switch SW1 is broken, or the energy (specifically, the time-integrated value of the current × the voltage) generated in the first switch SW1 from when the overcurrent starts flowing to the first switch SW1 until the first switch SW1 is broken. In addition, the rated current of the drain current of the first switch SW1 is, for example, smaller than the rated current of the collector current of the second switch SW 2.

Returning to the description of fig. 1, the control device 40 drives the inverter 20 to control the control amount of the rotating electric machine 30 to its command value. The controlled variable is, for example, torque. The controller 40 outputs a drive signal Gc corresponding to each of the switches SW1 and SW2 to the drive circuit 50 provided separately for each of the switches 20H and 20L, and turns on and off each of the switches SW1 and SW2 for driving the inverter 20. For example, the control device 40 generates the drive signal Gc corresponding to each drive circuit 50 by PWM processing based on comparison of the magnitudes of three-phase command voltages whose phases are separated by an electrical angle of 120 ° with carrier signals such as triangular waves. The drive signal Gc is either an on command instructing on-drive of the switch or an off command instructing off-drive. In each phase, the drive signal on the upper arm side and the corresponding drive signal on the lower arm side are alternately turned on commands. Therefore, in each phase, the switch of the upper arm switch section 20H and the switch of the lower arm switch section 20L are alternately in the on state.

The control system includes a shut down circuit 60. The shutoff circuit 60 divides the drive signal Gc output from the control device 40 into a first drive signal G1 corresponding to the first switch SW1 and a second drive signal G2 corresponding to the second switch SW2, and outputs the divided signals to the drive circuit 50.

For example, the control device 40 and the cutoff circuit 60 are provided in a low-voltage system, and the drive circuit 50 is provided in a high-voltage system electrically insulated from the low-voltage system. In this case, the signal transmission between the disconnection circuit 60 and the drive circuit 50 may be performed using, for example, an optical insulating element (e.g., a photocoupler) or a magnetic insulating element (e.g., a magnetic coupler) that can electrically insulate the low-voltage system from the high-voltage system and transmit a signal.

Further, the functions provided by the control device 40, the drive circuit 50, and the shut-off circuit 60 may be provided by, for example, software stored in a physical memory device and a computer, hardware, or a combination thereof that executes the software.

Next, the drive circuit 50 and its peripheral structure will be described with reference to fig. 3.

The drive circuit 50 includes a first charging switch 70, a first constant voltage power supply 71, a first charging resistor 72, and a first balancing resistor 73. In this embodiment, a P-channel MOSFET can be used as the first charge switch 70. A first constant voltage power supply 71 is connected to the source of the first charging switch 70, and a first terminal of a first charging resistor 72 is connected to the drain of the first charging switch 70. A first terminal of a first balancing resistor 73 is connected to a second terminal of the first charging resistor 72. A gate of the first switch SW1 is connected to a second terminal of the first balancing resistor 73.

The drive circuit 50 includes a first discharge resistor 74, a first discharge switch 75, a first protection resistor 76, a first protection switch 77, and a first off hold switch 78. In this embodiment, N-channel MOSFETs are used as the first discharge switch 75, the first protection switch 77, and the first off hold switch 78.

A drain of a first discharge switch 75 is connected to a first end of the first balancing resistor 73 via a first discharge resistor 74. A source of the first switch SW1 is connected to a source of the first discharge switch 75. A first terminal of the first balance resistor 73 is connected to a drain of a first protection switch 77 via a first protection resistor 76. A source of the first protection switch 77 is connected to a source of a first switch SW 1.

The gate of the first switch SW1 is connected to the drain of the first off hold switch 78. A source of the first switch SW1 is connected to a source of the first off hold switch 78.

The drive circuit 50 includes a second charging switch 80, a second constant voltage power supply 81, a second charging resistor 82, and a second balancing resistor 83. In this embodiment, a P-channel MOSFET can be used as the second charge switch 80. A second constant voltage power supply 81 is connected to the source of the second charge switch 80, and a first end of a second charge resistor 82 is connected to the drain of the second charge switch 80. A first end of a second balancing resistor 83 is connected to a second end of the second charging resistor 82. A second terminal of the second balancing resistor 83 is connected to a gate of a second switch SW 2. In the present embodiment, the output voltage of the second constant voltage power supply 81 is set to be lower than the output voltage of the first constant voltage power supply 71. However, the above setting is not essential.

The drive circuit 50 includes a second discharge resistor 84, a second discharge switch 85, a second protection resistor 86 serving as a soft-off resistor, a second protection switch 87, and a second off hold switch 88. In this embodiment, N-channel MOSFETs are used as the second discharge switch 85, the second protection switch 87, and the second off hold switch 88.

An emitter of the second switch SW2 is connected to a first end of the second balancing resistor 83 via the second discharge resistor 84 and the second discharge switch 85. An emitter of the second switch SW2 is connected to a first end of the second balance resistor 83 via a second protection resistor 86 and a second protection switch 87. The emitter of the second switch SW2 is connected to the gate of the second switch SW2 via the second off hold switch 88.

The first switch SW1 includes a first sense terminal St 1. The first sense terminal St1 outputs a weak current correlated with the drain current of the first switch SW 1. A first end of the first sense resistor 79 of the drive circuit 50 is connected to the first sense terminal St1, and a source of the first switch SW1 is connected to a second end of the first sense resistor 79. According to this structure, the voltage of the first sense resistor 79 is lowered by a weak current flowing through the first sense terminal St 1. Therefore, the voltage drop amount of the first sensing resistor 79 can be used as a correlation value of the drain current. The potential difference of the first sense resistor 79 is input to the drive control unit 90 of the drive circuit 50 as the first sense voltage Vse 1. In this embodiment, the first sense voltage Vse1 when the potential at the first end of the two ends of the first sense resistor 79 is higher than that at the second end is defined as positive.

The second switch SW2 includes a second sense terminal St 2. The second sense terminal St2 outputs a weak current correlated with the collector current of the second switch SW 2. A first end of a second sense resistor 89 of the drive circuit 50 is connected to the second sense terminal St2, and an emitter of a second switch SW2 is connected to a second end of the second sense resistor 89. The potential difference of the second sense resistor 89 is input to the drive control section 90 as a second sense voltage Vse 2. In this embodiment, the second sense voltage Vse2 when the potential at the first end of the two ends of the second sense resistor 89 is higher than that at the second end is defined as positive.

The drive control unit 90 drives the first switch SW1 and the second switch SW2 to be turned on and off based on the first drive signal G1 and the second drive signal G2 output from the cutoff circuit 60. Specifically, when determining that the first drive signal G1 has become the on command, the drive control unit 90 drives the first charge switch 70 on and drives the first discharge switch 75 off. Thus, the charging current flows from the first constant voltage power supply 71 to the gate of the first switch SW1, and the gate voltage of the first switch SW1 becomes equal to or higher than the first threshold voltage Vth 1. As a result, the first switch SW1 is switched from the off state to the on state.

When determining that the first drive signal G1 has become the off command, the drive control unit 90 drives the first charge switch 70 off and drives the first discharge switch 75 on. Accordingly, a discharge current flows from the gate to the source of the first switch SW1, and the gate voltage of the first switch SW1 is lower than the first threshold voltage Vth 1. As a result, the first switch SW1 is switched from the on state to the off state.

When it is determined that the second drive signal G2 has become the on command, the drive control unit 90 drives the second charge switch 80 on and drives the second discharge switch 85 off. Thus, the charging current flows from the second constant voltage power supply 81 to the gate of the second switch SW2, and the gate voltage of the second switch SW2 becomes equal to or higher than the second threshold voltage Vth 2. As a result, the second switch SW2 is switched from the off state to the on state.

When determining that the second drive signal G2 has become the off command, the drive control unit 90 drives the second charge switch 80 off and drives the second discharge switch 85 on. Accordingly, a discharge current flows from the gate to the emitter of the second switch SW2, and the gate voltage of the second switch SW2 is lower than the second threshold voltage Vth 2. As a result, the second switch SW2 is switched from the on state to the off state.

The drive control section 90 performs the off hold process. In detail, the drive control unit 90 has a function of detecting the gate voltages of the first switch SW1 and the second switch SW 2. The drive control unit 90 performs the off hold processing as follows: the first off hold switch 78 is driven based on the first drive signal G1 output from the cut-off circuit 60 and the detected gate voltage of the first switch SW1, and the second off hold switch 88 is driven based on the second drive signal G2 output from the cut-off circuit 60 and the detected gate voltage of the second switch SW 2.

In detail, when it is determined that the first drive signal G1 is the off command and the gate voltage of the first switch SW1 is the first predetermined voltage V α 1 or less, the drive control section 90 drives the first off hold switch 78 on and otherwise drives the first off hold switch 78 off. Here, the first predetermined voltage V α 1 is set to a voltage equal to or lower than the first threshold voltage Vth 1. When it is determined that the second drive signal G2 is the off command and the gate voltage of the second switch SW2 is the second predetermined voltage V α 2 or less, the drive control section 90 drives the second off hold switch 88 on and drives the second off hold switch 88 off otherwise. Here, the second predetermined voltage V α 2 is set to a voltage equal to or lower than the second threshold voltage Vth 2.

The drive control unit 90 includes a first short circuit determination unit 91 and a second short circuit determination unit 92 (corresponding to "determination unit"). The first short-circuit determining unit 91 and the second short-circuit determining unit 92 are provided to determine whether or not an overcurrent (short-circuit current) flows through the first switch SW1 and the second switch SW 2. When it is determined that the input first sensing voltage Vse1 exceeds the first determination threshold Voc1, the first short determination unit 91 outputs a first failure signal F1 to the disconnection circuit 60, which notifies that an overcurrent flows through the first switch SW 1. After the first failure signal F1 starts to be output, the first short circuit determining unit 91 stops the output of the first failure signal F1 when determining that the first sense voltage Vse1 is equal to or less than the first release threshold Vjdg1, which is smaller than the first determination threshold Voc 1. The first release threshold Vjdg1 is set to a value slightly larger than 0 or to 0.

When it is determined that the input second sensing voltage Vse2 exceeds the second determination threshold Voc2, the second short circuit determination section 92 outputs a second fault signal F2 to the disconnection circuit 60, which notifies that an overcurrent flows through the second switch SW 2. After the second failure signal F2 starts to be output, if the second short-circuit determining unit 92 determines that the second sense voltage Vse2 is equal to or less than the second release threshold Vjdg2, the output of the second failure signal F2 is stopped. The second release threshold Vjdg2 is set to a value slightly larger than 0 or to 0. The overcurrent is generated by upper and lower arm short circuits, interphase short circuits, grounding, and the like.

Next, a process performed by the shutdown circuit 60 will be described with reference to fig. 4.

In step S10, it is determined whether at least one of the first fail signal F1 and the second fail signal F2 is input.

When a negative determination is made in step S10, it is determined that no overcurrent flows in both the first switch SW1 and the second switch SW2, and the process proceeds to step S11. In step S11, the drive signal Gc input from the control device 40 is output to the drive control unit 90 as the first drive signal G1 and the second drive signal G2. That is, when the drive signal Gc is an on command, the first drive signal G1 and the second drive signal G2 that are on commands are output, and when the drive signal Gc is an off command, the first drive signal G1 and the second drive signal G2 that are off commands are output.

When an affirmative determination is made in step S10, it is determined that an overcurrent flows through at least one of the first switch SW1 and the second switch SW2, and the process proceeds to step S12. In step S12, the first drive signal G1 output to the drive control unit 90 is set as an off command regardless of the input drive signal Gc. In this case, when the input first drive signal G1 is switched to the off command in a state where at least one of the first fail signal F1 and the second fail signal F2 is output, the drive control section 90 drives the first charge switch 70, the first discharge switch 75, and the first off hold switch 78 to be turned off, and drives the first protection switch 77 to be turned on.

Here, the resistance value of the first protection switch 77 is Rs1, the resistance value of the first balance resistor 73 is Rb1, the resistance value of the second protection switch 87 is Rs2, and the resistance value of the second balance resistor 83 is Rb 2. In the present embodiment, "Rs 1+ Rb1 < Rs2+ Rb 2" is set. With the above setting, the switching speed when the first switch SW1 is switched to the off state is higher than the switching speed when the second switch SW2 is switched to the off state in the processing of step S14 described later.

In addition, when the resistance value of the first discharge resistor 74 is Rd1 and the resistance value of the second discharge resistor 84 is Rd2, the resistance values are "Rd 1+ Rb1 > Rs1+ Rb 1", "Rd 2+ Rb2 > Rs1+ Rb 1", "Rs 2+ Rb2 > Rd2+ Rb 2", and "Rs 2+ Rb2 > Rd1+ Rb 1" in this embodiment.

In step S13, it is determined whether the switching of the first switch SW1 to the off state is completed. In the present embodiment, when it is determined that the first sense voltage Vse1 is equal to or less than the first release threshold Vjdg1 and the input of the first fail signal F1 is stopped, it is determined that the switching is completed.

When an affirmative determination is made in step S13, the process proceeds to step S14, and the second drive signal G2 output to the drive control section 90 is set as the off command regardless of the input drive signal Gc. Thereby, the drive control unit 90 drives the second charge switch 80, the second discharge switch 85, and the second off hold switch 88 off, and drives the second protection switch 87 on. Thereby, the second switch SW2 is switched to the off state at a switching speed lower than the switching speed at which the first switch SW1 is switched to the off state. In the present embodiment, the disconnection circuit 60 constitutes an overcurrent protection unit.

The overcurrent protection operation performed by the disconnection circuit 60 when the upper and lower arms are short-circuited will be described with reference to fig. 5 and 6. In the following description, an overcurrent protection operation performed by the arm cutoff circuit 60 will be described with one of the upper arm switch unit 20H and the lower arm switch unit 20L being a counter arm and the other being a self arm.

A case where the first switch SW1 and the second switch SW2 of the own arm are driven to be turned on in a state where at least one of the first switch SW1 and the second switch SW2 of the opposite arm has a short-circuit fault will be described with reference to fig. 5. Fig. 5 (a) and (b) show changes in the first drive signal G1 and the second drive signal G2 outputted from the cutoff circuit 60, fig. 5 (c) shows changes in the gate voltage Vgs (gate-source voltage) of the first switch SW1, and fig. 5 (d) shows changes in the gate voltage Vge (gate-emitter voltage) of the second switch SW 2. Fig. 5 (e) and (f) show changes in the first sense voltage Vse1 and the second sense voltage Vse2, fig. 5 (g) shows changes in the loss (Id × Vds) generated in the first switch SW1, and fig. 5 (h) shows changes in the loss (Ic × Vce) generated in the second switch SW 2.

At time t1, the first drive signal G1 and the second drive signal G2 output from the cutoff circuit 60 to the drive control section 90 are switched to on commands. Thus, at time t2, the gate voltage Vgs of the first switch SW1 and the gate voltage Vge of the second switch SW2 start to rise.

Thereafter, at time t3, the first sensing voltage Vse1 exceeds the first determination threshold Voc 1. Therefore, the first failure signal F1 is output from the first short circuit determination section 91 to the cut-off circuit 60, and the first drive signal G1 output from the cut-off circuit 60 to the drive control section 90 is switched to the off command. As a result, at time t4, the gate voltage Vgs of the first switch SW1 starts to fall.

Thereafter, at time t5, the first sensing voltage Vse1 reaches below the first release threshold Vjdg 1. Therefore, the output of the first failure signal F1 from the first short circuit determination section 91 to the disconnection circuit 60 is stopped, and the second drive signal G2 output from the disconnection circuit 60 to the drive control section 90 is switched to the off command. As a result, at time t6, the gate voltage Vge of the second switch SW2 starts to fall.

Here, the falling speed Δ dVmos of the first sensing voltage Vse1 when the first switch SW1 is switched to the off state is faster than the falling speed Δ dVigbt of the second sensing voltage Vse2 when the second switch SW2 is switched to the off state. That is, the switching speed when the first switch SW1 is switched to the off state is faster than the switching speed when the second switch SW2 is switched to the off state. As a result, the time during which the overcurrent flows through the first switch SW1 can be shortened, and the time integral value (energy) of the loss generated in the first switch SW1 can be made equal to or less than the short-circuit margin of the first switch SW 1.

Although fig. 5 shows an example in which the first switch SW1 is first switched to the off state when it is determined that an overcurrent flows through the first switch SW1, the first switch SW1 is also first switched to the off state when it is determined that an overcurrent flows through the second switch SW 2.

Next, a case where a short-circuit failure occurs in at least one of the first switch SW1 and the second switch SW2 of the opposite arm in a state where the first switch SW1 and the second switch SW2 driving the own arm are turned on will be described with reference to fig. 6. Fig. 6 (a) to 6 (h) correspond to fig. 5 (a) to 5 (h) described above.

At time t1, the first drive signal G1 and the second drive signal G2 output from the cutoff circuit 60 to the drive control unit 90 are switched to on commands. Thereby, the gate voltage Vgs of the first switch SW1 and the gate voltage Vge of the second switch SW2 start to rise.

Then, at time t2, a short-circuit failure of the switch of the opposite arm occurs. Thus, short-circuit current flows through the first switch SW1 and the second switch SW2 of the arm itself.

Thereafter, at time t3, the first sensing voltage Vse1 exceeds the first determination threshold Voc 1. Therefore, the first failure signal F1 is output from the first short circuit determination section 91 to the cut-off circuit 60, and the first drive signal G1 output from the cut-off circuit 60 to the drive control section 90 is switched to the off command. As a result, at time t4, the gate voltage Vgs of the first switch SW1 starts to fall.

Thereafter, at time t5, the first sensing voltage Vse1 reaches below the first release threshold Vjdg 1. Therefore, the output of the first failure signal F1 from the first short circuit determination section 91 to the disconnection circuit 60 is stopped, and the second drive signal G2 output from the disconnection circuit 60 to the drive control section 90 is switched to the off command. As a result, the gate voltage Vge of the second switch SW2 starts to fall.

In the present embodiment described above, in the case of comparative examples 1 and 2, the first switch SW1 cannot be properly protected from an overcurrent.

First, comparative example 1 will be described with reference to fig. 7. Fig. 7 shows a case where the first switch SW1 and the second switch SW2 of the own arm are driven to be turned on in a state where at least one of the first switch SW1 and the second switch SW2 of the opposite arm has a short-circuit failure. Fig. 7 (a) to 7 (h) correspond to fig. 5 (a) to 5 (h) described above.

At time t1, the first drive signal G1 and the second drive signal G2 output from the cutoff circuit 60 to the drive control section 90 are switched to on commands. Thus, at time t2, the gate voltage Vgs of the first switch SW1 and the gate voltage Vge of the second switch SW2 start to rise.

In comparative example 1, when at least one of the first fail signal F1 and the second fail signal F2 is input to the disconnection circuit 60, the disconnection circuit 60 simultaneously switches the first drive signal G1 and the second drive signal G2 to the off command. In detail, at time t3, the first sensing voltage Vse1 exceeds the first determination threshold Voc 1. Therefore, the first failure signal F1 is output from the first short circuit determination unit 91 to the disconnection circuit 60, and the first drive signal G1 and the second drive signal G2 output from the disconnection circuit 60 to the drive control unit 90 are switched to the off command. As a result, at time t4, the gate voltage Vgs of the first switch SW1 and the gate voltage Vge of the second switch SW2 start to fall.

In comparative example 1, the switching speed when the first switch SW1 is switched to the off state is the same as the switching speed when the second switch SW2 is switched to the off state. Therefore, the time for the overcurrent to flow through the first switch SW1 cannot be shortened, and the energy generated in the first switch SW1 may exceed the short-circuit tolerance of the first switch SW 1.

Next, comparative example 2 will be described with reference to fig. 8. Fig. 8 shows a case where the first switch SW1 and the second switch SW2 of the own arm are driven to be turned on in a state where at least one of the first switch SW1 and the second switch SW2 of the opposite arm has a short-circuit failure. Fig. 8 (a) to 8 (f) correspond to fig. 5 (a) to 5 (f), and fig. 8 (g) shows a transition of the phase current flowing through the winding 31. Further, the times t1 to t4 of fig. 8 correspond to the previous times t1 to t4 of fig. 7.

In comparative example 2, when at least one of the first fail signal F1 and the second fail signal F2 is input to the disconnection circuit 60, the disconnection circuit 60 simultaneously switches the first drive signal G1 and the second drive signal G2 to the off command, as in comparative example 1. In comparative example 2, the switching speeds at which the second switch SW2 is switched to the off state are set to two types. In fig. 8 (d) and (g), the case where the switching speed is low is indicated by a broken line, and the case where the switching speed is high is indicated by a solid line.

When the first drive signal G1 and the second drive signal G2 are switched to the off command at the same time, if the switching speed of the second switch SW2 is increased, the phase current abruptly decreases as shown in fig. 8 (G). As a result, the surge voltage generated by the off-state switching increases, and the drain-source voltage of the first switch SW1 may exceed the allowable upper limit value (withstand voltage).

According to the present embodiment described in detail above, the following effects can be obtained.

When it is determined that an overcurrent flows through at least one of the first switch SW1 and the second switch SW2, the first switch SW1 having a small short-circuit margin among the first switch SW1 and the second switch SW2 is switched to the off state before the second switch SW 2. Accordingly, the time for the overcurrent to flow through the first switch SW1 can be shortened, and the energy generated in the first switch SW1 can be made to be equal to or less than the short-circuit tolerance of the first switch SW 1. As a result, the first switch SW1 can be appropriately protected from the overcurrent.

The first switch SW1, which is first switched to the off state, of the first switch SW1 and the second switch SW2 does not generate a large surge voltage associated with the switching to the off state. Therefore, the first switch SW1 that will not switch to the off state last can be made to have a higher switching speed than the second switch SW2 that will switch to the off state last. In view of this, the switching speed of the first switch SW1 is made faster than the switching speed of the second switch SW 2. Thus, when the switch is switched to the off state, the time for the first switch SW1 to flow the overcurrent can be shortened, and the energy generated in the first switch SW1 can be further reduced.

When an overcurrent flows, if the second switch SW2 is switched to the off state while the current flows through the first switch SW1, a surge voltage is generated in the first switch SW1 accompanying the switching to the off state. Therefore, after the first switch SW1 is switched to the off state, the second switch SW2 is switched to the off state. This can suppress the occurrence of surge voltage in response to the second switch SW2 being switched to the off state.

When it is determined that an overcurrent flows through either one of the first switch SW1 and the second switch SW2, the first switch SW1 is first switched to the off state. Accordingly, even when it is determined that an overcurrent flows through the second switch SW2, the overcurrent protection operation can be promptly shifted to the overcurrent protection operation of the first switch SW 1.

< second embodiment >

Hereinafter, a second embodiment will be described focusing on differences from the first embodiment with reference to the drawings.

Fig. 9 shows a sequence of processing executed by the shutdown circuit 60. In fig. 9, for convenience, the same processes as those shown in fig. 4 are denoted by the same reference numerals.

In the processing shown in fig. 9, the processing of step S13 is not provided. That is, the process of step S14 is performed before the switching of the first switch SW1 to the off state is completed. In this case as well, effects similar to those of the first embodiment can be obtained.

< third embodiment >

Hereinafter, a third embodiment will be described focusing on differences from the first embodiment with reference to the drawings.

Fig. 10 shows a sequence of processing executed by the shutdown circuit 60. In fig. 10, for convenience, the same processes as those shown in fig. 4 are denoted by the same reference numerals. In the present embodiment, the first protection resistor 76 and the first protection switch 77 are not included in the configuration of fig. 3.

In the case where an affirmative determination is made in step S10, the flow proceeds to step S15. In step S15, the first drive signal G1 output to the drive control unit 90 is set as an off command regardless of the input drive signal Gc. In this case, when the input first drive signal G1 is switched to the off command in a state where at least one of the first fail signal F1 and the second fail signal F2 is output, the drive control section 90 drives the first charge switch 70, the first discharge switch 75, and the first off hold switch 78 off, and drives the first off hold switch 78 on.

In this way, in the present embodiment, the first switch SW1 is switched to the off state using the first off hold switch 78. According to the above configuration, the switching speed when the first off hold switch 78 is switched to the off state can be further increased, and the energy generated in the first switch SW1 can be further reduced.

Further, according to the present embodiment, the first off hold switch 78 can be used as a switch used in the overcurrent protection operation, and it is not necessary to include the first protection resistor 76 and the first protection switch 77 in the drive circuit 50, so that the number of components of the drive circuit 50 can be reduced.

< other embodiments >

The above embodiments may be modified as follows.

The number of switches of the switch unit constituting each arm of each phase may be three or more. For example, when each switch unit includes three switches, the first switch, the second switch, and the third switch are arranged in order of increasing short-circuit tolerance. When it is determined that an overcurrent flows through at least one of the first to third switches, the first switch of the first to third switches may be first switched to the off state, the second switch may be switched to the off state, and the third switch may be switched to the off state.

The switches of the switch units constituting the arms of each phase are not limited to the same type of switch. For example, even if the first switch and the second switch are both MOSFETs formed of SiC devices, the short-circuit capacity may be different depending on the chip size. Even in the case as described above, application of the present disclosure is effective.

The control system may not include the cutoff circuit 60, and the drive control unit 90 may function as the cutoff circuit 60.

The power conversion circuit is not limited to the inverter, and may include upper and lower arm switches, for example, a full bridge circuit.

The control section and the method of the control section described in the present disclosure may also be realized by a special purpose computer provided by constituting a processor programmed to execute one to a plurality of functions embodied by a computer program and a memory. Alternatively, the control unit and the method of the control unit described in the present disclosure may be realized by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and the method of the control unit described in the present disclosure may be implemented by one or more special purpose computers including a combination of a processor and a memory programmed to execute one or more functions, and a processor including one or more hardware logic circuits. Further, the computer program may also be stored on a non-transitory tangible storage medium readable by a computer as instructions for execution by the computer.

Although the present disclosure has been described based on the embodiments, it should be understood that the present disclosure is not limited to the embodiments and configurations described above. The present disclosure also includes various modifications and variations within an equivalent range. In addition, various combinations and modes, including only one element, one or more other combinations and modes, also belong to the scope and the idea of the present disclosure.