阅读说明：本技术 电力变换装置 (Power conversion device ) 是由 但马秀伸 于 2019-11-06 设计创作，主要内容包括：不间断电源装置的栅极驱动电路(36)响应于第1及第2PWM信号(Au1、Bu1)而生成第1及第2栅极驱动信号(VG1、VG2),使第1及第2IGBT(Q1、Q2)交替地接通。该栅极驱动电路在第1IGBT(Q1)被接通的情况下,响应于第2PWM信号而将第1栅极驱动信号置于“L”电平,与第1IGBT的端子间电压(V1)超过了阈值电压(VTH1)这一情况相对应地将第2栅极驱动信号置于“H”电平。(A gate drive circuit (36) of the uninterruptible power supply device generates a 1 st gate drive signal (VG1, VG2) and a 2 nd gate drive signal (VG 2) in response to a 1 st PWM signal (Au1, Bu1) and alternately turns on a 1 st IGBT (Q1, Q2). The gate drive circuit sets the 1 st gate drive signal to an 'L' level in response to the 2 nd PWM signal when the 1 st IGBT (Q1) is turned on, and sets the 2 nd gate drive signal to an 'H' level corresponding to a case where an inter-terminal voltage (V1) of the 1 st IGBT exceeds a threshold voltage (VTH 1).)

1. A power conversion device is characterized in that,

the disclosed device is provided with:

a 1 st DC terminal for receiving a 1 st DC voltage;

an AC terminal for receiving an AC voltage;

a 2 nd dc terminal for receiving a 2 nd dc voltage different from the 1 st dc voltage;

a 1 st switching element connected between the 1 st dc terminal and the ac terminal;

a 2 nd switching element connected between the ac terminal and the 2 nd dc terminal;

a 1 st control circuit for alternately outputting 1 st and 2 nd control signals; and

a 1 st drive circuit for generating a 1 st and a 2 nd drive signals in response to an output signal of the 1 st control circuit, and alternately turning on the 1 st and the 2 nd switching elements;

if the 1 st and 2 nd driving signals are set to an active level, the 1 st and 2 nd switching elements are turned on, respectively;

if the 1 st and 2 nd driving signals are set to be in an inactive level, the 1 st and 2 nd switching elements are respectively turned off;

the 1 st drive circuit sets the 1 st drive signal to an inactive level in response to the 2 nd control signal when the 1 st switching element is turned on, and sets the 2 nd drive signal to an active level in response to a case where an inter-terminal voltage of the 1 st switching element exceeds a 1 st threshold voltage;

when the 2 nd switching element is turned on, the 1 st drive circuit sets the 2 nd drive signal to an inactive level in response to the 1 st control signal, and sets the 1 st drive signal to an active level in response to a case where the inter-terminal voltage of the 2 nd switching element exceeds a 2 nd threshold voltage.

2. The power conversion apparatus according to claim 1,

the 1 st and 2 nd switching elements are 1 st and 2 nd insulated gate bipolar transistors, respectively;

the power conversion device further includes 1 st and 2 nd diodes connected in inverse parallel to the 1 st and 2 nd insulated gate bipolar transistors, respectively.

3. The power conversion apparatus according to claim 1,

the 1 st control circuit alternately outputs the 1 st and 2 nd control signals in a 1 st period and continuously outputs the 2 nd control signal in a 2 nd period;

the 1 st drive circuit alternately turns on the 1 st and 2 nd switching elements in the 1 st period, and maintains the 1 st and 2 nd switching elements in an off state and an on state, respectively, in the 2 nd period;

the power conversion device further includes:

a 3 rd DC terminal for receiving a 3 rd DC voltage different from the 2 nd DC voltage;

a 3 rd switching element connected between the ac terminal and the 3 rd dc terminal;

a 4 th switching element connected between one terminal of the 2 nd switching element and the ac terminal, or between the other terminal of the 2 nd switching element and the 2 nd dc terminal;

a 2 nd control circuit for alternately outputting a 3 rd control signal and a 4 th control signal in the 2 nd period and continuously outputting the 4 th control signal in the 1 st period; and

a 2 nd drive circuit for generating a 3 rd and a 4 th drive signals in response to an output signal of the 2 nd control circuit, alternately turning on the 3 rd and the 4 th switching elements in the 2 nd period, and maintaining the 3 rd and the 4 th switching elements in an off state and an on state, respectively, in the 1 st period;

the 2 nd dc voltage is a voltage intermediate between the 1 st and 3 rd dc voltages;

if the 3 rd and 4 th driving signals are set to an active level, the 3 rd and 4 th switching elements are turned on, respectively;

if the 3 rd and 4 th driving signals are set to the inactive level, the 3 rd and 4 th switching elements are turned off, respectively;

when the 3 rd switching element is turned on, the 2 nd drive circuit sets the 3 rd drive signal to an inactive level in response to the 4 th control signal, and sets the 4 th drive signal to an active level in response to a case where the inter-terminal voltage of the 3 rd switching element exceeds a 3 rd threshold voltage;

when the 4 th switching element is turned on, the 2 nd drive circuit sets the 4 th drive signal to an inactive level in response to the 3 rd control signal, and sets the 3 rd drive signal to an active level in response to a case where the inter-terminal voltage of the 4 th switching element exceeds a 4 th threshold voltage.

4. The power conversion apparatus according to claim 3,

the 1 st, 2 nd, 3 rd and 4 th switching elements are 1 st, 2 nd, 3 rd and 4 th insulated gate bipolar transistors, respectively;

the power conversion device further includes 1 st, 2 nd, 3 rd and 4 th diodes connected in inverse parallel to the 1 st, 2 nd, 3 rd and 4 th insulated gate bipolar transistors, respectively.

5. The power conversion apparatus according to claim 1,

the 1 st control circuit alternately outputs the 1 st and 2 nd control signals in a 1 st period and continuously outputs the 2 nd control signal in a 2 nd period;

the 1 st drive circuit alternately turns on the 1 st and 2 nd switching elements in the 1 st period, and maintains the 1 st and 2 nd switching elements in an off state and an on state, respectively, in the 2 nd period;

the power conversion device further includes:

a 3 rd DC terminal for receiving a 3 rd DC voltage different from the 2 nd DC voltage;

a 3 rd switching element connected between one terminal of the 2 nd switching element and the 3 rd dc terminal;

a 1 st diode connected between one terminal of the 2 nd switching element and the 2 nd dc terminal;

a 4 th switching element connected between one terminal of the 1 st switching element and the ac terminal;

a 2 nd diode connected between the 2 nd dc terminal and one terminal of the 1 st switching element;

a 2 nd control circuit for alternately outputting a 3 rd control signal and a 4 th control signal in the 2 nd period and continuously outputting the 4 th control signal in the 1 st period; and

a 2 nd drive circuit for generating a 3 rd and a 4 th drive signals in response to an output signal of the 2 nd control circuit, alternately turning on the 3 rd and the 4 th switching elements in the 2 nd period, and maintaining the 3 rd and the 4 th switching elements in an off state and an on state, respectively, in the 1 st period;

the 2 nd dc voltage is a voltage intermediate between the 1 st and 3 rd dc voltages;

if the 3 rd and 4 th driving signals are set to an active level, the 3 rd and 4 th switching elements are turned on, respectively;

if the 3 rd and 4 th driving signals are set to the inactive level, the 3 rd and 4 th switching elements are turned off, respectively;

when the 3 rd switching element is turned on, the 2 nd drive circuit sets the 3 rd drive signal to an inactive level in response to the 4 th control signal, and sets the 4 th drive signal to an active level in response to a case where the inter-terminal voltage of the 3 rd switching element exceeds a 3 rd threshold voltage;

when the 4 th switching element is turned on, the 2 nd drive circuit sets the 4 th drive signal to an inactive level in response to the 3 rd control signal, and sets the 3 rd drive signal to an active level in response to a case where the inter-terminal voltage of the 4 th switching element exceeds a 4 th threshold voltage.

6. The power conversion apparatus according to claim 5,

the 1 st, 2 nd, 3 rd and 4 th switching elements are 1 st, 2 nd, 3 rd and 4 th insulated gate bipolar transistors, respectively;

the power conversion device further includes 3 rd, 4 th, 5 th, and 6 th diodes connected in inverse parallel to the 1 st, 2 nd, 3 rd, and 4 th insulated gate bipolar transistors, respectively.

7. The power conversion apparatus according to claim 1,

the 1 st drive circuit described above includes:

1 st and 2 nd voltage detectors for detecting voltages between terminals of the 1 st and 2 nd switching elements, respectively;

a 1 st comparator that outputs a 1 st signal in response to the 1 st voltage detector detecting that the voltage across the terminals of the 1 st switching element exceeds the 1 st threshold voltage;

a 2 nd comparator for outputting a 2 nd signal in response to the 2 nd voltage detector detecting that the voltage between the terminals of the 2 nd switching element exceeds the 2 nd threshold voltage;

a 1 st driver configured to set the 1 st drive signal to an inactive level when the 2 nd control signal is output from the 1 st control circuit, and to set the 1 st drive signal to an active level when the 2 nd signal is output from the 2 nd comparator when the 1 st control signal is output from the 1 st control circuit; and

and a 2 nd driver configured to set the 2 nd driving signal to an inactive level when the 1 st control signal is output from the 1 st control circuit, and set the 2 nd driving signal to an active level when the 1 st signal is output from the 1 st comparator when the 2 nd control signal is output from the 1 st control circuit.

8. The power conversion apparatus according to claim 1,

the 1 st and 2 nd switching elements constitute a flyback converter for converting dc power into ac power.

9. The power conversion apparatus according to claim 8,

a forward converter for converting AC power supplied from a commercial AC power supply into DC power;

supplying the dc power generated by the forward converter to the reverse converter and storing the dc power in a power storage device in a normal state in which the ac power is supplied from the commercial ac power supply;

the dc power of the power storage device is supplied to the inverter in the event of a power failure in which the supply of ac power from the commercial ac power supply is stopped.

10. The power conversion apparatus according to claim 1,

the 1 st and 2 nd switching elements constitute a forward converter that converts ac power to dc power.

11. The power conversion apparatus according to claim 10,

a reverse converter for converting DC power into AC power;

supplying the dc power generated by the forward converter to the reverse converter and storing the dc power in a power storage device in a normal state in which the ac power is supplied from the commercial ac power supply;

the dc power of the power storage device is supplied to the inverter in the event of a power failure in which the supply of ac power from the commercial ac power supply is stopped.

Technical Field

The present invention relates to a power conversion device, and particularly to a power conversion device including 1 st and 2 nd switching elements that are alternately turned on.

Background

For example, international publication No. 2012/046521 (patent document 1) discloses a power conversion device including 1 st and 2 nd switching elements and a control device that generates 1 st and 2 nd control signals and turns on the 1 st and 2 nd switching elements alternately. When the 1 st switching element is turned on, the control device sets the 1 st control signal to an inactive level to turn off the 1 st switching element, and sets the 2 nd control signal to an active level to turn on the 2 nd switching element after a certain dead time (dead time) has elapsed.

Documents of the prior art

Patent document

Patent document 1: international publication No. 2012/046521 specification

Disclosure of Invention

Problems to be solved by the invention

In patent document 1, the dead time is fixed to a certain value. However, the off delay time from setting the 1 st control signal to the inactive level until the 1 st switching element actually becomes the off state becomes shorter in inverse proportion to the current (interrupting current) flowing through the 1 st switching element when the 1 st control signal is the active level.

Therefore, the dead time is shorter than the actual off delay time depending on the value of the off current, and there is a possibility that the 2 nd switching element is turned on although the 1 st switching element is not yet turned off, and an overcurrent flows through the 1 st and 2 nd switching elements.

As a countermeasure, a method may be considered in which the dead time is set to a sufficiently longer time than the off delay time, but if the dead time is made longer, the on time of the 2 nd switching element becomes shorter, and the efficiency decreases.

Therefore, a main object of the present invention is to provide a power conversion device capable of preventing an overcurrent from flowing and improving efficiency.

Means for solving the problems

The power conversion device according to the present invention includes: a 1 st DC terminal for receiving a 1 st DC voltage; an AC terminal for receiving an AC voltage; a 2 nd DC terminal for receiving a 2 nd DC voltage different from the 1 st DC voltage; a 1 st switching element connected between a 1 st DC terminal and an AC terminal; a 2 nd switching element connected between the ac terminal and the 2 nd dc terminal; a 1 st control circuit for alternately outputting 1 st and 2 nd control signals; and a 1 st drive circuit for generating a 1 st drive signal and a 2 nd drive signal in response to an output signal of the 1 st control circuit, and alternately turning on the 1 st switching element and the 2 nd switching element. If the 1 st and 2 nd driving signals are set to the activated level, the 1 st and 2 nd switching elements are respectively switched on; if the 1 st and 2 nd driving signals are placed at the inactive level, the 1 st and 2 nd switching elements are turned off, respectively. The 1 st drive circuit sets the 1 st drive signal to an inactive level in response to the 2 nd control signal when the 1 st switching element is turned on, and sets the 2 nd drive signal to an active level corresponding to a case where the voltage between the terminals of the 1 st switching element exceeds a 1 st threshold voltage; in a case where the 2 nd switching element is turned on, the 2 nd driving signal is placed at an inactive level in response to the 1 st control signal, and the 1 st driving signal is placed at an active level corresponding to a case where the inter-terminal voltage of the 2 nd switching element exceeds the 2 nd threshold voltage.

Effects of the invention

The power conversion device according to the present invention includes: a 1 st control circuit for alternately outputting 1 st and 2 nd control signals; and a 1 st drive circuit for generating a 1 st drive signal and a 2 nd drive signal in response to an output signal of the 1 st control circuit, and alternately turning on the 1 st switching element and the 2 nd switching element. The 1 st drive circuit sets the 1 st drive signal to an inactive level in response to the 2 nd control signal when the 1 st switching element is turned on, and sets the 2 nd drive signal to an active level corresponding to the 1 st switching element having an inter-terminal voltage exceeding a 1 st threshold voltage. Therefore, since the 2 nd switching element is turned on after the 1 st switching element is actually turned off, it is possible to prevent an overcurrent from flowing and improve efficiency.

Drawings

Fig. 1 is a circuit block diagram showing a configuration of an uninterruptible power supply device according to embodiment 1 of the present invention.

Fig. 2 is a circuit block diagram showing the configuration of the inverter shown in fig. 1and its peripheral portion.

Fig. 3 is a circuit block diagram showing a configuration of an inverter control unit that controls the inverter shown in fig. 2.

Fig. 4 is a timing chart showing waveforms of the voltage command value, the triangular wave signal, and the PWM signal shown in fig. 3.

Fig. 5 is a circuit block diagram showing a configuration of the gate driver circuit shown in fig. 3.

Fig. 6 is a circuit diagram showing a configuration of the delay circuit shown in fig. 5.

Fig. 7 is a timing chart illustrating an operation of the gate driving circuit shown in fig. 5.

Fig. 8 is another timing chart illustrating an operation of the gate driver circuit shown in fig. 5.

Fig. 9 is a circuit block diagram showing the configuration of the inverter shown in fig. 1and its peripheral portion.

Fig. 10 is a circuit block diagram showing a configuration of an inverter control unit that controls the inverter shown in fig. 9.

Fig. 11 is a circuit block diagram showing a modification of embodiment 1.

Fig. 12 is a circuit block diagram showing a comparative example of embodiment 1.

Fig. 13 is a diagram for explaining a problem of the comparative example shown in fig. 12.

Fig. 14 is a circuit block diagram showing a configuration of an uninterruptible power supply device according to embodiment 2 of the present invention.

Fig. 15 is a circuit block diagram showing the configuration of the inverter shown in fig. 14 and its peripheral portion.

Fig. 16 is a circuit block diagram showing a configuration of an inverter control unit that controls the inverter shown in fig. 15.

Fig. 17 is a timing chart showing waveforms of the voltage command value, the triangular wave signal, and the PWM signal shown in fig. 16.

Fig. 18 is a circuit block diagram showing a modification of embodiment 2.

Fig. 19 is a circuit block diagram showing a main part of an uninterruptible power supply device according to embodiment 3 of the present invention.

Fig. 20 is a circuit block diagram showing a configuration of an inverter control unit that controls the inverter shown in fig. 19.

Detailed Description

[ embodiment 1]

Fig. 1 is a circuit block diagram showing a configuration of an uninterruptible power supply device 1 according to embodiment 1 of the present invention. The uninterruptible power supply 1 is a device that once converts three-phase ac power from the commercial ac power supply 21 into dc power, converts the dc power into three-phase ac power, and supplies the three-phase ac power to the load 24. Fig. 1 shows only a circuit corresponding to one phase (for example, U phase) of three phases (U phase, V phase, and W phase) for simplicity of the drawing and the description.

In fig. 1, the uninterruptible power supply 1 includes an ac input terminal T1, a bypass input terminal T2, a battery terminal T3, and an ac output terminal T4. Ac input terminal T1 receives ac power of a commercial frequency from commercial ac power supply 21. Bypass input terminal T2 receives ac power of commercial frequency from bypass ac power supply 22. The bypass ac power supply 22 may be a commercial ac power supply or a generator.

The battery terminal T3 is connected to the battery (power storage device) 23. The battery 23 stores dc power. A capacitor may be connected instead of the battery 23. Ac output terminal T4 is connected to load 24. The load 24 is driven by ac power.

The uninterruptible power supply device 1 further includes electromagnetic contactors 2, 8, 14, 16, current detectors 3, 11, capacitors 4, 9, 13, reactors 5, 12, a converter 6, a bidirectional chopper 7, an inverter 10, a semiconductor switch 15, an operation unit 17, and a control device 18.

The electromagnetic contactor 2 and the reactor 5 are connected in series between the ac input terminal T1 and an input node of the inverter 6. The capacitor 4 is connected to a node N1 between the electromagnetic contactor 2 and the reactor 5. The electromagnetic contactor 2 is turned on when the uninterruptible power supply unit 1 is in use, and is turned off when the uninterruptible power supply unit 1 is maintained, for example.

The instantaneous value of the ac input voltage Vi appearing at node N1 is detected by control device 18. The presence or absence of power failure or the like is determined based on the instantaneous value of the ac input voltage Vi. The current detector 3 detects an ac input current Ii flowing through the node N1, and provides a signal Iif indicating the detected value to the control device 18.

Capacitor 4 and reactor 5 constitute a low-pass filter, and pass ac power of a commercial frequency from commercial ac power supply 21 to converter 6, thereby preventing a signal of a switching frequency generated by converter 6 from passing to commercial ac power supply 21.

The inverter 6 is controlled by the control device 18 to convert ac power into dc power and output the dc power to the dc line L1 in a normal state where ac power is supplied from the commercial ac power supply 21. In a power failure in which the supply of ac power from commercial ac power supply 21 is stopped, the operation of inverter 6 is stopped. The output voltage of the converter 6 can be controlled to a desired value. The capacitor 4, the reactor 5, and the converter 6 constitute a forward converter.

The capacitor 9 is connected to the dc line L1, and smoothes the voltage of the dc line L1. The instantaneous value of the direct voltage VDC which occurs in the direct current line L1 is detected by the control device 18. The dc line L1 is connected to a high-voltage-side node of the bidirectional chopper 7, and a low-voltage-side node of the bidirectional chopper 7 is connected to a battery terminal T3 via the electromagnetic contactor 8.

The electromagnetic contactor 8 is turned on when the uninterruptible power supply unit 1 is in use, and is turned off when the uninterruptible power supply unit 1and the battery 23 are maintained, for example. The instantaneous value of the inter-terminal voltage VB of the battery 23 appearing at the battery terminal T3 is detected by the control device 18.

The bidirectional chopper 7 is controlled by the control device 18 to store the dc power generated by the converter 6 in the battery 23 in a normal state in which the ac power is supplied from the commercial ac power supply 21, and to supply the dc power of the battery 23 to the inverter 10 via the dc line L1 in a power failure in which the supply of the ac power from the commercial ac power supply 21 is stopped.

When storing the dc power in battery 23, bidirectional chopper 7 steps down dc voltage VDC of dc line L1 and supplies the stepped dc voltage VDC to battery 23. When supplying the dc power of battery 23 to inverter 10, bidirectional chopper 7 boosts inter-terminal voltage VB of battery 23 and outputs it to dc line L1. The dc line L1 is connected to the input node of the inverter 10.

The inverter 10 is controlled by the control device 18, and converts dc power supplied from the converter 6 or the bidirectional chopper 7 via the dc line L1 into ac power of commercial frequency and outputs the ac power. That is, the inverter 10 converts dc power supplied from the converter 6 via the dc line L1 into ac power during normal operation, and converts dc power supplied from the battery 23 via the bidirectional chopper 7 into ac power during power failure. The output voltage of the inverter 10 can be controlled to a desired value.

The output node 10a of the inverter 10 is connected to one terminal of the reactor 12, and the other terminal (node N2) of the reactor 12 is connected to the ac output terminal T4 via the electromagnetic contactor 14. The capacitor 13 is connected to the node N2.

The current detector 11 detects an instantaneous value of the output current Io of the inverter 10, and provides a signal Iof indicating the detected value to the control device 18. The instantaneous value of the ac output voltage Vo present at node N2 is detected by the control device 18.

The reactor 12 and the capacitor 13 constitute a low-pass filter, and pass ac power of a commercial frequency generated by the inverter 10 to the ac output terminal T4, thereby preventing a signal of a switching frequency generated by the inverter 10 from passing to the ac output terminal T4. The inverter 10, the reactor 12, and the capacitor 13 constitute a flyback converter.

The electromagnetic contactor 14 is controlled by the control device 18, and is turned on in an inverter power supply mode in which ac power generated by the inverter 10 is supplied to the load 24, and is turned off in a bypass power supply mode in which ac power from the bypass ac power supply 22 is supplied to the load 24.

The semiconductor switch 15 includes a thyristor (thyristor) and is connected between the bypass input terminal T2 and the ac output terminal T4. The electromagnetic contactor 16 is connected in parallel with the semiconductor switch 15. The semiconductor switch 15 is controlled by the control device 18, normally turned off, and instantaneously turned on in the event of a failure of the inverter 10, and supplies the ac power from the bypass ac power supply 22 to the load 24. The semiconductor switch 15 is turned off after a predetermined time has elapsed from the turn-on.

The electromagnetic contactor 16 is turned off in an inverter power supply mode in which ac power generated by the inverter 10 is supplied to the load 24, and is turned on in a bypass power supply mode in which ac power from the bypass ac power supply 22 is supplied to the load 24.

When the inverter 10 fails, the electromagnetic contactor 16 is turned on to supply the load 24 with ac power from the bypass ac power supply 22. That is, in the case where the inverter 10 fails, the semiconductor switch 15 is instantaneously turned on for a prescribed time, and the electromagnetic contactor 16 is turned on. This is to prevent the semiconductor switch 15 from being damaged by overheating.

The operation unit 17 includes a plurality of buttons operated by a user of the uninterruptible power supply device 1, an image display unit that displays various information, and the like. The user can turn on and off the power supply of the uninterruptible power supply device 1 or select one of the bypass power supply mode and the inverter power supply mode by operating the operation unit 17.

The controller 18 controls the entire uninterruptible power supply 1 based on signals from the operation unit 17, the ac input voltage Vi, the ac input current Ii, the dc voltage VDC, the battery voltage VB, the ac output current Io, the ac output voltage Vo, and the like. That is, the controller 18 detects whether or not a power failure has occurred based on the detected value of the ac input voltage Vi, and controls the converter 6 and the inverter 10 in synchronization with the phase of the ac input voltage Vi.

Further, controller 18 controls inverter 6 so that dc voltage VDC becomes a desired reference voltage VDCr in a normal state in which ac power is supplied from commercial ac power supply 21, and stops the operation of inverter 6 in a power failure in which the supply of ac power from commercial ac power supply 21 is stopped.

Further, the control device 18 controls the bidirectional chopper 7 so that the battery voltage VB becomes a desired reference voltage VBr at the time of normal operation, and controls the bidirectional chopper 7 so that the dc voltage VDC becomes a desired reference voltage VDCr at the time of power failure.

Next, the operation of the uninterruptible power supply 1 will be described. In a normal state where ac power is supplied from the commercial ac power supply 21, if the inverter power supply mode is selected, the semiconductor switch 15 and the electromagnetic contactor 16 are turned off, and the electromagnetic contactors 2, 8, and 14 are turned on.

Ac power supplied from commercial ac power supply 21 is converted into dc power by converter 6. The dc power generated by the converter 6 is stored in the battery 23 via the bidirectional chopper 7 and supplied to the inverter 10. The inverter 10 converts the dc power supplied from the converter 6 into ac power and supplies the ac power to the load 24. The load 24 is driven by the ac power supplied from the inverter 10.

If the supply of ac power from commercial ac power supply 21 is stopped, that is, if a power failure occurs, the operation of converter 6 is stopped, and dc power from battery 23 is supplied to inverter 10 through bidirectional chopper 7. The inverter 10 converts the dc power from the bidirectional chopper 7 into ac power and supplies the ac power to the load 24. Therefore, the operation of the load 24 can be continued while the battery 23 stores the dc power.

Further, in the case where the inverter 10 fails in the inverter power supply mode, the semiconductor switch 15 is instantaneously turned on, the electromagnetic contactor 14 is turned off, and the electromagnetic contactor 16 is turned on. Thus, the ac power from the bypass ac power supply 22 is supplied to the load 24 via the semiconductor switch 15 and the electromagnetic contactor 16, and the operation of the load 24 is continued. After a certain time, the semiconductor switch 15 is turned off, preventing the semiconductor switch 15 from being damaged by overheating.

Fig. 2 is a circuit block diagram showing the configuration of the inverter 10 shown in fig. 1and its peripheral portions. In fig. 2, a positive dc line L1 and a negative dc line L2 are connected between the converter 6 and the inverter 10. The capacitor 9 is connected between the dc lines L1 and L2.

In a normal state where ac power is supplied from commercial ac power supply 21, inverter 6 converts ac input voltage Vi from commercial ac power supply 21 into dc voltage VDC and outputs the dc voltage VDC between dc lines L1 and L2. In a power failure in which the supply of ac power from commercial ac power supply 21 is stopped, inverter 6 is stopped from operating, and bidirectional chopper 7 boosts battery voltage VB and outputs dc voltage VDC to between dc lines L1 and L2.

The inverter 10 includes IGBTs (Insulated Gate Bipolar transistors) Q1 to Q4 and diodes D1 to D4. IGBTQ 1and Q2 constitute the 1 st and 2 nd switching elements, respectively. IGBTQ 1and Q3 have their collectors connected to dc line L1 (the 1 st dc terminal), and their emitters connected to output nodes (ac terminals) 10a and 10b, respectively.

IGBTQ2 and Q4 have collectors connected to output nodes 10a and 10b, respectively, and emitters connected to a dc line L2 (No. 2 dc terminal). Diodes D1 to D4 are connected in anti-parallel to IGBTQ1 to Q4, respectively. An output node 10a of the inverter 10 is connected to a node N2 via a reactor 12 (fig. 1), and an output node 10b is connected to a neutral point NP. Capacitor 13 is connected between node N3 and neutral point NP.

IGBTQ1, Q4 and IGBTQ2, Q3 are alternately turned on. If IGBTQ1, Q4 are turned on and IGBTQ2, Q3 are turned off, the positive side terminal (direct current line L1) of the capacitor 9 is connected to the output node 10a via IGBTQ1, and the output node 10b is connected to the negative side terminal (direct current line L2) of the capacitor 9 via IGBTQ4, outputting the inter-terminal voltage of the capacitor 9 between the output nodes 10a, 10 b. That is, a positive dc voltage is output between the output nodes 10a and 10 b.

If IGBTQ2, Q3 are turned on and IGBTQ1, Q4 are turned off, the positive side terminal (direct current line L1) of the capacitor 9 is connected to the output node 10b via IGBTQ3, and the output node 10a is connected to the negative side terminal (direct current line L2) of the capacitor 9 via IGBTQ2, outputting the inter-terminal voltage of the capacitor 9 between the output nodes 10b, 10 a. That is, a negative dc voltage is output between the output nodes 10a and 10 b.

Here, a problem of the inverter 10 will be explained. As described above, IGBTQ 1and IGBTQ2 are alternately turned on. When switching from the on state of IGBTQ1 to the on state of IGBTQ2, if IGBTQ2 is on although IGBTQ1 has not yet become the off state, an overcurrent flows from the positive side terminal (dc line L1) of capacitor 9 to the negative side terminal (dc line L2) of capacitor 9 via IGBTQ 1and Q2, and IGBTQ 1and Q2 break down.

In contrast, when switching from the on state of IGBTQ2 to the on state of IGBTQ1, if IGBTQ1 is on although IGBTQ2 has not yet become the off state, an overcurrent flows from the positive side terminal (dc line L1) of capacitor 9 to the negative side terminal (dc line L2) of capacitor 9 via IGBTQ 1and Q2, and IGBTQ 1and Q2 are broken. IGBTQ4 and Q3 also have the same problems as IGBTQ 1and Q2. Embodiment 1 solves this problem.

Fig. 3 is a circuit block diagram showing a configuration of inverter control unit 30 that controls inverter 10 shown in fig. 1. The inverter control unit 30 is included in the control device 18. In fig. 3, the inverter control unit 30 includes a voltage command unit 31, a triangular wave generator 32, a comparator 33, a buffer 34, an inverter 35, and gate (gate) drive circuits 36 and 37.

The voltage command unit 31 generates a sinusoidal voltage command value Vor based on the instantaneous value of the ac output voltage Vo appearing at the node N2 (fig. 1) and the output signal Iof of the current detector 11 (fig. 1). The phase of the voltage command value Vor is synchronized with the phase of the ac input voltage Vi of the corresponding phase (here, U phase) among the three phases (U phase, V phase, W phase).

The triangular wave generator 32 outputs a triangular wave signal Cu1 of a frequency fH (e.g., 20KHz) sufficiently higher than a commercial frequency (e.g., 60 Hz). The comparator 33 outputs a PWM signal Au1 indicating a comparison result between the voltage command value Vor from the voltage command unit 31 and the triangular wave signal Cu1 from the triangular wave generator 32. The buffer 34 gives the PWM signal Au1 to the gate drive circuits 36, 37. The inverter 35 inverts the PWM signal Au1 to generate a PWM signal Bu1, and outputs the PWM signal Bu1 to the gate drive circuits 36 and 37.

Fig. 4 (a), 4 (B), and 4 (C) are timing charts showing waveforms of the voltage command value Vor, the triangular wave signal Cu1, and the PWM signals Au 1and Bu1 shown in fig. 3. As shown in fig. 4 (a), the voltage command value Vor is a sine wave signal of a commercial frequency. The frequency of the triangular wave signal Cu1 is higher than the frequency of the voltage command value Vor (commercial frequency). The peak value on the positive side of the triangular wave signal Cu1 is higher than the peak value on the positive side of the voltage command value Vor. The peak value on the negative side of the triangular wave signal Cu1 is lower than the peak value on the negative side of the voltage command value Vor.

As shown in fig. 4 a and 4B, when the level of the triangular wave signal Cu1 is higher than the voltage command value Vor, the PWM signal Au1 is at the "L" (low) level, and when the level of the triangular wave signal Cu1 is lower than the voltage command value Vor, the PWM signal Au1 is at the "H" (high) level. The PWM signal Au1 becomes a positive pulse signal train.

During the period in which the voltage command value Vor is positive, if the voltage command value Vor rises, the pulse width of the PWM signal Au1 increases. In the period in which the voltage command value Vor is negative, if the voltage command value Vor falls, the pulse width of the PWM signal Au1 decreases. As shown in fig. 4 (B) and 4 (C), the PWM signal Bu1 is an inverted signal of the PWM signal Au 1.

Here, if the PWM signal Au1 set at the "H" level is set as the 1 st control signal and the PWM signal Bu1 set at the "H" level is set as the 2 nd control signal, the 1 st and 2 nd control signals are alternately output as shown in fig. 4 (B) and 4 (C). The voltage command unit 31, the triangular wave generator 32, the comparator 33, the buffer 34, and the inverter 35 constitute a 1 st control circuit that alternately outputs 1 st and 2 nd control signals.

Returning to fig. 3, the gate driving circuit 36 generates gate driving signals VG1, VG2 for turning IGBTQ1, Q2 on and off based on the PWM signals Au1, Bu 1and collector-emitter voltages V1, V2 of IGBTQ1, Q2.

If the gate drive signal VG1 is placed at the "H" level of the activation level, IGBTQ1 turns on. If IGBTQ1 is turned on, the collector-emitter voltage V1 of IGBTQ1 becomes the minimum value V1L. If the gate drive signal VG1 is placed at the "L" level, which is an inactive level, IGBTQ1 turns off. If IGBTQ1 is turned off, collector-emitter voltage V1 of IGBTQ1 becomes maximum V1H. A predetermined threshold voltage VTH1 is set between V1L and V1H.

If the gate drive signal VG2 is placed at the "H" level of the activation level, IGBTQ2 turns on. If IGBTQ2 is turned on, the collector-emitter voltage V2 of IGBTQ2 becomes the minimum value V2L. If the gate drive signal VG2 is placed at the "L" level, which is an inactive level, IGBTQ2 turns off. If IGBTQ2 is turned off, the collector-emitter voltage V2 of IGBTQ2 becomes the maximum value V2H. A predetermined threshold voltage VTH2 is set between V2L and V2H.

When IGBTQ1 is turned on, when PWM signal Au1 is lowered from "H" level to "L" level and PWM signal Bu1 is raised from "L" level to "H" level, gate drive circuit 36 sets gate drive signal VG1 to "L" level, which is a non-active level, compares collector-emitter voltage V1 of IGBTQ1 with threshold voltage VTH1, determines that IGBTQ1 is in an off state when V1 exceeds VTH1, sets gate drive signal VG2 to "H" level, which is an active level, and turns on IGBTQ 2.

When IGBTQ2 is on, when PWM signal Au1 is raised from the "L" level to the "H" level and PWM signal Bu1 is lowered from the "H" level to the "L" level, gate drive circuit 36 sets gate drive signal VG2 to the "L" level, which is an inactive level, and sets collector-emitter voltage V2 and threshold voltage VTH2 of IGBTQ2 to high and low levels, and when V2 exceeds VTH2, determines that IGBTQ2 is in an off state, sets gate drive signal VG1 to the "H" level, which is an active level, and turns on IGBTQ 1.

The gate drive circuit 37 generates gate drive signals VG3 and VG4 for turning on and off IGBTQ3 and Q4 based on the PWM signals Au 1and Bu 1and collector-emitter voltages V3 and V4 of IGBTQ3 and Q4.

If the gate drive signal VG3 is placed at the "H" level of the activation level, IGBTQ3 turns on. If IGBTQ3 is turned on, the collector-emitter voltage V3 of IGBTQ3 becomes the minimum value V3L. If the gate drive signal VG3 is placed at the "L" level, which is an inactive level, IGBTQ3 turns off. If IGBTQ3 is turned off, the collector-emitter voltage V3 of IGBTQ3 becomes the maximum value V3H. A predetermined threshold voltage VTH3 is set between V3L and V3H.

If the gate drive signal VG4 is placed at the "H" level of the activation level, IGBTQ4 turns on. If IGBTQ4 is turned on, the collector-emitter voltage V4 of IGBTQ4 becomes the minimum value V4L. If the gate drive signal VG4 is placed at the "L" level, which is an inactive level, IGBTQ4 turns off. If IGBTQ4 is turned off, the collector-emitter voltage V4 of IGBTQ4 becomes the maximum value V4H. A predetermined threshold voltage VTH4 is set between V4L and V4H.

When IGBTQ4 is turned on, when PWM signal Au1 is lowered from "H" level to "L" level and PWM signal Bu1 is raised from "L" level to "H" level, gate drive circuit 37 sets gate drive signal VG4 to "L" level, which is a non-active level, compares collector-emitter voltage V4 of IGBTQ4 with threshold voltage VTH4, determines that IGBTQ4 is in an off state when V4 exceeds VTH4, sets gate drive signal VG3 to "H" level, which is an active level, and turns on IGBTQ 3.

When IGBTQ3 is on, when PWM signal Au1 is raised from the "L" level to the "H" level and PWM signal Bu1 is lowered from the "H" level to the "L" level, gate drive circuit 37 sets gate drive signal VG3 to the "L" level, which is an inactive level, compares collector-emitter voltage V3 of IGBTQ3 with threshold voltage VTH3, determines that IGBTQ3 is in an off state when V3 exceeds VTH3, sets gate drive signal VG4 to the "H" level, which is an active level, and turns on IGBTQ 4.

Fig. 5 is a circuit block diagram showing the configuration of the gate driver circuit 36. In fig. 5, the gate drive circuit 36 includes voltage detectors 41, 42, comparators 43, 44, delay circuits 45, 46, AND gates 47, 48 AND drivers 49, 50.

The voltage detector 41 detects a collector-emitter voltage V2 of IGBTQ2, and outputs a signal V2f indicating the detected value. The voltage detector 42 detects a collector-emitter voltage V1 of IGBTQ1, and outputs a signal V1f indicating the detected value.

The comparator 43 (2 nd comparator) compares the voltage V2 indicated by the output signal V2f of the voltage detector 41 with the threshold voltage VTH2, and outputs a signal Φ 43 indicating the comparison result. When V2< VTH2, the signal φ 43 is at the "L" level, and when V2> VTH2, the signal φ 43 is at the "H" level.

The comparator 44 (1 st comparator) compares the voltage V1 indicated by the output signal V1f of the voltage detector 42 with the threshold voltage VTH1, and outputs a signal Φ 44 indicating the comparison result. When V1< VTH1, the signal φ 44 is at "L" level, and when V1> VTH1, the signal φ 44 is at "H" level.

The threshold voltages VTH 1and VTH2 are set according to the characteristics of IGBTQ 1and Q2, respectively. The threshold voltages VTH 1and VTH2 may be different voltages or the same voltage.

The delay circuit 45 delays only the rising edge of the PWM signal Au1 by a predetermined time Td1 to generate the signal Φ 45. The delay circuit 46 delays only the rising edge of the PWM signal Bu1 by a predetermined time Td2 to generate the signal Φ 46. The delay times Td 1and Td2 are set according to the characteristics of IGBTQ 1and Q2, respectively. The delay times Td 1and Td2 may be different times or the same time.

Fig. 6 is a circuit diagram showing the configuration of the delay circuit 45. In fig. 6, the delay circuit 45 includes an AND gate 51AND an inverter 52 of an even-numbered stage connected in series. The PWM signal Au1 is directly supplied to one input node of the AND gate 51, AND is supplied to the other input node of the AND gate 51 via the inverter 52 of the even-numbered stage. The output signal of the AND gate 51 becomes the output signal Φ 45 of the delay circuit 45. The number of inverters 52 is set according to the delay time Td 1.

In the case where the PWM signal Au1 is placed at the "H" level, the output signal Φ 52 of the inverter 52 at the final stage is at the "H" level, AND the output signal Φ 45 of the AND gate 51 is at the "H" level. If the PWM signal Au1 is reduced from the "H" level to the "L" level, the output signal Φ 45 of the AND gate 51 is immediately reduced from the "H" level to the "L" level.

In the case where the PWM signal Au1 is set to the "L" level, the output signal Φ 52 of the inverter 52 of the final stage is at the "L" level, AND the output signal Φ 45 of the AND gate 51 is at the "L" level. If the PWM signal Au1 is lowered from the "L" level to the "H" level, the output signal Φ 52 of the inverter 52 of the final stage is raised from the "L" level to the "H" level AND the output signal Φ 45 of the AND gate 51 is raised from the "L" level to the "H" level after the lapse of the delay time Td 1.

Therefore, according to this delay circuit 45, only the rising edge among the rising edge and the falling edge of the PWM signal Au1 is delayed by the delay time Td 1. The delay circuit 46 has the same configuration as the delay circuit 45.

Returning to fig. 5, the AND gate 47 outputs a logical product signal phi 47 of the output signal phi 43 of the comparator 43 AND the output signal phi 45 of the delay circuit 45. The driver 49 generates the gate drive signal VG1 at the same logic level as the signal phi 47. The gate drive signal VG1 is a voltage signal that is provided between the gate and the emitter of the corresponding IGBTQ 1.

The AND gate 48 outputs a logical product signal phi 48 of the output signal phi 44 of the comparator 44 AND the output signal phi 46 of the delay circuit 46. The driver 50 generates the gate drive signal VG2 at the same logic level as the signal phi 48. The gate drive signal VG2 is a voltage signal that is provided between the gate and the emitter of the corresponding IGBTQ 2.

Fig. 7 is a timing chart illustrating an operation of the gate driver circuit 36 shown in fig. 5. Fig. 7 shows the operation of the gate drive circuit 36 when the PWM signal Au1 falls from the "H" level to the "L" level.

In fig. 7, (a) shows a waveform of the PWM signal Au1, (B) shows a waveform of the output signal Φ 45 of the delay circuit 45, (C) shows a waveform of the gate drive signal VG1, (D) shows a waveform of the collector-emitter voltage V1 of the IGBTQ1, and (E) shows a waveform of the output signal Φ 44 of the comparator 44.

Further, (F) shows the waveform of the PWM signal Bu1, (G) shows the waveform of the output signal Φ 46 of the delay circuit 46, (H) shows the waveform of the output signal Φ 48 of the AND gate 48, (I) shows the waveform of the gate drive signal VG2, (J) shows the waveform of the collector-emitter voltage V2 of the IGBTQ2, AND (K) shows the waveform of the output signal Φ 43 of the comparator 43.

At time t0, the PWM signal Au1 is placed at the "H" level, the output signal Φ 45 of the delay circuit 45 is at the "H" level, and the gate drive signal VG1 is placed at the "H" level of the activation level. Therefore, IGBTQ1 is turned on, and collector-emitter voltage V1 of IGBTQ1 becomes minimum value V1L, and output signal Φ 44 of comparator 44 becomes "L" level.

Further, the PWM signal Bu1 is placed at the "L" level, the output signal Φ 46 of the delay circuit 46 is placed at the "L" level, the output signal Φ 48 of the AND gate 48 is at the "L" level, AND the gate drive signal VG2 is placed at the "L" level which is the inactive level. Therefore, IGBTQ2 is turned off, and collector-emitter voltage V2 of IGBTQ2 becomes maximum value V2H, and output signal Φ 43 of comparator 43 becomes "H" level.

If the PWM signal Au1 is lowered to the "L" level at a certain time t1, the output signal Φ 45 of the delay circuit 45 is lowered to the "L" level, the gate drive signal VG1 is lowered toward the "L" level of the inactive level, and the collector-emitter voltage V1 of the IGBTQ1 is raised toward the maximum value V1H.

If the collector-emitter voltage V1 of IGBTQ1 exceeds the threshold voltage VTH1 (time t2), the output signal φ 44 of comparator 44 is raised to an "H" level. The threshold voltage VTH1 is set to a voltage slightly lower than the maximum value V1H of V1, and if V1> VTH1, IGBTQ1 is turned off.

Further, at the time t1, the PWM signal Bu1 is raised to the "H" level, and the output signal Φ 46 of the delay circuit 46 is raised to the "H" level after the lapse of the delay time Td2 from the time t 1.

If the output signal φ 44 of the comparator 44 is raised to the "H" level at time t2, the output signal φ 48 of the AND gate 48 is raised to the "H" level, the gate drive signal VG2 is raised toward the "H" level, AND the collector-emitter voltage V2 of IGBTQ2 is lowered toward the minimum value V2L.

If the collector-emitter voltage V2 of IGBTQ2 falls below the threshold voltage VTH2 (time t3), the output signal φ 43 of comparator 43 is lowered to "L" level. At time t4, collector-emitter voltage V2 of IGBTQ2 reaches minimum value V2L, and IGBTQ2 is turned on.

Fig. 8 is another timing chart illustrating the operation of the gate driver circuit 36 shown in fig. 5. Fig. 8 shows the operation of the gate drive circuit 36 when the PWM signal Au1 rises from the "L" level to the "H" level.

In fig. 8, (a) shows a waveform of the PWM signal Bu1, (B) shows a waveform of the output signal Φ 46 of the delay circuit 46, (C) shows a waveform of the gate drive signal VG2, (D) shows a waveform of the collector-emitter voltage V2 of the IGBTQ2, and (E) shows a waveform of the output signal Φ 43 of the comparator 43.

Further, (F) shows a waveform of the PWM signal Au1, (G) shows a waveform of the output signal Φ 45 of the delay circuit 45, (H) shows a waveform of the output signal Φ 47 of the AND gate 47, (I) shows a waveform of the gate drive signal VG1, (J) shows a waveform of the collector-emitter voltage V1 of the IGBTQ1, AND (K) shows a waveform of the output signal Φ 44 of the comparator 44.

At time t0, PWM signal Bu1 is set to "H" level, output signal Φ 46 of delay circuit 46 is set to "H" level, gate drive signal VG2 is set to "H" level of the active level, IGBTQ2 is turned on, collector-emitter voltage V2 of IGBTQ2 becomes minimum value V2L, and output signal Φ 43 of comparator 43 is set to "L" level.

Further, the PWM signal Au1 is set to the "L" level, the output signal Φ 45 of the delay circuit 45 is set to the "L" level, the output signal Φ 47 of the AND gate 47 is set to the "L" level, the gate drive signal VG1 is set to the "L" level, the IGBTQ1 is turned off, the collector-emitter voltage V1 of the IGBTQ1 is the maximum value V1H, AND the output signal Φ 44 of the comparator 44 is set to the "H" level.

At a certain time t1, if the PWM signal Au1 is raised to the "H" level and the PWM signal Bu1 is lowered to the "L" level, the output signal Φ 46 of the delay circuit 46 is lowered to the "L" level, the gate drive signal VG2 is lowered toward the "L" level of the inactive level, and the collector-emitter voltage V2 of the IGBTQ2 is raised toward the maximum value V2H.

If the collector-emitter voltage V2 of IGBTQ2 exceeds the threshold voltage VTH2 (time t2), the output signal φ 43 of comparator 43 is raised to an "H" level. The threshold voltage VTH2 is set to a voltage slightly lower than the maximum value V2H of V2, and if V2> VTH2, IGBTQ2 is turned off. Further, after the delay time Td1 elapses from when the PWM signal Au1 is raised to the "H" level, the output signal Φ 45 of the delay circuit 45 is raised to the "H" level.

If the output signal Φ 43 of the comparator 43 is raised to the "H" level at time t2, the output signal Φ 47 of the AND gate 47 is raised to the "H" level, the gate drive signal VG1 rises toward the "H" level, AND the collector-emitter voltage V1 of the IGBTQ1 falls toward the minimum value V1L. If the collector-emitter voltage V1 of IGBTQ1 falls below the threshold voltage VTH1 (time t3), the output signal φ 44 of comparator 44 is lowered to "L" level. At time t4, collector-emitter voltage V1 of IGBTQ1 reaches minimum value V1L, and IGBTQ1 is turned on.

The structure and operation of the gate driver circuit 37 (fig. 3) are the same as those of the gate driver circuit 36, and therefore, the description thereof will not be repeated.

Fig. 9 is a circuit block diagram showing the configuration of the inverter 6 shown in fig. 1and its peripheral portion, and is a diagram compared with fig. 2. In fig. 9, inverter 6 includes IGBTQ11 to Q14 and diodes D11 to D14. IGBTQ11 and Q12 constitute the 1 st and 2 nd switching elements, respectively. IGBTQ11 and Q13 have their collectors connected to dc line L1 (the 1 st dc terminal), and their emitters connected to input nodes (ac terminals) 6a and 6b, respectively.

IGBTQ12 and Q14 have collectors connected to input nodes 6a and 6b, respectively, and emitters connected to dc line L2. Diodes D11 to D14 are connected in anti-parallel to IGBTQ11 to Q14, respectively. Input node 6a of converter 6 is connected to node N1 via reactor 5 (fig. 1), and input node 6b is connected to neutral point NP. Capacitor 4 is connected between node N1 and neutral point NP.

As is apparent from fig. 2 and 9, the inverter 10 and the converter 6 have the same configuration as seen from the capacitor 9. After the initial charging of capacitor 9 is completed, converter 6 operates in the same manner as inverter 10. When capacitor 9 is initially charged, the operation of inverter 10 is stopped, and IGBTQ11 to Q14 are turned off. An ac input voltage Vi supplied from a commercial ac power supply 21 (fig. 1) is full-wave rectified by diodes D11 to D14, supplied between dc lines L1 and L2, smoothed by a capacitor 9, and becomes a dc voltage VDC. A dc power supply for initially charging the capacitor 9 may be additionally provided.

If the initial charging of the capacitor 9 is completed, the on/off control of the IGBTQ 11-Q14 is started. In this converter 6, as in the inverter 10, IGBTQ11, Q14 and IGBTQ12, Q13 are alternately turned on.

If IGBTQ11, Q14 are turned on and IGBTQ12, Q13 are turned off, the positive side terminal (direct current line L1) of the capacitor 9 is connected to the input node 6a via IGBTQ11, and the input node 6b is connected to the negative side terminal (direct current line L2) of the capacitor 9 via IGBTQ14, outputting the inter-terminal voltage of the capacitor 9 between the input nodes 6a, 6 b. That is, a positive dc voltage is output between the input nodes 6a and 6 b.

If IGBTQ12, Q13 are turned on and IGBTQ11, Q14 are turned off, the positive side terminal (direct current line L1) of the capacitor 9 is connected to the input node 6b via IGBTQ13, and the input node 6a is connected to the negative side terminal (direct current line L2) of the capacitor 9 via IGBTQ12, outputting the inter-terminal voltage of the capacitor 9 between the input nodes 6b, 6 a. That is, a negative dc voltage is output between the input nodes 6a and 6 b.

Here, the problem of the inverter 6 will be explained. As described above, IGBTQ11 and IGBTQ12 are alternately turned on. When switching from the on state of IGBTQ11 to the on state of IGBTQ12, if IGBTQ12 is on although IGBTQ11 has not yet become the off state, an overcurrent flows from the positive side terminal (dc line L1) of capacitor 9 to the negative side terminal (dc line L2) of capacitor 9 via IGBTQ11 and Q12, and IGBTQ11 and Q12 break down.

In contrast, when switching from the state where IGBTQ12 is on to the state of IGBTQ11, if IGBTQ11 is on although IGBTQ12 has not yet become the off state, an overcurrent flows from the positive-side terminal (dc line L1) of capacitor 9 to the negative-side terminal (dc line L2) of capacitor 9 via IGBTQ11 and Q12, and IGBTQ11 and Q12 break down. IGBTQ14 and Q13 also have the same problems as IGBTQ11 and Q12. Embodiment 1 also solves this problem.

Fig. 10 is a circuit block diagram showing a configuration of inverter control unit 60 included in control device 18 shown in fig. 1. In fig. 10, the converter control unit 60 includes a voltage command unit 61, a triangular wave generator 62, a comparator 63, a buffer 64, an inverter 65, and gate drive circuits 66 and 67.

Voltage command unit 61 generates a sinusoidal voltage command value Vir based on inter-terminal voltage VDC of capacitor 9, an instantaneous value of ac input voltage Vi appearing at node N1 (fig. 1), and output signal Iif of current detector 3 (fig. 1).

That is, voltage command unit 61 sets phase difference θ between voltage command value Vir and ac input voltage Vi based on deviation Δ VDC of dc voltage VDC and reference voltage VDCr being VDC-VDCr. When Δ VDC >0, θ >0 is set. In this case, the phase of the ac voltage output to the node 6a or 6b of the inverter 6 is earlier than the phase of the ac input voltage Vi, and the power is supplied from the capacitor 9 to the commercial ac power supply 21, so that the dc voltage VDC decreases.

When Δ VDC <0, θ <0 is assumed. In this case, the phase of the ac voltage output to the nodes 6a and 6b of the inverter 6 is delayed from the phase of the ac input voltage Vi, and the commercial ac power supply 21 supplies power to the capacitor 9, thereby increasing the dc voltage VDC. Thus, the dc voltage VDC is maintained as the reference voltage VDCr.

The triangular wave generator 62 outputs a triangular wave signal Cu2 of a sufficiently high frequency fH (e.g., 20KHz) compared to the commercial frequency (e.g., 60 Hz). The comparator 63 compares the voltage command value Vir from the voltage command unit 61 with the triangular wave signal Cu2 from the triangular wave generator 62, and outputs a PWM signal Au2 indicating the comparison result. The buffer 64 gives the PWM signal Au2 to the gate drive circuit 66. The inverter 65 inverts the PWM signal Au2 to generate a PWM signal Bu2, which is supplied to the gate drive circuit 66.

The waveforms of the voltage command value Vir, the triangular wave signal Cu2, and the PWM signals Au2 and Bu2 are the same as those of the voltage command value Vor, the triangular wave signal Cu1, and the PWM signals Au 1and Bu1 shown in fig. 4.

Returning to fig. 10, the gate driving circuit 66 generates gate driving signals VG11, VG12 for controlling IGBTQ11, Q12 based on collector-emitter voltages V11, V12 of the PWM signals Au2, Bu2, IGBTQ111, Q12.

If the gate drive signal VG11 is placed at the "H" level of the activation level, IGBTQ11 turns on. If IGBTQ11 is turned on, the collector-emitter voltage V11 of IGBTQ11 becomes the minimum value V11L. If the gate drive signal VG11 is placed at the "L" level, which is an inactive level, IGBTQ11 turns off. If IGBTQ11 is turned off, collector-emitter voltage V11 of IGBTQ11 becomes maximum V11H. A predetermined threshold voltage VTH11 is set between V11L and V11H.

If the gate drive signal VG12 is placed at the "H" level of the activation level, IGBTQ12 turns on. If IGBTQ12 is turned on, the collector-emitter voltage V12 of IGBTQ12 becomes the minimum value V12L. If the gate drive signal VG12 is placed at the "L" level, which is an inactive level, IGBTQ12 turns off. If IGBTQ12 is turned off, the collector-emitter voltage V12 of IGBTQ12 becomes the maximum value V12H. A predetermined threshold voltage VTH12 is set between V12L and V12H.

When IGBTQ11 is turned on, when PWM signal Au2 is lowered from "H" level to "L" level and PWM signal Bu2 is raised from "L" level to "H" level, gate drive circuit 66 sets gate drive signal VG11 to "L" level, which is an inactive level, compares collector-emitter voltage V11 of IGBTQ11 with threshold voltage VTH11, determines that IGBTQ11 is in an off state when V11 exceeds VTH11, sets gate drive signal VG12 to "H" level, which is an active level, and turns on IGBTQ 12.

When IGBTQ12 is on, when PWM signal Au2 is raised from the "L" level to the "H" level and PWM signal Bu2 is lowered from the "H" level to the "L" level, gate drive circuit 66 sets gate drive signal VG12 to the "L" level, which is an inactive level, compares collector-emitter voltage V12 of IGBTQ12 with threshold voltage VTH12, determines that IGBTQ12 is in an off state when V12 exceeds VTH12, sets gate drive signal VG11 to the "H" level, which is an active level, and turns on IGBTQ 11.

The gate drive circuit 67 generates gate drive signals VG13 and VG14 for turning on and off IGBTQ13 and Q14 based on the PWM signals Au2 and Bu2 and the collector-emitter voltages V13 and V14 of IGBTQ13 and Q14.

If the gate drive signal VG13 is placed at the "H" level of the activation level, IGBTQ13 turns on. If IGBTQ13 is turned on, the collector-emitter voltage V13 of IGBTQ13 becomes the minimum value V13L. If the gate drive signal VG13 is placed at the "L" level, which is an inactive level, IGBTQ13 turns off. If IGBTQ13 is turned off, the collector-emitter voltage V13 of IGBTQ13 becomes the maximum value V13H. A predetermined threshold voltage VTH13 is set between V13L and V13H.

If the gate drive signal VG14 is placed at the "H" level of the activation level, IGBTQ14 turns on. If IGBTQ14 is turned on, the collector-emitter voltage V14 of IGBTQ14 becomes the minimum value V14L. If the gate drive signal VG14 is placed at the "L" level, which is an inactive level, IGBTQ14 turns off. If IGBTQ14 is turned off, the collector-emitter voltage V14 of IGBTQ14 becomes the maximum value V14H. A predetermined threshold voltage VTH14 is set between V14L and V14H.

When IGBTQ14 is turned on, when PWM signal Au2 is lowered from "H" level to "L" level and PWM signal Bu2 is raised from "L" level to "H" level, gate drive circuit 67 sets gate drive signal VG14 to "L" level, which is an inactive level, compares the level of collector-emitter voltage V14 of IGBTQ14 with the level of threshold voltage VTH14, determines that IGBTQ14 is in an off state when V14 exceeds VTH14, sets gate drive signal VG13 to "H" level, which is an active level, and turns on IGBTQ 13.

When IGBTQ13 is on, when PWM signal Au2 is raised from the "L" level to the "H" level and PWM signal Bu2 is lowered from the "H" level to the "L" level, gate drive circuit 67 sets gate drive signal VG13 to the "L" level, which is an inactive level, compares collector-emitter voltage V13 of IGBTQ13 with threshold voltage VTH13, determines that IGBTQ13 is in an off state when V13 exceeds VTH13, sets gate drive signal VG14 to the "H" level, which is an active level, and turns on IGBTQ 14.

The configuration and operation of each of the gate drive circuits 66 and 67 are the same as those of the gate drive circuit 36 shown in fig. 5 to 8, and therefore, the description thereof will not be repeated.

As described above, in embodiment 1, when switching from the on state of IGBTQ1 to the on state of IGBTQ2, gate drive signal VG1 is set to the inactive level, and gate drive signal VG2 is set to the active level in accordance with the case where inter-terminal voltage V1 of IGBTQ1 exceeds threshold voltage VTH 1. Therefore, since IGBTQ2 is turned on when IGBTQ1 is actually turned off, an overcurrent can be prevented from flowing through IGBTQ 1and Q2, and efficiency can be improved. The other IGBTQ3, Q4, and Q11 to Q14 are also the same as IGBTQ 1and Q2.

Fig. 11 is a circuit block diagram showing a modification of embodiment 1, and is a diagram compared with fig. 5. Referring to fig. 11, in this modification, the gate drive circuit 36 is replaced with a gate drive circuit 36A. The gate drive circuit 36A differs from the gate drive circuit 36 in that: the delay circuits 45, 46 are eliminated, the PWM signal Au1 is given directly to the other input node of the AND gate 47, AND the PWM signal Bu1 is given directly to the other input node of the AND gate 48. This is the same as setting the delay times Td1, Td2 of the delay circuits 46, 47 to 0 seconds. The other gate drive circuits 37, 66, and 67 are also changed to the same configuration as the gate drive circuit 36A. In this modification, the same effects as those of embodiment 1 can be obtained.

Fig. 12 is a circuit block diagram showing a comparative example of embodiment 1, and is a diagram compared with fig. 5. Referring to fig. 12, in this comparative example, the gate drive circuit 36 is replaced with a gate drive circuit 36B. The gate drive circuit 36B differs from the gate drive circuit 36 in that: the voltage detectors 41 AND 42, the comparators 43 AND 44, AND the AND gates 47 AND 48 are removed, AND the delay circuits 45 AND 46 are replaced with delay circuits 45A AND 46A.

The delay circuit 45A delays only the rising edge of the PWM signal Au1 out of the rising edge and the falling edge by a certain dead time TD1, and provides the delayed signal to the driver 49. The delay circuit 45B delays only the rising edge of the rising edge and the falling edge of the PWM signal Bu1 by a certain dead time TD2, and provides the delayed rising edge to the driver 49.

In the case where IGBTQ1, Q2 are set to the on state and the off state, respectively, if the PWM signal Au1 is lowered from the "H" level to the "L" level and the PWM signal Bu1 is raised from the "L" level to the "H" level, the gate drive signal VG1 is quickly lowered to the "L" level, IGBTQ1 is turned off, the gate drive signal VG2 is raised to the "H" level after the dead time TD2 elapses, and IGBTQ2 is turned on.

Further, in the case where IGBTQ1, Q2 are set to the off state and the on state, respectively, if the PWM signal Au1 is raised from the "L" level to the "H" level and the PWM signal Bu1 is lowered from the "H" level to the "L" level, the gate drive signal VG2 is rapidly lowered to the "L" level, IGBTQ2 is turned off, the gate drive signal VG1 is raised to the "H" level after the elapse of the dead time TD1, and IGBTQ1 is turned on. The other gate drive circuits 37, 66, and 67 are also changed to have the same configuration as the gate drive circuit 36B.

In this comparative example, the dead times TD 1and TD2 are each fixed to a constant value. However, the off delay time Toff from when the gate drive signal VG1 is set to "L" level to when IGBTQ1 actually turns off varies in inverse proportion to the current (off current Ioff) flowing through IGBTQ1 when the gate drive signal VG1 is at "H" level.

Fig. 13 is a graph illustrating a relationship between the off current Ioff and the off delay time Toff. As shown in fig. 13, when the off current Ioff is the minimum value, the off delay time Toff becomes the maximum value, and as the off current Ioff increases, the off delay time Toff decreases.

Therefore, depending on the value of the off-current Ioff, the off-delay time Toff is longer than each of the dead times TD 1and TD2, and IGBTQ2 (or Q1) is turned on before IGBTQ1 (or Q2) is turned off, and there is a possibility that an overcurrent flows. On the other hand, if the dead time TD1 (or TD2) is set to a sufficiently longer time than the off delay time Toff, the on time of IGBTQ1 (or Q2) becomes shorter, and the efficiency decreases.

In contrast, in embodiment 1, when switching from the on state of IGBTQ1 to the on state of IGBTQ2, the gate drive signal VG1 is set to the inactive level, and the gate drive signal VG2 is set to the active level in accordance with the case where the inter-terminal voltage V1 of IGBTQ1 exceeds the threshold voltage VTH 1. Thus, IGBTQ2 is turned on when IGBTQ1 is actually turned off, so that an overcurrent can be prevented from flowing in IGBTQ1, Q2, and an improvement in efficiency can be achieved.

[ embodiment 2]

Fig. 14 is a circuit block diagram showing a configuration of an uninterruptible power supply device 70 according to embodiment 2 of the present invention, and is a diagram compared with fig. 1. Referring to fig. 14, the uninterruptible power supply device 70 differs from the uninterruptible power supply device 1 according to embodiment 1 in that the converter 6, the bidirectional chopper 7, the inverter 10, and the control device 18 are replaced with a converter 71, a bidirectional chopper 72, an inverter 73, and a control device 73, respectively.

Fig. 15 is a circuit block diagram showing the inverter 73 and its peripheral portion. In fig. 15, 3 dc lines L1 to L3 are connected between the converter 71 and the inverter 73. The dc line L2 is connected to the neutral point NP and is set to a neutral point voltage (for example, 0V). The capacitor 9 comprises 2 capacitors 9a, 9 b. The capacitor 9a is connected between the dc lines L1 and L2. The capacitor 9b is connected between the dc lines L2 and L3.

In a normal state where ac power is supplied from commercial ac power supply 21, inverter 71 converts ac power from commercial ac power supply 21 into dc power and supplies the dc power to dc lines L1 to L3. At this time, the inverter 71 charges the capacitors 9a and 9b so that the dc voltage VDCa between the dc lines L1 and L2 becomes the reference voltage VDCr and the dc voltage VDCb between the dc lines L2 and L3 becomes the reference voltage VDCr.

The voltages of the dc lines L1, L2, and L3 are set to a positive dc voltage (+ VDCr), a neutral point voltage (0V), and a negative dc voltage (-VDCr), respectively. In a power failure in which the supply of ac power from commercial ac power supply 21 is stopped, the operation of inverter 71 is stopped.

The bidirectional chopper 72 stores the dc power generated by the converter 71 in the battery 23 when normal. At this time, the bidirectional chopper 72 charges the battery 23 so that the inter-terminal voltage VB of the battery 23 becomes the reference voltage VBr.

The bidirectional chopper 72 supplies dc power of the battery 23 to the inverter 73 when power is cut. At this time, the bidirectional chopper 72 charges the capacitors 9a and 9b, respectively, so that the inter-terminal voltages VDCa and VDCb of the capacitors 9a and 9b become the reference voltage VDCr, respectively.

The inverter 73 converts the dc power generated by the converter 71 into ac power of a commercial frequency and supplies the ac power to the load 24 in a normal state. At this time, the inverter 73 generates an ac output voltage Vo of a commercial frequency based on the positive dc voltage, the neutral point voltage, and the negative dc voltage supplied from the dc lines L1 to L3.

The inverter 73 includes IGBTQ21 to Q24 and diodes D21 to D24. IGBTQ21 (the 1 st switching element) has a collector connected to dc line L1 (the 1 st dc terminal) and an emitter connected to output node 72a (the ac terminal). IGBTQ22 and Q24 (the 2 nd and 4 th switching elements) have their collectors connected to each other, and their emitters connected to dc line L2 (the 2 nd dc terminal) and output node 72a, respectively. IGBTQ23 (the 3 rd switching element) has a collector connected to output node 72a and an emitter connected to dc line L3 (the 3 rd dc terminal). Diodes D21 to D24 are connected in anti-parallel to IGBTQ21 to Q24, respectively. The output node 72a is connected to the node N2 via the reactor 12.

In inverter 73, IGBTQ23 and Q24 are turned off and on in period 1, IGBTQ21 and Q22 are alternately turned on, IGBTQ21 and Q22 are turned off and on in period 2, and IGBTQ23 and Q24 are alternately turned on.

In the 1 st period, if IGBTQ21 is turned on, a positive voltage is output from the direct current line L1 to the output node 72a via IGBTQ 11. Further, if IGBTQ22 is turned on, output node 72a is connected to dc line L2 via diode D24 and IGBTQ22, and dc line L2 is connected to output node 72a via diode D22 and IGBTQ24, and output node 72a is set to the neutral point voltage. Thus, in the 1 st period, a positive voltage and a neutral point voltage are alternately output to the output node 72 a.

In the 2 nd period, if IGBTQ23 is turned on, the output node 72a is connected to the dc line L2 via IGBTQ23, and the output node 72a is set to a negative voltage. Further, if IGBTQ24 is turned on, dc line L2 is connected to output node 72a via diode D22 and IGBTQ24, and output node 72a is connected to dc line L2 via diode D24 and IGBTQ22, and output node 72a is set to the neutral point voltage. Thus, in the 2 nd period, a negative voltage and a neutral point voltage are alternately output to the output node 72 a.

Here, a problem of the inverter 73 will be described. In the period 1, when switching is made from the state where IGBTQ21 is on to the state where IGBTQ22 is on, if IGBTQ22 is on although IGBTQ21 is not yet in the off state, an overcurrent flows from the positive terminal (dc line L1) of the capacitor 9a to the negative terminal (dc line L2) of the capacitor 9a via IGBTQ21, diode D24, and IGBTQ22, and IGBTQ21, diode D24, and IGBTQ22 are broken.

In contrast, when switching from the on state of IGBTQ22 to the on state of IGBTQ21, if IGBTQ21 is on although IGBTQ22 has not yet become the off state, an overcurrent flows from the positive terminal (dc line L1) of capacitor 9a to the negative terminal (dc line L2) of capacitor 9a via IGBTQ21, diode D24, and IGBTQ22, and IGBTQ21, diode D24, and IGBTQ22 are broken. IGBTQ24 and Q23 also have the same problems as IGBTQ21 and Q22. Embodiment 2 solves this problem.

Fig. 16 is a circuit block diagram showing a configuration of an inverter control unit 80 that controls the inverter 73. In fig. 16, the inverter control unit 80 includes a voltage command unit 81, triangular wave generators 82 and 83, comparators 84 and 85, buffers 86 and 87, inverters 88 and 89, and gate drive circuits 90 and 91.

The voltage command unit 81 generates a sinusoidal voltage command value Vor based on the instantaneous value of the ac output voltage Vo appearing at the node N2 (fig. 15) and the output signal Iof of the current detector 11 (fig. 15). The phase of the voltage command value Vor is synchronized with the phase of the ac input voltage Vi of the corresponding phase (here, U-phase) among the three phases (U-phase, V-phase, W-phase).

The triangular wave generator 82 outputs a triangular wave signal Cu1a of a frequency fH (e.g., 20KHz) sufficiently higher than a commercial frequency (e.g., 60 Hz). The triangular wave generator 83 outputs a triangular wave signal Cu1b having the same phase and the same frequency fH as the triangular wave signal Cu1 a.

The comparator 84 compares the voltage command value Vor from the voltage command unit 81 with the triangular wave signal Cu1a from the triangular wave generator 82, and outputs a PWM signal Φ 1 indicating the comparison result. The buffer 86 gives the PWM signal Φ 1 to the gate drive circuit 90. The inverter 88 inverts the PWM signal Φ 1 to generate a PWM signal Φ 2, which is supplied to the gate drive circuit 90.

The comparator 85 compares the voltage command value Vor from the voltage command unit 81 with the triangular wave signal Cu1b from the triangular wave generator 83, and outputs a PWM signal Φ 3 indicating the comparison result. The buffer 87 gives the PWM signal Φ 3 to the gate drive circuit 91. The inverter 89 inverts the PWM signal Φ 3 to generate a PWM signal Φ 4, and outputs the PWM signal Φ 4 to the gate drive circuit 91.

FIG. 17 is a timing chart showing waveforms of the voltage command value Vor, the triangular wave signals Cu1a, Cu1b, and the PWM signals φ 1 to φ 4 shown in FIG. 16. In fig. 17, (a) shows waveforms of the voltage command value Vor and the triangular wave signals Cu1a and Cu1B, and (B), (C), (D), and (E) respectively show waveforms of the PWM signals Φ 1, Φ 3, Φ 4, and Φ 2.

As shown in fig. 17 (a), the voltage command value Vor is a sine wave signal of a commercial frequency. The lowest value of the triangular wave signal Cu1a is 0V, and the highest value thereof is higher than the positive peak value of the voltage command value Vor. The maximum value of the triangular wave signal Cu1b is 0V, and the minimum value thereof is lower than the negative peak value of the voltage command value Vor. The triangular wave signals Cu1a and Cu1b are signals having the same phase, and the phases of the triangular wave signals Cu1a and Cu1b are synchronized with the phase of the voltage command value Vor. The triangular wave signals Cu1a and Cu1b have a frequency higher than the frequency of the voltage command value Vor (commercial frequency).

As shown in fig. 17 a and 17B, when the level of the triangular wave signal Cu1a is higher than the voltage command value Vor (time t0 to t1, t2 to t3, t4 to t9, …), the PWM signal Φ 1 is at the "L" level. On the other hand, when the level of the triangular wave signal Cu1a is lower than the voltage command value Vor (times t1 to t2, t3 to t4, and …), the PWM signal Φ 1 becomes "H" level. The PWM signal φ 1 is a positive pulse signal train.

In the 1 st period in which the voltage command value Vor is positive, if the voltage command value Vor rises, the pulse width of the PWM signal Φ 1 increases. In the 2 nd period in which the voltage command value Vor is negative, the PWM signal Φ 1 is fixed to the "L" level. As shown in fig. 17 (B) and 17 (E), the PWM signal Φ 2 is an inverted signal of the PWM signal Φ 1.

Here, if the PWM signals Φ 1, Φ 2 set at the "H" level are set to the 1 st and 2 nd control signals, respectively, the 1 st and 2 nd control signals are alternately output as shown in fig. 17 (B) and 17 (E). The voltage command unit 81, the triangular wave generator 82, the comparator 84, the buffer 86, and the inverter 88 constitute a 1 st control circuit that alternately outputs 1 st and 2 nd control signals.

As shown in fig. 17 a and 17C, when the level of the triangular wave signal Cu1b is lower than the voltage command value Vor (time t0 to t5, t6 to t7, …), the PWM signal Φ 3 is at the "L" level. On the other hand, when the level of the triangular wave signal Cu1b is higher than the voltage command value Vor (times t5 to t6, t7 to t8, and …), the PWM signal Φ 3 is at the "H" level. The PWM signal φ 3 is a positive pulse signal train.

In the 1 st period in which the voltage command value Vor is positive, the PWM signal Φ 3 is fixed to the "L" level. In the 2 nd period in which the voltage command value Vor is negative, if the voltage command value Vor decreases, the pulse width of the PWM signal Φ 3 increases. As shown in fig. 17 (C) and 17 (D), the PWM signal Φ 4 is an inverted signal of the PWM signal Φ 3.

Here, if the PWM signals Φ 3, Φ 4 set at the "H" level are set as the 3 rd and 4 th control signals, respectively, the 3 rd and 4 th control signals are alternately output as shown in fig. 17 (C) and 17 (D). The voltage command unit 81, the triangular wave generator 83, the comparator 85, the buffer 87, and the inverter 89 constitute a 2 nd control circuit that alternately outputs the 3 rd and 4 th control signals.

As shown in fig. 17 (B) to 17 (E), if the waveforms of the PWM signals Φ 1 to Φ 4 change, the ac output voltage Vo having the same waveform as the voltage command value Vor shown in fig. 17 (a) is output between the node N2 and the neutral point NP. Note that, although the waveforms of the voltage command value Vor and the signals Cu1a, Cu1b, Φ 1 to Φ 4 corresponding to U are shown in fig. 17 (a) to 17 (E), the waveforms of the voltage command value Vor and the signals corresponding to V-phase and W-phase are also the same. However, the voltage command values and the phases of the signals corresponding to the U-phase, the V-phase, and the W are shifted by 120 degrees, respectively.

Returning to fig. 16, the gate driving circuit 90 generates gate driving signals VG21, VG22 for turning IGBTQ21, Q22 on and off based on the PWM signals Φ 1, Φ 2 and collector-emitter voltages V21, V22 of IGBTQ21, Q22.

If the gate drive signal VG21 is placed at the "H" level of the activation level, IGBTQ21 turns on. If IGBTQ21 is turned on, the collector-emitter voltage V21 of IGBTQ21 becomes the minimum value V21L. If the gate drive signal VG21 is placed at the "L" level, which is an inactive level, IGBTQ21 turns off. If IGBTQ21 is turned off, collector-emitter voltage V21 of IGBTQ21 becomes maximum V21H. A predetermined threshold voltage VTH21 is set between V21L and V21H.

If the gate drive signal VG22 is placed at the "H" level of the activation level, IGBTQ22 turns on. If IGBTQ22 is turned on, the collector-emitter voltage V22 of IGBTQ22 becomes the minimum value V22L. If the gate drive signal VG22 is placed at the "L" level, which is an inactive level, IGBTQ22 turns off. If IGBTQ22 is turned off, the collector-emitter voltage V22 of IGBTQ22 becomes the maximum value V22H. A predetermined threshold voltage VTH22 is set between V22L and V22H.

When IGBTQ21 is turned on, when PWM signal Φ 1 decreases from "H" level to "L" level and PWM signal Φ 2 increases from "L" level to "H" level, gate drive circuit 90 sets gate drive signal VG21 at "L" level, which is a non-active level, compares the level of collector-emitter voltage V21 of IGBTQ21 with the level of threshold voltage VTH21, determines that IGBTQ21 is in an off state when V21 exceeds VTH21, sets gate drive signal VG22 at "H" level, which is an active level, and turns on IGBTQ 22.

When IGBTQ22 is on, when PWM signal Φ 1 rises from the "L" level to the "H" level and PWM signal Φ 2 falls from the "H" level to the "L" level, gate drive circuit 90 sets gate drive signal VG22 to the "L" level, which is the inactive level, compares the level of collector-emitter voltage V22 of IGBTQ22 with that of threshold voltage VTH22, and when V22 exceeds VTH22, determines that IGBTQ22 is in the off state, sets gate drive signal VG21 to the "H" level, which is the active level, and turns on IGBTQ 21.

Further, the gate drive circuit 91 generates gate drive signals VG23 and VG24 for turning on and off IGBTQ23 and Q24 based on the PWM signals Φ 3 and Φ 4 and collector-emitter voltages V23 and V24 of IGBTQ23 and Q24.

If the gate drive signal VG23 is placed at the "H" level of the activation level, IGBTQ23 turns on. If IGBTQ23 is turned on, the collector-emitter voltage V23 of IGBTQ23 becomes the minimum value V23L. If the gate drive signal VG23 is placed at the "L" level, which is an inactive level, IGBTQ23 turns off. If IGBTQ23 is turned off, collector-emitter voltage V3 of IGBTQ23 becomes maximum V23H. A predetermined threshold voltage VTH23 is set between V23L and V23H.

If the gate drive signal VG24 is placed at the "H" level of the activation level, IGBTQ24 turns on. If IGBTQ24 is turned on, the collector-emitter voltage V24 of IGBTQ24 becomes the minimum value V24L. If the gate drive signal VG24 is placed at the "L" level, which is an inactive level, IGBTQ24 turns off. If IGBTQ24 is turned off, the collector-emitter voltage V24 of IGBTQ24 becomes the maximum value V24H. A predetermined threshold voltage VTH24 is set between V24L and V24H.

When IGBTQ23 is turned on, when PWM signal Φ 3 decreases from "H" level to "L" level and PWM signal Φ 4 increases from "L" level to "H" level, gate drive circuit 91 sets gate drive signal VG23 at "L" level, which is a non-active level, compares the level of collector-emitter voltage V23 of IGBTQ23 with the level of threshold voltage VTH23, determines that IGBTQ23 is in an off state when V23 exceeds VTH23, sets gate drive signal VG24 at "H" level, which is an active level, and turns on IGBTQ 24.

When IGBTQ24 is on, when PWM signal Φ 3 rises from the "L" level to the "H" level and PWM signal Φ 4 falls from the "H" level to the "L" level, gate drive circuit 91 sets gate drive signal VG24 to the "L" level which is the inactive level, compares the level of collector-emitter voltage V24 of IGBTQ24 with that of threshold voltage VTH24, determines that IGBTQ24 is in the off state when V24 exceeds VTH24, sets gate drive signal VG23 to the "H" level which is the active level, and turns on IGBTQ 23.

The configuration and operation of each of the gate driver circuits 90 and 91 are the same as those of the gate driver circuit 36 (fig. 5) and (fig. 7 and 8), and therefore, the description thereof will not be repeated. Note that, similarly to embodiment 1, when the converter 71 and the inverter 73 have the same configuration as seen from the capacitors 9a and 9b, the converter 71 operates as an inverter after the initial charging of the capacitors 9a and 9b is completed, and a converter control unit that controls the converter 71 is similar to the inverter control unit 80 (fig. 16).

As described above, in embodiment 2, when switching from the on state of IGBTQ21 to the on state of IGBTQ22, the gate drive signal VG21 is set to the inactive level, and the gate drive signal VG22 is set to the active level in accordance with the case where the inter-terminal voltage V21 of IGBTQ21 exceeds the threshold voltage VTH 21. Therefore, since IGBTQ22 is turned on when IGBTQ21 is actually turned off, it is possible to prevent an overcurrent from flowing through IGBTQ21 and Q22, and to improve efficiency. IGBTQ23 and Q24 are also similar to IGBTQ21 and Q22.

Fig. 18 is a circuit block diagram showing a modification of embodiment 2, and is a diagram compared with fig. 15. In this modification, the inverter 73 in fig. 15 is replaced with an inverter 73A. Inverter 73A differs from inverter 73 in that IGBTQ22 and IGBTQ24 are connected in reverse. That is, IGBTQ22 and Q24 have their emitters connected to each other, and IGBTQ22 and Q24 have their collectors connected to output node 72a and dc line L2, respectively. Diodes D22, D24 are connected in anti-parallel with IGBTQ22, Q24, respectively. In this modification, the same effects as those of embodiment 2 can be obtained.

[ embodiment 3]

Fig. 19 is a circuit block diagram showing a main part of an uninterruptible power supply device according to embodiment 3 of the present invention, and is a diagram compared with fig. 15. Referring to fig. 18, the uninterruptible power supply device differs from uninterruptible power supply device 1 according to embodiment 2 in that converter 71 and inverter 73 are replaced with converter 95 and inverter 96, respectively.

In fig. 15, in a normal state where ac power is supplied from commercial ac power supply 21, inverter 95 converts ac power from commercial ac power supply 21 into dc power and supplies the dc power to dc lines L1 to L3. At this time, the inverter 95 charges the capacitors 9a and 9b so that the dc voltage VDCa between the dc lines L1 and L2 becomes the reference voltage VDCr and the dc voltage VDCb between the dc lines L2 and L3 becomes the reference voltage VDCr.

The voltages of the dc lines L1, L2, and L3 are set to a positive dc voltage (+ VDCr), a neutral point voltage (0V), and a negative dc voltage (-VDCr), respectively. In a power failure in which the supply of ac power from commercial ac power supply 21 is stopped, the operation of inverter 95 is stopped.

In a normal state, inverter 96 converts the dc power generated by converter 95 into ac power of a commercial frequency, and supplies the ac power to load 24. At this time, inverter 96 generates ac output voltage Vo at a commercial frequency based on the positive dc voltage, the neutral point voltage, and the negative dc voltage supplied from dc lines L1 to L3.

Inverter 96 includes IGBTQ 31-Q34 and diodes D31-D36. The collector of IGBTQ31 (the 1 st switching element) is connected to dc line L1 (the 1 st dc terminal), the emitter of IGBTQ31 is connected to the collector of IGTBQ34 (the 4 th switching element), and the emitter of IGBTQ34 is connected to output node 96a (the ac terminal). The collector of IGBTQ32 (the 2 nd switching element) is connected to output node 96a, the emitter of IGBTQ32 is connected to the collector of IGTBQ33 (the 3 rd switching element), and the emitter of IGBTQ33 is connected to dc line L2.

Diodes D31 to D34 are connected in anti-parallel to IGBTQ31 to Q34, respectively. The diode D35 (1 st diode) has an anode connected to the emitter of IGBTQ32 and a cathode connected to the dc line L2. The diode D36 (the 2 nd diode) has an anode connected to the dc line L2 and a cathode connected to the collector of the IGBTQ 34.

In inverter 96, IGBTQ33 and Q34 are turned off and on in period 1, IGBTQ31 and Q32 are alternately turned on, IGBTQ31 and Q32 are turned off and on in period 2, and IGBTQ33 and Q34 are alternately turned on.

In the 1 st period, if IGBTQ31 is turned on, a positive voltage is output from the direct current line L1 to the output node 96a via IGBTQ31, 34. Further, if IGBTQ32 is turned on, output node 96a is connected to dc line L2 via IGBTQ32 and diode D35, and dc line L2 is connected to output node 96a via diode D36 and IGBTQ34, and output node 96a is set to the neutral point voltage. Thus, in the 1 st period, a positive voltage and a neutral point voltage are alternately output to the output node 96 a.

In the 2 nd period, if IGBTQ33 is turned on, the output node 96a is connected to the dc line L3 via IGBTQ32 and Q33, and the output node 96a is set to a negative voltage. Further, if IGBTQ34 is turned on, dc line L2 is connected to output node 96a via diode D36 and IGBTQ34, and output node 96a is connected to dc line L2 via IGBTQ32 and diode D35, and output node 96a is set to the neutral point voltage. Thus, in the 2 nd period, a negative voltage and a neutral point voltage are alternately output to the output node 96 a.

Here, a problem of the inverter 96 will be explained. In the period 1, when switching is made from the state where IGBTQ31 is on to the state where IGBTQ32 is on, if IGBTQ32 is on although IGBTQ31 is not in the off state yet, an overcurrent flows from the positive terminal (dc line L1) of the capacitor 9a to the negative terminal (dc line L2) of the capacitor 9a via IGBTQ31, Q34, Q32, and the diode D35, and IGBTQ31, Q34, Q32, and the diode D35 are broken.

In contrast, when switching from the on state of IGBTQ32 to the on state of IGBTQ31, if IGBTQ31 is on although IGBTQ32 has not yet become the off state, an overcurrent flows from the positive terminal (dc line L1) of capacitor 9a to the negative terminal (dc line L2) of capacitor 9a via IGBTQ31, Q34, Q32, and diode D35, and IGBTQ31, Q34, Q32, and diode D35 break down. IGBTQ34 and Q33 also have the same problems as IGBTQ31 and Q32. Embodiment 2 solves this problem.

Fig. 20 is a circuit block diagram showing a configuration of an inverter control unit 97 that controls the inverter 96, and is a diagram compared with fig. 16. Referring to fig. 20, inverter control unit 97 differs from inverter control unit 80 of fig. 16 in that gate drive circuits 90 and 91 are replaced with gate drive circuits 98 and 99, respectively. Waveforms of the voltage command value Vor, the triangular wave signals Cu1a, Cu1b, and the PWM signals Φ 1 to Φ 4 are as shown in fig. 17.

The gate drive circuit 98 generates gate drive signals VG31 and VG32 for turning on and off IGBTQ31 and Q32 based on the PWM signals Φ 1and Φ 2 and collector-emitter voltages V31 and V32 of IGBTQ31 and Q32.

If the gate drive signal VG31 is placed at the "H" level of the activation level, IGBTQ31 turns on. If IGBTQ31 is turned on, the collector-emitter voltage V31 of IGBTQ31 becomes the minimum value V31L. If the gate drive signal VG31 is placed at the "L" level, which is an inactive level, IGBTQ31 turns off. If IGBTQ31 is turned off, the collector-emitter voltage V31 of IGBTQ31 becomes the maximum value V31H. A predetermined threshold voltage VTH31 is set between V31L and V31H.

If the gate drive signal VG32 is placed at the "H" level of the activation level, IGBTQ32 turns on. If IGBTQ32 is turned on, the collector-emitter voltage V32 of IGBTQ32 becomes the minimum value V32L. If the gate drive signal VG32 is placed at the "L" level, which is an inactive level, IGBTQ32 turns off. If IGBTQ32 is turned off, the collector-emitter voltage V32 of IGBTQ32 becomes the maximum value V32H. A predetermined threshold voltage VTH22 is set between V32L and V32H.

When IGBTQ31 is turned on, when PWM signal Φ 1 decreases from "H" level to "L" level and PWM signal Φ 2 increases from "L" level to "H" level, gate drive circuit 98 sets gate drive signal VG31 at "L" level, which is a non-active level, compares the level of collector-emitter voltage V31 of IGBTQ31 with that of threshold voltage VTH31, and determines that IGBTQ31 is in an off state when V31 exceeds VTH31, sets gate drive signal VG32 at "H" level, which is an active level, and turns on IGBTQ 32.

When IGBTQ32 is on, when PWM signal Φ 1 rises from the "L" level to the "H" level and PWM signal Φ 2 falls from the "H" level to the "L" level, gate drive circuit 98 sets gate drive signal VG32 to the "L" level which is the inactive level, compares the level of collector-emitter voltage V32 of IGBTQ32 with that of threshold voltage VTH32, determines that IGBTQ32 is in the off state when V32 exceeds VTH32, sets gate drive signal VG31 to the "H" level which is the active level, and turns on IGBTQ 31.

Further, the gate drive circuit 99 generates gate drive signals VG33 and VG34 for turning on and off IGBTQ33 and Q34 based on the PWM signals Φ 3 and Φ 4 and collector-emitter voltages V33 and V34 of IGBTQ33 and Q34.

If the gate drive signal VG33 is placed at the "H" level of the activation level, IGBTQ33 turns on. If IGBTQ33 is turned on, the collector-emitter voltage V33 of IGBTQ33 becomes the minimum value V33L. If the gate drive signal VG33 is placed at the "L" level, which is an inactive level, IGBTQ33 turns off. If IGBTQ33 is turned off, collector-emitter voltage V33 of IGBTQ33 becomes maximum V33H. A predetermined threshold voltage VTH33 is set between V33L and V33H.

If the gate drive signal VG34 is placed at the "H" level of the activation level, IGBTQ34 turns on. If IGBTQ34 is turned on, the collector-emitter voltage V34 of IGBTQ34 becomes the minimum value V34L. If the gate drive signal VG34 is placed at the "L" level, which is an inactive level, IGBTQ34 turns off. If IGBTQ34 is turned off, the collector-emitter voltage V34 of IGBTQ34 becomes the maximum value V34H. A predetermined threshold voltage VTH34 is set between V34L and V34H.

When IGBTQ33 is turned on, when PWM signal Φ 3 decreases from "H" level to "L" level and PWM signal Φ 4 increases from "L" level to "H" level, gate drive circuit 99 sets gate drive signal VG33 to "L" level, which is a non-active level, compares the level of collector-emitter voltage V33 of IGBTQ33 with that of threshold voltage VTH33, determines that IGBTQ33 is in an off state when V33 exceeds VTH33, sets gate drive signal VG34 to "H" level, which is an active level, and turns on IGBTQ 34.

When IGBTQ34 is on, when PWM signal Φ 3 rises from the "L" level to the "H" level and PWM signal Φ 4 falls from the "H" level to the "L" level, gate drive circuit 99 sets gate drive signal VG34 to the "L" level, which is the inactive level, compares the level of collector-emitter voltage V34 of IGBTQ34 with that of threshold voltage VTH34, determines that IGBTQ34 is in the off state when V34 exceeds VTH34, sets gate drive signal VG33 to the "H" level, which is the active level, and turns on IGBTQ 33.

The configuration and operation of the gate driver circuits 98 and 99 are the same as those of the gate driver circuit 36 (fig. 5) and (fig. 7 and 8), and therefore, the description thereof will not be repeated. Note that, similarly to embodiment 1, the converter 95 and the inverter 96 have the same configuration when viewed from the capacitors 9a and 9b, and after the initial charging of the capacitors 9a and 9b is completed, the converter 95 operates as an inverter, and a converter control unit that controls the converter 95 is similar to the inverter control unit 97 (fig. 20).

As described above, in embodiment 3, when switching from the on state of IGBTQ31 to the on state of IGBTQ32, the gate drive signal VG31 is set to the inactive level, and the gate drive signal VG32 is set to the active level in accordance with the case where the inter-terminal voltage V31 of IGBTQ31 exceeds the threshold voltage VTH 31. Thus, IGBTQ32 is turned on when IGBTQ31 is actually turned off, so that an overcurrent can be prevented from flowing in IGBTQ31, Q32, and an improvement in efficiency can be achieved. IGBTQ33 and Q34 are also similar to IGBTQ31 and Q32.

The embodiments disclosed herein are illustrative in all respects and should not be considered as limiting. The present invention is defined by the claims rather than the above description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Description of the reference symbols

1. 70 an uninterruptible power supply device; t1 ac input terminal; t2 bypasses the input terminal; t3 battery terminals; t4 ac output terminal; 2. 8, 14, 16 electromagnetic contactors; 3. 11 a current detector; 4. 9, 9a, 9b, 13 capacitors; 5. 12 a reactor; 6. 71, 95 converters; 7. 72a bidirectional chopper; 10. 73, 96 inverters; 15 a semiconductor switch; 17 an operation section; 18 a control device; 21 a commercial alternating current power supply; 22 bypass an alternating current power supply; 23 batteries; a 24 load; Q1-Q4, Q11-Q14, Q21-Q24 and Q31-Q34 IGBT; diodes D1-D4, D11-D14, D21-D24 and D31-D36; 30. 80, 97 inverter control unit; 31. 61, 81 voltage command section; 32. 62, 82, 83 triangular wave generators; 33. 43, 44, 63, 84, 85 comparators; 34. 64, 86, 87 buffers; 35. 52, 65, 88, 89 inverters; 36. 36A, 36B, 37, 66, 67, 90, 91, 98, 99 gate drive circuits; 41. 42 a voltage detector; 45. 45A, 46A delay circuits; 47. 48, 51AND gates; 49. 50 drivers.