阅读说明：本技术 一种基于转印技术的平面隧穿场效应晶体管及其制备方法 (Planar tunneling field effect transistor based on transfer printing technology and preparation method thereof ) 是由 吕红亮 李苗 朱翊 吕智军 芦宾 张玉明 于 2019-10-14 设计创作，主要内容包括：本发明涉及一种基于转印技术的平面隧穿场效应晶体管及其制备方法，该制备方法包括步骤：在第一衬底(101)的一端制备漏区(104)，在所述第一衬底(101)的另一端制备源区(105)；利用外延层转印技术在所述第一衬底(101)上制备InGaAs沟道层(108)，使所述InGaAs沟道层(108)覆盖所述漏区(104)并且与所述源区(105)部分交叠；在所述InGaAs沟道层(108)上生长栅氧化层(109)。该制备方法将外延层转印技术制备InGaAs沟道层与器件的结构相结合，形成的隧穿场效应晶体管为平面结构，有利于实现器件对准、电极隔离和器件互联，有利于实现高性能的异质集成系统。(The invention relates to a planar tunneling field effect transistor based on a transfer printing technology and a preparation method thereof, wherein the preparation method comprises the following steps: preparing a drain region (104) at one end of a first substrate (101), and preparing a source region (105) at the other end of the first substrate (101); preparing an InGaAs channel layer (108) on the first substrate (101) by using an epitaxial layer transfer technology, wherein the InGaAs channel layer (108) covers the drain region (104) and partially overlaps with the source region (105); and growing a gate oxide layer (109) on the InGaAs channel layer (108). The preparation method combines the InGaAs channel layer prepared by the epitaxial layer transfer printing technology with the structure of a device, and the formed tunneling field effect transistor is of a planar structure, so that the device alignment, the electrode isolation and the device interconnection are favorably realized, and a high-performance heterogeneous integrated system is favorably realized.)

1. A preparation method of a planar tunneling field effect transistor based on a transfer printing technology is characterized by comprising the following steps:

preparing a drain region (104) at one end of a first substrate (101), and preparing a source region (105) at the other end of the first substrate (101);

preparing an InGaAs channel layer (108) on the first substrate (101) by using an epitaxial layer transfer technology, wherein the InGaAs channel layer (108) covers the drain region (104) and partially overlaps with the source region (105);

and growing a gate oxide layer (109) on the InGaAs channel layer (108).

2. The method for preparing a planar tunneling field effect transistor based on a transfer printing technology according to claim 1, wherein a drain region (104) is prepared at one end of a first substrate (101), and a source region (105) is prepared at the other end of the first substrate (101), and the method comprises the following steps:

growing a pad oxide layer (102) on the first substrate (101);

growing a nitride layer (103) on the underlying oxide layer (102).

3. The method for preparing a planar tunneling field effect transistor based on a transfer printing technology according to claim 2, wherein preparing a drain region (104) at one end of a first substrate (101) and preparing a source region (105) at the other end of the first substrate (101) comprises:

etching the nitride layer (103) and the pad oxide layer (102) to form a first ion implantation region (106) on one end surface of the first substrate (101);

performing ion implantation on the first substrate (101) in the first ion implantation area (106) to form a drain area (104);

etching the nitride layer (103) and the pad oxide layer (102), and forming a second ion implantation region (107) on the surface of the other end of the first substrate (101);

and carrying out ion implantation on the first substrate (101) in the second ion implantation area (107) to form a source area (105).

4. The transfer printing technology-based method for fabricating a planar tunneling field effect transistor according to claim 1, wherein the fabricating the InGaAs channel layer (108) on the first substrate (101) by using an epitaxial layer transfer printing technology comprises:

growing an InP sacrificial layer (202) on a second substrate (201);

growing an InGaAs channel layer (108) on the InP sacrificial layer (202);

separating the InGaAs channel layer (108) from the InP sacrificial layer (202), the second substrate (201);

placing the InGaAs channel layer (108) on the first substrate (101).

5. The method for manufacturing a planar tunneling field effect transistor (tffet) based on a transfer printing technique according to claim 4, wherein the separating the InGaAs channel layer (108) from the InP sacrificial layer (202) and the second substrate (201) comprises:

etching the InGaAs channel layer (108), and forming a plurality of grooves (203) on the InGaAs channel layer (108);

selectively etching the InP sacrificial layer (202) through the trenches (203) to reduce a contact area of the InGaAs channel layer (108) and the InP sacrificial layer (202);

adhering the InGaAs channel layer (108) with a flexible stamp adhesive stamp (204) to separate the InGaAs channel layer (108) from the InP sacrificial layer (202), the second substrate (201).

6. The method for manufacturing a planar tunneling field effect transistor based on a transfer printing technique according to claim 5, wherein the placing of the InGaAs channel layer (108) on the first substrate (101) comprises:

transfer placing the InGaAs channel layer (108) adhered to the flexible stamp adhesive stamp (204) on the first substrate (101);

-bonding said InGaAs channel layer (108) and said first substrate (101);

removing the flexible seal adhesive seal (204).

7. The method for preparing a planar tunneling field effect transistor (FEET) based on a transfer printing technology as claimed in claim 1, wherein the thickness of the InGaAs channel layer (108) is 5-20 nm.

8. The method for preparing a planar tunneling field effect transistor based on a transfer printing technology according to claim 1, wherein the thickness of the gate oxide layer (109) is 1-5 nm.

9. The method for preparing a planar tunneling field effect transistor (tffet) based on a transfer printing technique according to claim 1, further comprising, after growing a gate oxide layer (109) on the InGaAs channel layer (108):

-depositing an insulating layer (110) on said gate oxide layer (109);

preparing a source electrode (111), a grid electrode (113) and a drain electrode (112) in the insulating layer (110), wherein the source electrode (111) is positioned on the source region (105), the drain electrode (112) is positioned on the InGaAs channel layer (108) and is positioned above the drain region (104), and the grid electrode (113) is positioned above the grid oxide layer (109).

10. A planar tunneling field effect transistor based on a transfer printing technology is characterized by being prepared by the preparation method of any one of claims 1-9.

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a planar tunneling field effect transistor based on a transfer printing technology and a preparation method thereof.

Background

With the continuous reduction of the size of the traditional Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the integration level of the chip is effectively improved, but the problem of power consumption is more and more prominent. First, the sub-threshold swing of the MOSFET device is limited to 60mV/dec, controlled by the drift diffusion transport mechanism, and lowering the supply voltage becomes more challenging due to the exponential increase in sub-threshold leakage. Secondly, the short channel effect has an increasingly severe effect on the device, significantly increasing leakage current. Tunneling Field Effect Transistors (TFETs) are a particularly promising solution that can break the theoretical limit of the sub-threshold swing of MOSFETs, making the sub-threshold swing below 60 mV/dec. And, different from the operating principle of the MOSFET, the TFET can effectively avoid all short channel effects of the small-sized MOSFET device based on the band-to-band tunneling operating mechanism.

In recent years, people have widely explored the potential application prospect of the tunneling field effect transistor as ultra-low power consumption. The choice of TFET material is very wide, such as Si, Ge, InAs, InGaAs, etc. Compared with Si materials, III-V materials have narrower band gaps and larger effective masses, have higher tunneling probability and can realize larger tunneling current. Therefore, a Heterojunction Tunneling Field Effect Transistor (HTFET) is considered to be more advantageous in achieving a high on-current.

However, currently, HTFETs mostly employ vertical nanowire structures. However, the process flow of the vertical nanowire structure is incompatible with the traditional process, the device alignment, the electrode isolation, the interconnection and the like are complicated, and a heterogeneous integrated system with higher performance is difficult to realize; on the other hand, the conduction current of the HTFET of the vertical nanowire structure cannot be controlled by improving the device structure parameters, which is not favorable for the flexible requirements of actual circuit design.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a planar tunneling field effect transistor based on a transfer printing technology and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:

the embodiment of the invention provides a preparation method of a planar tunneling field effect transistor based on a transfer printing technology, which comprises the following steps:

preparing a drain region at one end of a first substrate, and preparing a source region at the other end of the first substrate;

preparing an InGaAs channel layer on the first substrate by using an epitaxial layer transfer printing technology, wherein the InGaAs channel layer covers the drain region and partially overlaps with the source region;

and growing a gate oxide layer on the InGaAs channel layer.

In one embodiment of the present invention, a method of fabricating a drain region at one end of a first substrate and a source region at the other end of the first substrate, comprises:

growing a bedding oxide layer on the first substrate;

and growing a nitride layer on the underlying oxide layer.

In one embodiment of the present invention, preparing a drain region at one end of a first substrate and a source region at the other end of the first substrate includes:

etching the nitride layer and the bottom oxide layer, and forming a first ion implantation area on one end surface of the first substrate;

performing ion implantation on the first substrate in the first ion implantation area to form a drain region;

etching the nitride layer and the bottom oxide layer, and forming a second ion implantation area on the surface of the other end of the first substrate;

and carrying out ion implantation on the first substrate in the second ion implantation area to form a source area.

In one embodiment of the invention, the preparation of the InGaAs channel layer on the first substrate by using an epitaxial layer transfer technology comprises the following steps:

growing an InP sacrificial layer on the second substrate;

growing an InGaAs channel layer on the InP sacrificial layer;

separating the InGaAs channel layer from the InP sacrificial layer and the second substrate;

and placing the InGaAs channel layer on the first substrate.

In one embodiment of the invention, separating the InGaAs channel layer from the InP sacrificial layer and the second substrate includes:

etching the InGaAs channel layer, and forming a plurality of grooves on the InGaAs channel layer;

selectively etching the InP sacrificial layer through a plurality of grooves to reduce the contact area of the InGaAs channel layer and the InP sacrificial layer;

adhering the InGaAs channel layer with a flexible stamp to separate the InGaAs channel layer from the InP sacrificial layer, the second substrate.

In one embodiment of the invention, placing the InGaAs channel layer on the first substrate comprises:

transferring and placing the InGaAs channel layer adhered on the flexible seal adhesive seal on the first substrate;

bonding the InGaAs channel layer and the first substrate;

and removing the flexible seal sticking seal.

In one embodiment of the invention, the thickness of the InGaAs channel layer is 5-20 nm.

In one embodiment of the invention, the thickness of the gate oxide layer is 1-5 nm.

In an embodiment of the present invention, after growing a gate oxide layer on the InGaAs channel layer, the method further includes:

depositing an insulating layer on the gate oxide layer;

and preparing a source electrode, a grid electrode and a drain electrode in the insulating layer, wherein the source electrode is positioned on the source region, the drain electrode is positioned on the InGaAs channel layer and above the drain region, and the grid electrode is positioned above the grid oxide layer.

Another embodiment of the present invention provides a planar tunneling field effect transistor based on a transfer printing technology, which is manufactured by the manufacturing method as described in the above embodiments.

Compared with the prior art, the invention has the beneficial effects that:

1. according to the preparation method, the InGaAs channel layer prepared by the epitaxial layer transfer printing technology is combined with the structure of the device, and the formed tunneling field effect transistor is of a planar structure, so that the device alignment, the electrode isolation and the device interconnection are favorably realized, and a high-performance heterogeneous integrated system is favorably realized.

2. The preparation method adopts the epitaxial layer transfer printing technology to prepare the InGaAs channel layer on the first substrate, can avoid the extension of interface defects to the InGaAs channel layer, prevent the degradation of the film quality of the InGaAs channel layer, can relieve the mismatch of thermal expansion coefficients to a certain extent, and reduce the density of the interface defects, thereby inhibiting the trap-assisted tunneling and further improving the subthreshold swing of the device from the process angle.

3. According to the planar heterojunction tunneling field effect transistor, the InGaAs channel layer covers the drain region and is partially overlapped with the source region, on one hand, the electron tunneling direction of the planar heterojunction tunneling field effect transistor points to the InGaAs channel layer from the source region, the electron effective tunneling area can be liberated from the interface of a narrow source, channel and gate, the effective tunneling area of the transistor can be increased, the on-state current of the device can be improved, a steeper switching curve can be obtained, and the sub-threshold swing of the device can be improved; on the other hand, the on-state current of the device can be regulated and controlled by regulating and controlling the overlapping length of the InGaAs channel layer and the source region, and the flexibility of circuit design is improved.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a planar tunneling field effect transistor based on a transfer printing technology according to an embodiment of the present invention;

fig. 2a to fig. 2i are schematic diagrams illustrating a method for manufacturing a planar tunneling field effect transistor based on a transfer printing technology according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating an InGaAs channel layer formed by an epitaxial layer transfer technique according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a planar tunneling field effect transistor based on a transfer printing technology according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.