Forming self-aligned gate and source/drain contacts and resulting devices
阅读说明:本技术 形成自对准栅极及源/漏接触以及所得装置 (Forming self-aligned gate and source/drain contacts and resulting devices ) 是由 朱利安·弗罗吉尔 谢瑞龙 朴灿柔 程慷果 于 2019-07-15 设计创作,主要内容包括:本发明涉及形成自对准栅极及源/漏接触以及所得装置,其中,一种方法包括:形成主动层;在该主动层的沟道区上方形成栅极结构;邻近该栅极结构形成侧间隙壁;邻近该侧间隙壁形成第一介电层;凹入该栅极结构以界定栅极空腔;在该栅极空腔中形成内间隙壁;在该栅极空腔中形成覆盖层;凹入该第一介电层及该侧间隙壁,以暴露该覆盖层的侧壁表面;移除该内间隙壁,以界定第一间隙壁空腔;在该间隙壁空腔中并接触该覆盖层的侧壁表面形成上间隙壁;在该上间隙壁及该覆盖层上方形成第二介电层;以及形成至少部分嵌入该第二介电层中并接触该上间隙壁的表面的第一接触结构。(The invention relates to forming self-aligned gate and source/drain contacts and resulting devices, wherein a method comprises: forming an active layer; forming a gate structure over the channel region of the active layer; forming a side spacer adjacent to the gate structure; forming a first dielectric layer adjacent to the sidewall spacers; recessing the gate structure to define a gate cavity; forming an inner spacer in the gate cavity; forming a capping layer in the gate cavity; recessing the first dielectric layer and the sidewall spacers to expose sidewall surfaces of the capping layer; removing the inner spacer to define a first spacer cavity; forming an upper spacer in the spacer cavity and contacting a sidewall surface of the capping layer; forming a second dielectric layer over the upper spacer and the capping layer; and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.)
1. An apparatus, comprising:
an active layer;
a gate structure located over the channel region of the active layer;
a side spacer located adjacent to the gate structure;
a capping layer over the gate structure;
an upper spacer contacting a sidewall surface of the capping layer and a portion of an upper surface of the gate structure;
a second dielectric layer over the top spacer and the capping layer; and
and a first contact structure at least partially embedded in the second dielectric layer and contacting the surface of the upper spacer.
2. The apparatus of claim 1, further comprising:
a source/drain region in the active layer adjacent to the side spacer; and
and a lower source/drain contact structure contacting the source/drain region, wherein the first contact structure contacts the outer surface of the upper spacer and the lower source/drain contact structure.
3. The device of claim 1, wherein the first contact structure contacts an inner surface of the upper spacer and the gate structure.
4. The apparatus of claim 1, wherein the side spacer includes an air gap defined therein.
5. A method, comprising:
forming an active layer;
forming a gate structure over the channel region of the active layer;
forming a side spacer adjacent to the gate structure;
forming a first dielectric layer adjacent to the sidewall spacers;
recessing the gate structure to define a gate cavity;
forming an inner spacer in the gate cavity;
forming a capping layer in the gate cavity adjacent to the inner spacer;
recessing the first dielectric layer and the sidewall spacers to expose sidewall surfaces of the capping layer;
removing the inner spacer to define a first spacer cavity adjacent to the capping layer;
forming an upper spacer in the spacer cavity and contacting a sidewall surface of the capping layer;
forming a second dielectric layer over the upper spacer and the capping layer; and
a first contact structure is formed at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.
6. The method of claim 5, further comprising:
forming source/drain regions in the active layer adjacent to the side spacers;
forming a lower source/drain contact structure contacting the source/drain region;
removing a first portion of the second dielectric layer to expose the lower source/drain contact structure and an outer surface of the upper spacer and define a first contact cavity; and
forming the first contact structure in the first contact cavity, the first contact structure contacting the outer surface of the upper spacer and the lower source/drain contact structure.
7. The method of claim 6, further comprising:
removing a second portion of the second dielectric layer to expose the capping layer;
removing the capping layer to expose an inner surface of the upper spacer and the gate structure, thereby defining a second contact cavity; and
a second contact structure is formed in the second contact cavity, the second contact structure contacting the inner surface of the upper spacer and the gate structure.
8. The method of claim 5, further comprising:
removing a first portion of the second dielectric layer to expose the capping layer;
removing the capping layer to expose an inner surface of the upper spacer and the gate structure, thereby defining a first contact cavity; and
forming the first contact structure in the first contact cavity, the first contact structure contacting the inner surface of the upper spacer and the gate structure.
9. The method of claim 5, further comprising:
removing the side spacers before removing the inner spacers to define a lower spacer cavity; and
a dielectric material is formed in at least an upper portion of the lower spacer cavity to define an air gap in the lower spacer cavity adjacent the gate structure.
10. The method of claim 9, wherein said dielectric material lines said lower spacer cavity.
11. The method of claim 9, further comprising:
forming source/drain regions in the fin adjacent to the side spacers;
forming a lower source/drain contact structure contacting the source/drain region;
removing a first portion of the second dielectric layer to expose the lower source/drain contact structure and an outer surface of the upper spacer and define a first contact cavity; and
forming the first contact structure in the first contact cavity, the first contact structure contacting the outer surface of the upper spacer and the lower source/drain contact structure.
12. The method of claim 11, further comprising:
forming an intermediate source/drain contact structure over the lower source/drain contact structure, the intermediate source/drain contact structure exposing an upper portion of the side spacer;
removing the side spacers after forming the intermediate source/drain contact structure; and
the first contact structure is formed to contact the intermediate source/drain contact structure.
13. The method of claim 12, wherein the intermediate source/drain contact structure and the first contact structure comprise the same material.
14. A method, comprising:
forming an active layer;
forming a gate structure over the channel region of the active layer;
forming a side spacer adjacent to the gate structure;
forming source/drain regions in the active layer adjacent to the side spacers;
forming a first dielectric layer adjacent to the sidewall spacers;
recessing the gate structure to define a gate cavity;
forming an inner spacer in the gate cavity;
forming a capping layer in the gate cavity adjacent to the inner spacer;
recessing the first dielectric layer and the sidewall spacers to expose sidewall surfaces of the capping layer;
forming a source/drain contact structure adjacent to the side spacer and contacting the source/drain region;
removing the side spacer to define a lower spacer cavity;
forming a dielectric material in at least an upper portion of the lower spacer cavity to define an air gap in the lower spacer cavity adjacent the gate structure;
removing the inner spacer to define a first spacer cavity adjacent to the capping layer;
forming an upper spacer in the spacer cavity and contacting a sidewall surface of the capping layer;
forming a second dielectric layer over the upper spacer and the capping layer; and
a first contact structure is formed at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.
15. The method of claim 14, further comprising:
removing a first portion of the second dielectric layer to expose the lower source/drain contact structure and an outer surface of the upper spacer and define a first contact cavity; and
forming the first contact structure in the first contact cavity, the first contact structure contacting the outer surface of the upper spacer and the lower source/drain contact structure.
16. The method of claim 15, further comprising:
removing a second portion of the second dielectric layer to expose the capping layer;
removing the capping layer to expose an inner surface of the upper spacer and the gate structure, thereby defining a second contact cavity; and
a second contact structure is formed in the second contact cavity, the second contact structure contacting the inner surface of the upper spacer and the gate structure.
17. The method of claim 14, further comprising:
removing a first portion of the second dielectric layer to expose the capping layer;
removing the capping layer to expose an inner surface of the upper spacer and the gate structure, thereby defining a first contact cavity; and
forming the first contact structure in the first contact cavity, the first contact structure contacting the inner surface of the upper spacer and the gate structure.
18. The method of claim 14, wherein said dielectric material lines said lower spacer cavity.
19. The method of claim 14, further comprising:
forming an intermediate source/drain contact structure over the lower source/drain contact structure, the intermediate source/drain contact structure exposing an upper portion of the side spacer;
removing the side spacers after forming the intermediate source/drain contact structure; and
the first contact structure is formed to contact the intermediate source/drain contact structure.
20. The method of claim 19, wherein the intermediate source/drain contact structure and the first contact structure comprise the same material.
Technical Field
The present application relates generally to the fabrication of semiconductor devices, and more particularly to a method for forming self-aligned gate and source/drain contacts using sacrificial gate capping spacers (sacrificial gate cap spacers) and the resulting device.
Background
Generally, due to the large number of semiconductor devices (i.e., circuit elements such as transistors, resistors, capacitors, etc.) and the required complex layout in current integrated circuits, the electrical connections or "wiring" of the various semiconductor devices such as transistors, capacitors, etc. cannot be established within the same device level at which they are fabricated. Thus, various electrical connections are formed in a metallization system that includes a plurality of stacked "metallization layers" formed above the device level of the product, which constitute the overall circuit pattern of the Integrated Circuit (IC) product.
For normal operation, for a typical transistor, separate conductive paths are formed for the conductive gate structure, source region, and drain region of the transistor. Part of the process includes forming what are commonly referred to as device level contacts, i.e., a plurality of so-called "CA contact" structures for establishing electrical connection with the source/drain regions of the transistor device, and a gate contact structure (sometimes referred to as a "CB contact" structure) for establishing electrical connection with the gate structure of the transistor device. The CB gate contact is typically located vertically above the isolation material surrounding the transistor device, i.e., the CB gate contact is typically not located above the active region, but in some advanced architectures it may be located above the active region.
The CB gate contact is typically located over an isolation region to avoid or reduce the probability of forming an electrical short between the CB gate contact and a conductive source/drain structure (e.g., a Trench Silicide (TS) structure) formed in the source/drain region of the transistor adjacent to the gate structure of the transistor. Typically, there are also design rules that dictate the minimum spacing that must be maintained between the CB gate contact and the conductive source/drain structure in an attempt to prevent such electrical shorts. Unfortunately, there is an area penalty associated with the requirement that the CB gate contact be located only over the isolation region. Furthermore, an insulating material (typically in the form of at least side spacers) is located between the gate structure and the conductive source/drain structures located on opposite sides of the gate structure. The spacers are typically made of silicon nitride having a relatively high k value, e.g., about 7-8. Due to this physical configuration of the transistor, a gate-to-contact (gate-to-contact) capacitor is defined, wherein the gate electrode serves as a conductive plate of the capacitor, the conductive source/drain structure serves as another conductive plate of the capacitor, and a spacer is located between the two conductive plates. This gate-contact capacitor is parasitic in nature because it must be charged and discharged each time the transistor device is turned on (on) and off (off), all of which results in delaying the switching speed of the device.
The present application provides various methods and resulting devices that can avoid, or at least reduce, the effects of one or more of the above-described problems.
Disclosure of Invention
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
The present application relates generally to various methods of forming self-aligned gate and source/drain contacts using a sacrificial gate overlying a spacer, and the resulting devices. An example apparatus includes: among other things, an active layer, a gate structure over a channel region of the active layer, a side spacer adjacent the gate structure, a capping layer over the gate structure, an upper spacer (upper spacer) contacting a sidewall surface of the capping layer and a portion of an upper surface of the gate structure, a second dielectric layer over the upper spacer and the capping layer, and a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.
An example method includes: forming, among other things, an active layer; forming a gate structure over the channel region of the active layer; forming a side spacer adjacent to the gate structure; forming a first dielectric layer adjacent to the sidewall spacers; recessing the gate structure to define a gate cavity (cavity); forming an inner spacer in the gate cavity; and forming a capping layer in the gate cavity adjacent to the inner spacer. The method further comprises the following steps: recessing the first dielectric layer and the sidewall spacers to expose sidewall surfaces of the capping layer; removing the inner spacer to define a first spacer cavity adjacent to the capping layer; forming an upper spacer in the spacer cavity and contacting a sidewall surface of the capping layer; forming a second dielectric layer over the upper spacer and the capping layer; and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.
Another example method includes: forming, among other things, an active layer; forming a gate structure over the channel region of the active layer; forming a side spacer adjacent to the gate structure; forming source/drain regions in the active layer adjacent to the side spacers; forming a first dielectric layer adjacent to the sidewall spacers; recessing the gate structure to define a gate cavity; forming an inner spacer in the gate cavity; and forming a capping layer in the gate cavity adjacent to the inner spacer. The method further comprises the following steps: recessing the first dielectric layer and the sidewall spacers to expose sidewall surfaces of the capping layer; forming a source/drain contact structure adjacent to the side spacer and contacting the source/drain region; removing the side spacer to define a lower spacer cavity (lower spacer cavity); forming a dielectric material in at least an upper portion of the lower spacer cavity to define an air gap in the lower spacer cavity adjacent the gate structure; removing the inner spacer to define a first spacer cavity adjacent to the capping layer; forming an upper spacer in the spacer cavity and contacting a sidewall surface of the capping layer; forming a second dielectric layer over the upper spacer and the capping layer; and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.
Drawings
The present application may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
FIGS. 1A-1J illustrate various methods for forming self-aligned gate and source/drain contacts using sacrificial gate capping spacers and the resulting devices disclosed herein; and
figures 2A-2E show various methods for forming self-aligned gate and source/drain contacts using sacrificial gate overlying spacer walls, and the resulting devices disclosed herein.
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Detailed Description
Various exemplary embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The inventive subject matter will now be described with reference to the drawings. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present application with details that are well known to those skilled in the art, but are nevertheless included to explain and explain examples of the present application. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present application relates generally to various methods and resulting devices for forming self-aligned gate and source/drain contacts using a sacrificial gate overlying a spacer. After a complete reading of the present application, it will be readily apparent to those skilled in the art that the present method can be used in a variety of devices including, but not limited to, logic devices, memory devices, and the like. Various exemplary embodiments of the methods and apparatus disclosed herein will now be described in more detail with reference to the accompanying drawings.
Fig. 1A-1J illustrate various methods for forming self-aligned gate and source/drain contacts in a
The
Fig. 1B shows the
Fig. 1C shows the
Fig. 1D shows
Fig. 1E shows
FIG. 1F shows the
Figure 1G shows the
Fig. 1H shows a top view of the
Fig. 1I and 1J show the
Fig. 2A-2E show an alternative embodiment of a method for using the air gap
Fig. 2B shows the
Figure 2C shows the
The fabrication process of the
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps described above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. It is noted that various processes or structures such as "first," "second," and the like, which are used in this specification and the appended claims, are illustrative only,
The use of the terms "third" or "fourth" etc. are merely used as a quick reference to such steps/structures and do not necessarily imply that such steps/structures are performed/formed in an ordered sequence. Of course, depending on the exact claim language, an order of such processes may or may not be required. The invention is, therefore, claimed as set forth in the appended claims.
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