阅读说明：本技术 一种感测电路及其读取结果的方法 (Sensing circuit and method for reading result thereof ) 是由 唐原 徐仁泰 于 2019-11-06 设计创作，主要内容包括：本发明公开了一种感测电路及其读取结果的方法，该感测电路能够消除存储单元中的电荷泵噪声。所述感测电路包括多个级联晶体管，该多个级联晶体管包括：闪存单元；感测节点；以及MOSFET。该感测电路还包括用于生成输出电压的电荷泵。所述电荷泵的第一输出电压在读取操作中与所述MOSFET的栅极连接，以将该MOSFET偏置。感测放大器的输入端与所述感测节点连接，以在所述MOSFET偏置后接收所述闪存单元的读取数据。所述电荷泵第一输出电压和所述MOSFET之间连有低通滤波器。(The invention discloses a sensing circuit and a method for reading a result thereof, wherein the sensing circuit can eliminate charge pump noise in a storage unit. The sensing circuit includes a plurality of cascode transistors including: a flash memory unit; a sensing node; and a MOSFET. The sensing circuit also includes a charge pump for generating the output voltage. A first output voltage of the charge pump is connected to the gate of the MOSFET to bias the MOSFET during a read operation. An input of a sense amplifier is connected to the sense node to receive read data of the flash memory cell after the MOSFET is biased. And a low-pass filter is connected between the first output voltage of the charge pump and the MOSFET.)

1. A sensing circuit for generating a read result of data stored in a memory cell, the sensing circuit comprising:

a plurality of cascode transistors connected between a power supply and a ground, the plurality of cascode transistors comprising:

a flash memory unit;

a sensing node; and

a metal-oxide semiconductor field effect transistor connected between the sensing node and the flash memory cell;

a charge pump for generating an output voltage, wherein a first output voltage of the charge pump is connected to a gate of the metal-oxide semiconductor field effect transistor in a read operation of the flash memory cell to bias the metal-oxide semiconductor field effect transistor; and

and the low-pass filter is connected between the first output voltage of the charge pump and the grid electrode of the metal-oxide semiconductor field effect transistor.

2. The sensing circuit of claim 1, wherein the second output voltage of the charge pump is directly input to the plurality of cascode transistors in a program operation of the flash memory cell.

3. The sensing circuit of claim 1, further comprising a sense amplifier having an input connected to the sensing node to receive read data of the flash memory cell after the metal-oxide semiconductor field effect transistor is biased and to generate a read result by amplifying and outputting the read data.

4. The sensing circuit of claim 2, further comprising a first switch connected between the second output voltage and the plurality of cascode transistors, and a second switch connected between the first output voltage and the plurality of cascode transistors.

5. The sensing circuit of claim 4, wherein the plurality of cascode transistors further comprises:

a data bit line node; and

the node of the inverted data bit line is,

wherein the metal-oxide semiconductor field effect transistor is connected between the inverted data bit line node and the data bit line node; the first switch is turned on to bias the data bit line node in a program operation of the flash memory cell, and the second switch is turned on to bias the metal-oxide semiconductor field effect transistor in a read operation of the flash memory cell to transfer a value of the data bit line node to the inverted data bit line node and the sensing node.

6. The sensing circuit of claim 1, wherein the low pass filter comprises:

a transistor, a source of the transistor is connected with the first output voltage of the charge pump, a drain of the transistor is connected with a gate of the metal-oxide semiconductor field effect transistor, and the gate of the transistor is grounded; and

a decoupling capacitor connected between the drain of the transistor and ground.

7. A method for generating read results for data stored in a memory cell, the method comprising:

connecting a plurality of cascode transistors between a power supply and a ground, the plurality of cascode transistors comprising:

a flash memory unit;

a sensing node; and

a metal-oxide semiconductor field effect transistor connected between the sensing node and the flash memory cell;

generating a first voltage in a read operation of the flash memory cell;

low pass filtering the first voltage;

inputting the low-pass filtered first voltage to a gate of the metal-oxide semiconductor field effect transistor to bias the metal-oxide semiconductor field effect transistor; and

and receiving the read data of the flash memory unit.

8. The method of claim 7, wherein in a programming operation of the flash memory cell, the method comprises:

generating a second voltage; and

the second voltage is directly input to the plurality of cascode transistors.

9. The method of claim 8, wherein the plurality of cascode transistors further comprises:

a data bit line node; and

an inverted data bit line node is provided,

wherein the metal-oxide semiconductor field effect transistor is connected between the inverted data bit line node connection and the data bit line node, the method further comprising:

inputting the second voltage to a first switch in a program operation of the flash memory cell,

turning on the first switch to directly input the second voltage to the data bit line node, an

Biasing the data bit line node to save a value of the flash memory; and inputting the voltage after low-pass filtering to a second switch in a read operation of the flash memory cell,

turning on the second switch to input the low-pass filtered voltage to the gate of the metal-oxide semiconductor field effect transistor, an

Biasing the metal-oxide semiconductor field effect transistor with the low pass filtered voltage to pass the value of the data bit line node to the inverted data bit line node and the sense node.

10. The method of claim 7, wherein in a programming operation of the flash memory cell, the method comprises: and amplifying and outputting the read data to generate a read result.

Technical Field

The present invention relates to sensing circuits, and more particularly, to a sensing circuit that cancels noise in the output of a charge pump.

Background

Sense amplifiers are an integral part of the sensing circuitry used in computer memory. The sensing circuit compares the reference current with the current drawn by the memory cell. The voltage is high or low according to whether the current drawn by the memory cell is greater than or less than the reference current. Wherein if the resulting voltage is high, a "0" is read, indicating that the memory cell has been programmed; if the resulting voltage is low, a "1" is read, indicating that the memory cell is erased. The sense amplifier generates a read result by amplifying the sensed voltage.

A conventional sensing circuit is composed of a plurality of transistors connected between a power supply VDD and a ground terminal and a sense amplifier connected to a sensing node. The voltage generated by the charge pump is delivered directly to the plurality of transistors to enable the sensing circuit to perform a current comparison, allowing the resulting voltage to be sensed by the sense node and subsequently amplified and output by the sense amplifier.

The amount of current drawn by a memory cell depends on the threshold voltage of the memory cell. The charge pump provides a bias voltage to the memory cell when the memory cell is programmed. When the voltage on the memory cell is high, it indicates that the current drawn by the memory cell is less than the reference current provided by the first transistor connected to VDD. At this time, the voltage on the sensing node is at a high level representing "0", thereby achieving programming of the memory cell. In a read operation, the voltage provided by the charge pump is so high that all of the plurality of transistors are turned on. Thus, the current drawn by the memory cell is higher than the reference current by being lower than the memory cell threshold voltage, causing the voltage of the sense node to be a low level representing a "1", indicating that the memory cell is erased. Thus, the sense amplifier can output the result value of the sensing node as the read result.

It can be seen that the sense node is extremely sensitive to voltage level variations. As is well known, charge pumps have a clock input and have a feedback path for adjusting the strength of the charge pump. When the output intensity of the charge pump is not high enough compared with the reference value, the input clock increases the cycle frequency of the charge pump to charge the charge pump. When the intensity of the charge pump is higher than the reference value, the input clock is suspended to stop the charging of the charge pump. The combined action of this regulation mechanism and the variable clock period causes fluctuations in the output of the charge pump, and the resulting charge pump output noise may have an effect on the voltage at the sense node, resulting in erroneous readings.

Disclosure of Invention

In view of the above, it is an object of the present invention to provide a sensing circuit including a low pass filter for preventing fluctuations in the output of a charge pump.

According to an example embodiment of the present invention, a sensing circuit includes a plurality of cascode transistors connected between a power supply and a ground terminal, the plurality of cascode transistors including: a flash memory unit; a sensing node; and a MOSFET connected between the sensing node and the flash memory cell. The sensing circuit further includes: a charge pump for generating an output voltage, wherein a first output voltage of the charge pump is connected to the gate of the MOSFET in a read operation of the flash memory cell to bias the MOSFET, and a second output voltage of the charge pump is directly input to the plurality of cascode transistors in a program operation of the flash memory cell; and a low pass filter connected between the first output voltage of the charge pump and the gate of the MOSFET. The low-pass filter includes: a transistor having a source connected to the first output voltage of the charge pump, a drain connected to the gate of the MOSFET, and a gate connected to ground; and a decoupling capacitor connected between the drain of the transistor and a ground terminal.

A first switch is connected between the first output voltage and the plurality of cascade transistors, and a second switch is connected between the second output voltage and the plurality of cascade transistors. The plurality of cascode transistors further includes: a data bit line node; and a reverse data bit line node, wherein the MOSFET is connected between the reverse data bit line node and the data bit line node. In a program operation of the flash memory cell, the first switch is turned on to bias the data bit line node; and in a read operation of the flash memory cell, the second switch is turned on to bias the MOSFET to pass the value of the data bit line node to the inverted data bit line node.

According to an exemplary embodiment of the present invention, a method of generating read results for data stored in a memory cell comprises: connecting a plurality of cascode transistors between a power supply and a ground terminal, the plurality of cascode transistors comprising: a flash memory unit; a sensing node; and a MOSFET connected between the sensing node and the flash memory cell. The method further comprises the following steps: generating a first voltage in a read operation of the flash memory cell; low pass filtering the first voltage; inputting the low-pass filtered first voltage to a gate of the MOSFET to bias the MOSFET; and receiving read data of the flash memory unit.

In a program operation of the flash memory cell, the method includes: generating a second voltage; and directly inputting the second voltage to the plurality of cascode transistors.

The plurality of cascode transistors further includes: a data bit line node; and an inverted data bit line node. The MOSFET is connected between the inverted data bit line node and the data bit line node, and the method further comprises: in a program operation of the flash memory cell, inputting the second voltage to a first switch, turning on the first switch to directly input the second voltage to the data bit line node, and biasing the data bit line node to save a value of the flash memory; in a read operation of the flash memory cell, the low-pass filtered voltage is input to a second switch, the second switch is turned on to input the low-pass filtered voltage to the gate of the MOSFET, and the MOSFET is biased with the low-pass filtered voltage to pass the value of the data bit line node to the inverted data bit line node and the sense node.

The above and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment, which is illustrated in the accompanying drawings.

Drawings

FIG. 1 illustrates a sensing circuit according to an exemplary embodiment of the invention.

Fig. 2A shows the charge pump output with and without a low pass filter.

Fig. 2B shows the low pass filter of fig. 1.

Detailed Description

As described above, the sensing circuit receives the voltage of the charge pump, wherein in a memory cell programming operation, a data value is preserved by providing a bias voltage to the sensing circuit; in a read operation, a read result representing a stored data value is generated by providing a greater voltage.

Because the charge pump requires a clock input and regulation, there is ripple/noise in the charge pump output that may affect the accuracy of the sense amplifier read results. Accordingly, the present invention provides a low pass filter coupled to the output of a charge pump that smoothes fluctuations in the output voltage signal of the charge pump.

Referring to FIG. 1, a sensing circuit 100 according to an exemplary embodiment of the invention is shown. As shown, the sensing circuit 100 includes a VPPD charge pump 110 that generates an output VPDD. The output is transmitted via a first switch to a node DBL in a plurality of interconnected transistors having a cascaded topology. The output of charge pump 110 is also transmitted to low pass filter 120, which is used to transmit output VPPDSHF to the gate of transistor N0 via a second switch. The first transistor in the series of interconnected transistors has its drain connected to a supply voltage VDD and its gate connected to a reference voltage SPREF. The second transistor in the series of interconnected transistors has its source connected to node iDBL and its gate connected to cascode amplifier 130, where node iDBL is further input to cascode amplifier 130. The last transistor in the series of interconnected transistors is a flash memory cell having a gate connected to a word line and a source connected to ground. Furthermore, a sense node SO is present between the first and second transistors, wherein the sense node SO is connected to the input of the sense amplifier 140. The sense amplifier 140 is used to generate a read result.

The output of the low pass filter is connected to the gate of transistor N0 as shown. In a read operation, the gate is biased by signal VPPDSHF, allowing the data signal stored in DBL to pass to iDBL and, in turn, to sense node SO. In this manner, sense amplifier 140 may generate read results that are not affected by fluctuations.

In a programming operation, a logical bit "0" or "1" is input to the flash memory cell via the wordline, and the output of the charge pump VPPD enables the value of the logical bit to be stored in the flash memory cell by biasing node DBL. Although there are still fluctuations in signal VPPD due to the absence of a low pass filter between VPPD and node DBL, node DBL is not overly sensitive to noise. Furthermore, during the programming operation, the bias of the DBL requires a sufficiently high current, and the low-pass filter has a high impedance, which affects the input of the current, so that the low-pass filter cannot be inserted there.

Under the influence of the N0 drain-to-gate capacitance, if the charge pump output is applied directly to the N0 gate, noise in the output will couple with node iDBL, which will also pass to the sense node. By placing a low pass filter 120 between the charge pump output and node iDBL, all noise during the read operation can be filtered out.

Referring to fig. 2A, the charge pump output is shown without a low pass filter and with a low pass filter. As shown, when there is a ripple in the charge pump output VPPD, the ripple may cause a ripple on node iDBL and sense node SO as well. After the low-pass filter is added, the noise becomes smooth, so that a stable signal is obtained to ensure a correct reading result.

Fig. 2B shows a low pass filter 120. As shown, the low pass filter 120 includes an input connected to the source of a transistor whose gate is connected to ground. The drain of the transistor is connected to a decoupling capacitor and to the output of the low pass filter 120. The decoupling capacitor is connected to ground and the transistor acts as a resistor. In a read operation, the output of the low pass filter 120 is used to bias the N0 gate. Since the gate does not conduct any current, no voltage drop occurs across the resistor in the low pass filter 120.

The circuit described above is easy to implement, since the low-pass filter 120 only needs one transistor. Decoupling capacitors have been included in the sensing circuit, as is well known, and can be used in the low pass filter 120. The low pass filter 120 is used only for read operations and does not affect program operations. Therefore, the circuit 100 of the present invention has a simple structure and a high cost performance.

In addition, the sensing circuit can realize programming and low-interference reading signals by modifying the original circuit, the sensing circuit and the sensing circuit are not interfered with each other, the circuit structure is simpler, and the integration level of the system is improved.

It will be readily appreciated by those skilled in the art that various modifications and variations can be made to the above-described apparatus and method within the technical scope of the present invention. Accordingly, the above disclosure should be construed as limited only by the scope and metes of the following claims.