阅读说明：本技术 采用用于校准的脉冲到数字转换器(pdc)的延迟锁定环(dll) (Delay Locked Loop (DLL) using pulse to digital converter (PDC) for calibration ) 是由 E·黑路 B·班迪达 于 2018-06-18 设计创作，主要内容包括：本公开的方面涉及从同相时钟信号生成正交时钟信号。根据一个方面，延迟锁定环(DLL)包括：第一脉冲到数字转换器(PDC)，生成第一脉冲宽度测量，其中第一脉冲宽度测量包括第一符号和第一幅度；第二脉冲到数字转换器(PDC)，生成第二脉冲宽度测量，其中第二脉冲宽度测量包括第二符号和第二幅度；数字环路滤波器，其被耦合到第一PDC和第二PDC，数字环路滤波器基于第一脉冲宽度测量和第二脉冲宽度测量生成经过滤波的比较输出；以及第一延迟生成块，基于经过滤波的比较输出和同相时钟信号生成正交时钟信号。(Aspects of the present disclosure relate to generating a quadrature clock signal from an in-phase clock signal. According to one aspect, a Delay Locked Loop (DLL) includes: a first pulse-to-digital converter (PDC) that generates a first pulse width measurement, wherein the first pulse width measurement includes a first symbol and a first amplitude; a second pulse-to-digital converter (PDC) that generates a second pulse width measurement, wherein the second pulse width measurement includes a second symbol and a second amplitude; a digital loop filter coupled to the first PDC and the second PDC, the digital loop filter generating a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and a first delay generation block that generates a quadrature clock signal based on the filtered comparison output and the in-phase clock signal.)

1. A Delay Locked Loop (DLL), comprising:

a first pulse-to-digital converter, PDC, that generates a first pulse width measurement, wherein the first pulse width measurement comprises a first symbol and a first amplitude;

a second pulse-to-digital converter (PDC) generating a second pulse width measurement, wherein the second pulse width measurement includes a second symbol and a second amplitude;

a digital loop filter coupled to the first PDC and the second PDC, the digital loop filter generating a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and

a first delay generation block that generates a quadrature clock signal based on the filtered comparison output and an in-phase clock signal.

2. The Delay Locked Loop (DLL) of claim 1, further comprising: a divider block that divides the in-phase clock signal by an integer to generate a first masking pulse.

3. The Delay Locked Loop (DLL) of claim 2, wherein said divider block generates a second masking pulse based on said first masking pulse.

4. The Delay Locked Loop (DLL) of claim 3, further comprising: a first set-reset (SR) latch that generates a first latch clock output based on the in-phase clock signal; and a second set-reset (SR) latch that generates a second latch clock output based on the quadrature clock signals.

5. The Delay Locked Loop (DLL) of claim 4, further comprising:

a first AND gate coupled to the first set-reset SR latch to perform a first logical AND operation of the second masking pulse AND the first latch clock output to generate a first clock output, an

A second AND gate coupled to the second set-reset SR latch to perform a second logical AND operation of the first masking pulse AND the second latch clock output to generate a second clock output.

6. The Delay Locked Loop (DLL) of claim 5, wherein said first clock output is input to said first pulse to digital converter (PDC) to generate said first pulse width measurement and said second clock output is input to said second pulse to digital converter (PDC) to generate said second pulse width measurement.

7. The Delay Locked Loop (DLL) of claim 1, wherein said first pulse to digital converter (PDC) comprises a first fractional element and a first integrating element.

8. The Delay Locked Loop (DLL) of claim 7, wherein said first pulse width measurement is a cascade of a first fractional pulse width measurement generated by said first fractional element and a first integrated pulse width measurement generated by said first integrating element.

9. The Delay Locked Loop (DLL) of claim 8, wherein said second pulse to digital converter (PDC) comprises a second fractional element and a second integrating element.

10. The Delay Locked Loop (DLL) of claim 9, wherein said second pulse width measurement is a cascade of a second fractional pulse width measurement generated by said second fractional element and a second integrated pulse width measurement generated by said second integrating element.

11. A method for generating a quadrature clock signal from an in-phase clock signal, comprising:

generating a first pulse width measurement of a first clock output, wherein the first pulse width measurement comprises a first sign and a first magnitude;

generating a second pulse width measurement of a second clock output, wherein the second pulse width measurement comprises a second sign and a second magnitude;

generating a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and

generating the quadrature clock signal based on the in-phase clock signal and the filtered comparison output.

12. The method of claim 11, further comprising: the in-phase clock signal is divided by an integer to generate a first masking pulse and a second masking pulse.

13. The method of claim 12, wherein the integer is greater than or equal to one ("1").

14. The method of claim 12, further comprising: a first latch clock output is generated based on the in-phase clock signal.

15. The method of claim 14, further comprising: performing a first logical AND operation of the second masking pulse AND the first latch clock output to generate the first clock output.

16. The method of claim 15, further comprising: a second latch clock output is generated based on the quadrature clock signals.

17. The method of claim 16, further comprising: performing a second logical AND operation of the first masking pulse AND the second latch clock output to generate the second clock output.

18. The method of claim 17, wherein the first pulse width measurement is a cascade of a first fractional pulse width measurement and a first integrated pulse width measurement.

19. The method of claim 18, wherein the second pulse width measurement is a cascade of a second fractional pulse width measurement and a second integrated pulse width measurement.

20. The method of claim 19, wherein a first pulse-to-digital converter (PDC) is used to generate the first pulse width measurement, the first PDC including a first fractional element that generates the first fractional pulse width measurement and a first integrating element that generates the first integrated pulse width measurement.

21. The method of claim 20, wherein a second pulse-to-digital converter (PDC) is used to generate the second pulse width measurement, the second PDC including a second fractional element that generates the second fractional pulse width measurement and a second integration element that generates the second integrated pulse width measurement.

22. An apparatus for generating a quadrature clock signal from an in-phase clock signal, the apparatus comprising:

means for generating a first pulse width measurement of a first clock output, wherein the first pulse width measurement comprises a first sign and a first magnitude;

means for generating a second pulse width measurement of a second clock output, wherein the second pulse width measurement comprises a second symbol and a second amplitude;

means for generating a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and

means for generating the quadrature clock signal based on the in-phase clock signal and the filtered comparison output.

23. The apparatus of claim 22, further comprising means for dividing the in-phase clock signal by an integer to generate a first masking pulse and a second masking pulse.

24. The apparatus of claim 23, further comprising means for generating a first latched clock output based on the in-phase clock signal.

25. The apparatus of claim 24, further comprising means for performing a first logical AND operation of the second masking pulse AND the first latched clock output to generate the first clock output.

26. The apparatus of claim 25, further comprising means for generating a second latch clock output based on the quadrature clock signals.

27. The apparatus of claim 26, further comprising means for performing a second logical AND operation of the first masking pulse AND the second latching clock output to generate the second clock output.

28. The apparatus of claim 27, wherein the first pulse width measurement is a cascade of a first fractional pulse width measurement and a first integrated pulse width measurement, and the second pulse width measurement is a cascade of a second fractional pulse width measurement and a second integrated pulse width measurement.

29. A computer-readable medium storing computer-executable code operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to generate a quadrature clock signal from an in-phase clock signal, the computer-executable code comprising:

instructions for causing the computer to provide a first pulse width measurement that generates a first clock output, wherein the first pulse width measurement comprises a first sign and a first magnitude;

instructions for causing the computer to provide a second pulse width measurement that generates a second clock output, wherein the second pulse width measurement comprises a second sign and a second magnitude;

instructions for causing the computer to generate a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and

instructions for causing the computer to generate the quadrature clock signal based on the in-phase clock signal and the filtered comparison output.

30. The computer-readable medium of claim 29, further comprising:

instructions for causing the computer to divide the in-phase clock signal by an integer to generate a first masking pulse and a second masking pulse;

instructions for causing the computer to generate a first latch clock output based on the in-phase clock signal and a second latch clock output based on the quadrature clock signal; and

instructions for causing the computer to perform a first logical AND operation of the second masking pulse AND the first latch clock output to generate the first clock output, AND perform a second logical AND operation of the first masking pulse AND the second latch clock output to generate the second clock output.

Technical Field

The present disclosure relates generally to the field of delay locked loops, and more particularly to a delay locked loop for generating a quadrature clock signal from an in-phase clock signal.

Background

Several forms of transducers may be used in electronic circuits to convert one signal in one domain to another signal in another domain. For example, a pulse-to-digital converter (PDC) is an electronic circuit that converts pulse widths (measured in units of time) into a digital representation. Different implementations of the pulse-to-digital converter can be used in different applications. However, some pulse-to-digital converters (PDC) may have a limited linear range and thus limit their practical applications. Reference is made to U.S. patent application No.15/644,285 to Hailu et al, the disclosure of which is incorporated herein by reference.

Disclosure of Invention

The following presents a simplified summary of one or more aspects of the disclosure in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended to neither identify key or critical elements of all aspects of the disclosure, nor delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

In one aspect, the present disclosure provides a Delay Locked Loop (DLL). Accordingly, a Delay Locked Loop (DLL) includes: a first pulse-to-digital converter (PDC) that generates a first pulse width measurement, wherein the first pulse width measurement includes a first symbol and a first amplitude; a second pulse-to-digital converter, PDC, that generates a second pulse width measurement, wherein the second pulse width measurement comprises a second symbol and a second amplitude; a digital loop filter coupled to the first PDC and the second PDC, the digital loop filter generating a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and a first delay generation block that generates a quadrature clock signal based on the filtered comparison output and the in-phase clock signal.

In one example, the Delay Locked Loop (DLL) further includes: a divider block that divides the in-phase clock signal by an integer to generate a first masking pulse, wherein the divider block generates a second masking pulse based on the first masking pulse. The Delay Locked Loop (DLL) may further include: a first set-reset (SR) latch that generates a first latch clock output based on an in-phase clock signal; and a second set-reset (SR) latch that generates a second latch clock output based on the quadrature clock signals. In one example, a Delay Locked Loop (DLL) includes: a first AND gate coupled to the first set-reset (SR) latch to perform a first logical AND operation of the second masking pulse AND the first latch clock output to generate a first clock output; AND a second AND gate coupled to the second set-reset (SR) latch to perform a second logical AND operation of the first masking pulse AND the second latch clock output, thereby generating a second clock output.

In one example, a first clock output is input to a first pulse-to-digital converter (PDC) to generate a first pulse width measurement and a second clock output is input to a second pulse-to-digital converter (PDC) to generate a second pulse width measurement. In one example, a first pulse-to-digital converter (PDC) includes: a first fractional element and a first integral element. The first pulse width measurement is a cascade of a first fractional pulse width measurement generated by a first fractional element and a first integrated pulse width measurement generated by a first integrating element. In one example, a second pulse-to-digital converter (PDC) includes: a second fractional element and a second integral element. The second pulse width measurement is a cascade of a second fractional pulse width measurement generated by a second fractional element and a second integrated pulse width measurement generated by a second integrating element.

Another aspect of the disclosure provides a method for generating a quadrature clock signal from an in-phase clock signal, the method comprising: generating a first pulse width measurement of the first clock output, wherein the first pulse width measurement comprises a first sign and a first magnitude; generating a second pulse width measurement of the second clock output, wherein the second pulse width measurement comprises a second sign and a second magnitude; generating a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and generating a quadrature clock signal based on the in-phase clock signal and the filtered comparison output.

In one example, the method further comprises: the in-phase clock signal is divided by an integer to generate a first masking pulse and a second masking pulse, where the integer is greater than or equal to one ("1"). The method further comprises the following steps: generating a first latch clock output based on the in-phase clock signal; performing a first logical AND operation of the second masking pulse AND the first latch clock output to generate a first clock output; generating a second latch clock output based on the quadrature clock signal; AND performing a second logical AND operation of the first masking pulse AND the second latch clock output to generate a second clock output; wherein the first pulse width measurement is a cascade of a first fractional pulse width measurement and a first integral pulse width measurement; and wherein the second pulse width measurement is a cascade of a second fractional pulse width measurement and a second integrated pulse width measurement.

In one example, a first pulse-to-digital converter (PDC) is used to generate a first pulse width measurement, the first pulse-to-digital converter (PDC) including a first fractional element that generates the first fractional pulse width measurement and a first integral element that generates the first integral pulse width measurement. In one example, a second pulse-to-digital converter (PDC) is used to generate a second pulse width measurement, the second pulse-to-digital converter (PDC) including a second fractional element that generates the second fractional pulse width measurement and a second integral element that generates the second integral pulse width measurement.

Another aspect of the disclosure provides an apparatus for generating a quadrature clock signal from an in-phase clock signal, the apparatus comprising: means for generating a first pulse width measurement of the first clock output, wherein the first pulse width measurement comprises a first sign and a first magnitude; means for generating a second pulse width measurement of the second clock output, wherein the second pulse width measurement comprises a second sign and a second magnitude; means for generating a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and means for generating the quadrature clock signal based on the in-phase clock signal and the filtered comparison output.

The apparatus may also include means for dividing the in-phase clock signal by an integer to generate a first masking pulse and a second masking pulse; means for generating a first latched clock output based on the in-phase clock signal; means for performing a first logical AND operation of a second masking pulse AND a first latched clock output to generate the first clock output; means for generating a second latch clock output based on the quadrature clock signal; means for performing a second logical AND operation of the first masking pulse AND the second latch clock output to generate a second clock output. In one example, the first pulse width measurement is a cascade of a first fractional pulse width measurement and a first integrated pulse width measurement, and the second pulse width measurement is a cascade of a second fractional pulse width measurement and a second integrated pulse width measurement.

Another aspect of the disclosure provides a computer-readable medium storing computer-executable code operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to generate a quadrature clock signal from an in-phase clock signal, the computer-executable code comprising: instructions for causing a computer to provide a first pulse width measurement that generates a first clock output, wherein the first pulse width measurement comprises a first sign and a first magnitude; instructions for causing the computer to provide a second pulse width measurement that generates a second clock output, wherein the second pulse width measurement comprises a second sign and a second magnitude; instructions for causing a computer to generate a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and instructions for causing the computer to generate the quadrature clock signal based on the in-phase clock signal and the filtered comparison output.

In one example, the computer-readable medium further comprises: instructions for causing a computer to divide an in-phase clock signal by an integer to generate a first masking pulse and a second masking pulse; instructions for causing a computer to generate a first latch clock output based on an in-phase clock signal, and instructions for a user to generate a second latch clock output based on a quadrature clock signal; AND instructions for causing the computer to perform a first logical AND operation of the second masking pulse AND the first latch clock output to generate the first clock output, AND to perform a second logical AND operation of the first masking pulse AND the second latch clock output to generate the second clock output.

These and other aspects of the invention will be more fully understood upon reading the following detailed description. Other aspects, features and embodiments of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific exemplary embodiments of the invention in conjunction with the accompanying figures. While features of the invention may be discussed with respect to certain embodiments and figures below, all embodiments of the invention may include one or more of the advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having certain advantageous features, one or more such features may also be used in accordance with the various embodiments of the invention discussed herein. In a similar manner, although example embodiments may be discussed below as apparatus, system, or method embodiments, it should be understood that such example embodiments may be implemented in a variety of apparatus, systems, and methods.

Drawings

Fig. 1 illustrates an example of a Delay Locked Loop (DLL) that includes some analog components for the DLL input section.

Fig. 2 illustrates an example of a Delay Locked Loop (DLL) including a pulse-to-digital converter (PDC) for the DLL input section in accordance with the present disclosure.

Fig. 3 illustrates an example of a digital loop filter according to the present disclosure.

Fig. 4 illustrates an example pulse-to-digital converter (PDC) in accordance with this disclosure.

Fig. 5 illustrates an example of a simulation plot of a first relative time shift of the in-phase clock signal Iclk and the quadrature clock signal Qclk as a function of time, and a second relative time shift of the complementary in-phase clock signal Ibclk and the complementary quadrature clock signal Qbclk as a function of time.

Fig. 6 illustrates an example flow diagram for generating a quadrature clock signal from an in-phase clock signal using a Delay Locked Loop (DLL) that includes a pulse-to-digital converter (PDC) for a DLL input section.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

A pulse-to-digital converter (PDC) may use analog components such as RC filters, comparators, etc. to extract pulse width measurements as inputs to a Delay Locked Loop (DLL) for calibration. However, the use of analog components may not fit well into smaller feature sizes and may limit their operating speed. DLLs that use PDCs with analog components, such as resistor-capacitor (RC) filters and comparators, to extract pulse widths for DLL calibration may encounter large area usage and some limited frequency response. For example, a PDC may have a bandwidth limited to about 20MHz or less. Additionally, the PDC may only provide symbol errors, and not amplitude errors, as part of the delay comparison for DLL calibration, which may result in increased calibration time.

Fig. 1 illustrates an example of a Delay Locked Loop (DLL)100 that includes some analog components for the DLL input section. In one example, a first Set Reset (SR) latch 110 accepts a first set input from an in-phase clock signal Iclk191 and a first reset input from a quadrature clock signal Qclk 192. In one example, the first SR latch 110 is a rising edge triggered SR latch. Next, the first SR latch 110 provides a first latch clock output 115 to the first RC filter 111. Next, the first RC filter 111 provides a first filtered clock output 196 to a first comparator input of the comparator 130. In one example, the second set-reset (SR) latch 120 accepts a second set input from the quadrature clock signal Qclk 192 and a second reset input from the complementary in-phase clock signal Ibclk 193. In one example, the second SR latch 120 is a rising edge triggered SR latch. Next, the second SR latch 120 provides a second latch clock output 125 to the second RC filter 121. Next, the second RC filter 121 provides a second filtered clock output 197 to a second comparator input of the comparator 130.

In one example, the comparator 130 compares the first comparator input with the second comparator input, and the comparator 130 provides a comparator output. In one example, the comparator output is a bi-level signal indicating which comparator input is at a higher level. For example, if the first comparator input is greater than the second comparator input, the comparator output may be set to HIGH, and if the second comparator input is greater than the first comparator input, the comparator output may be set to LOW. In one example, the comparator 130 may be clocked by the input clock signal Fclk 180. For example, the input clock signal Fclk 180 may have a frequency of 20MHz or less. In one example, the comparator output may only indicate sign information of a comparison between the first comparator input and the second comparator input. In another example, the comparator output is sent as an input to the digital loop filter 140. In one example, digital loop filter 140 may be clocked by input clock signal Fclk 180. In one example, digital loop filter 140 filters the comparator output and provides a filtered comparator output 141.

In one example, the filtered comparator output 141 is sent as a first comparison input to the first delay generation unit 150. In one example, the in-phase clock signal Iclk191 is sent as a first reference input to the first delay generation unit 150. The first delay generation unit 150 generates a quadrature clock signal Qclk 192 having a quadrature delay with respect to a first reference input (i.e., the in-phase clock signal Iclk 191). In one example, the quadrature delay is equivalent to a 90 degree phase delay.

In one example, the filtered comparator output 141 is sent as a second comparison input to the second delay generation unit 160. In one example, the complementary in-phase clock signal Ibclk 193 is sent as a second reference input to the second delay generation unit 160. In one example, the second delay generation unit 160 produces a complementary quadrature clock signal Qbclk 194 having a quadrature delay relative to a second reference input (i.e., the complementary in-phase clock signal Ibclk 193). In one example, the quadrature delay is equivalent to a 90 degree phase delay.

The present disclosure relates to pulse-to-digital converters (PDCs), for example for use in Delay Locked Loops (DLLs). In accordance with the present disclosure, a pulse-to-digital converter (PDC) may be used to convert the pulse width (measured in units of time) into a digital representation. For example, a PDC may be used as part of an input compare circuit for tracking waveform delay in a Delay Locked Loop (DLL). A DLL is an electronic circuit that locks one time delay to another time delay through a feedback mechanism. For example, the DLL may be used to generate quadrature (e.g., in-phase and quadrature) clocks for digital interface circuits such as serializer/deserializer applications. In one example, a PDC may be used within a DLL to extract pulse widths for DLL calibration.

In this disclosure, the linear range is defined as the input range of pulse widths with a proportional output range of numbers. The term "proportional" is defined to mean that an incremental change in pulse width causes an incremental change in proportion in the digital representation. As disclosed herein, the implementation of a pulse-to-digital converter (PDC) facilitates extending the linear range of a Delay Locked Loop (DLL).

Fig. 2 illustrates an example of a Delay Locked Loop (DLL)200 including a pulse-to-digital converter (PDC) for the DLL input section in accordance with the present disclosure. In one example, the first set-reset (SR) latch 210 accepts a first set input from the in-phase clock signal Iclk 291, and the first set-reset (SR) latch 210 accepts a first reset input from the quadrature clock signal Qclk 292. In one example, the first SR latch 210 is a rising edge triggered SR latch. Next, the first SR latch 210 may provide a first latch clock output 215 to a first input of an AND gate 211. Next, the first "AND" gate 211 may provide a first clock output 296 to a first pulse-to-digital converter (PDC) 212. The first PDC212 may provide the first digital word 298 as a first input to the digital loop filter 240. In one example, the first digital word 298 provides a first width measurement between the in-phase clock signal Iclk 291 and the quadrature clock signal Qclk 292. In one example, the first width measurement includes both sign and magnitude information.

In one example, the second set-reset (SR) latch 220 accepts a second set input from the quadrature clock signal Qclk 292 and a second reset input from the complementary in-phase clock signal Ibclk 293. In one example, the second SR latch 220 is a rising edge triggered SR latch. Next, the second SR latch 220 may provide a second latch clock output 225 to a first input of a second AND gate 221. Next, the second AND gate 221 may provide a second clock output 297 to the second pulse-to-digital converter (PDC) 222. The second PDC222 may provide the second digital word 299 as a second input to the digital loop filter 240. In one example, the second digital word 299 provides a second width measurement between the quadrature clock signal Qclk 292 and the complementary in-phase clock signal Ibclk 293. In one example, the second width measurement includes both sign and magnitude information.

In one example, the divider block 230 may generate the first masking pulse Imask and the second masking pulse Qmask. In one example, a first input to the divider block 230 is an in-phase clock signal, Iclk 291, and a second input to the divider block 230 is a complementary in-phase clock signal, Ibclk 293. In one example, the divider block 230 generates the first masking pulse Imask by dividing the in-phase clock signal 291 by an integer M to generate the first masking pulse Imask. In one example, the divider block 230 generates the second masking pulse Qmask by shifting the first masking pulse Imask by 90 degrees. In another example, the divider block 230 interpolates the in-phase clock signal Iclk 291 and the complementary in-phase clock Ibclk293 to generate the second masking pulse Qmask.

The first masking pulse Imask may be a second input of the second AND gate 221. The second masking pulse Qmask may be a second input of the first AND gate 211. In one example, the divider block 230 may create a clock Fclk 231 to control how often the first PDC212, the second PDC222, and the digital loop filter 240 process their inputs. In one example, the unit setting of the divider block 230 may allow two PDCs (i.e., the first PDC212 and the second PDC222) and the digital loop filter 240 to operate at a maximum clock rate. In one example, the maximum clock rate results in the shortest calibration time.

In one example, the digital loop filter 240 accepts the first digital word 298 and the second digital word 299 as inputs for comparison. In one example, the digital loop filter 240 produces a filtered comparison output 241. In one example, the filtered comparison output 241 includes both sign and magnitude information for the comparison. Next, the filtered comparison output 241 is sent as a first input to the first delay generation block 250 and the filtered comparison output 241 is sent as a first input to the second delay generation block 260. Additionally, the in-phase clock signal Iclk 291 is sent as a second input to the first delay generation block 250 and the complementary in-phase clock signal Ibclk293 is sent as a second input to the second delay generation block 260. In one example, the quadrature clock signal Qclk 292 is the output of the first delay generation block 250 and the complementary quadrature clock signal Qbclk 294 is the output of the second delay generation block B60. In one example, the quadrature clock signal Qclk 292 is provided to the first set-reset (SR) latch 210 and the second set-reset (SR) latch 220 via a feedback loop 270.

In one example, the first PDC212 and the second PDC222 each create an n-bit digital word (e.g., the first digital word 298 and the second digital word 299) representing a pulse width measurement. That is, the first digital word 298 is a first pulse width measurement and the second digital word 299 is a second pulse width measurement. Next, the digital loop filter 240 accepts the two n-bit digital words and generates a signed k-bit digital control signal (e.g., filtered comparison output 241) for two delay generation blocks (e.g., first delay generation block 250 and second delay generation block 260). In one example, the k-bit digital control signal includes both sign and magnitude information.

Fig. 3 illustrates an example of a digital loop filter 300 according to the present disclosure. In one example, the digital loop filter 300 is implemented as the digital loop filter 240 disclosed in fig. 2. As shown in fig. 3, digital loop filter 300 includes subtractor 310 and integrator/decimator 320. In one example, the subtractor 310 obtains a difference of the first subtractor input in 0301 and the second subtractor input in 1302. The difference is the output of subtractor 310 and is labeled as subtractor output 311. Subtractor output 311 may be used as an input to integrator/decimator 320 (labeled "in fig. 3). In one example, the first subtractor input in 0301 is a first digital word 298 and the second subtractor input in 1302 is a second digital word 299.

In one example, integrator/decimator 320 integrates subtractor output 311 and integrator/decimator 320 decimates subtractor output 311. In one example, integrating subtractor output 311 is defined as averaging subtractor output 311. The averaging may or may not include weighting; i.e. with a weighted average of the subtractor outputs 311. In one example, decimation is defined as reducing the sampling density. That is, in one example, the number of subtractor outputs 311 is reduced based on a desired resolution, which may be determined by a particular application or by a user. In one example, the integrator/decimator 320 operates in synchronization with an input clock signal 322 (labeled "clk" in fig. 3). The output 321 of the integrator/decimator 320 (labeled "out" in fig. 3) is the same as the filtered comparison output 241 (shown in fig. 2).

Fig. 4 illustrates an example pulse-to-digital converter (PDC)400 according to this disclosure. In one example, the pulse-to-digital converter (PDC)400 shown in fig. 4 is used as the two PDCs (i.e., PDC212 and PDC222) shown in fig. 2. In one aspect, the pulse-to-digital converter (PDC)400 includes three features: fractional elements, integral elements and immunity circuits.

As shown in fig. 4, an input pulse signal 411 and an external reset signal ext _ reset 412 are used as inputs to PDC 400. The input pulse signal 411 AND the inverted external reset signal (generated by inverter 413) are sent to a first AND gate 414 to produce a first waveform w 1. In one example, the first waveform w1 is generated as a logical AND operation on the input pulse signal 411 AND the inverted external reset signal. In one example, the first waveform W1 is a pulse waveform having a pulse width W. Next, the first waveform w1 is sent to the first delay element 461 to generate the second waveform w 2. The second waveform w2 is a delayed copy of the first waveform w 1. The time delay between the first waveform w1 and the second waveform w2 is given by T1.

Next, the second waveform w2 is sent to the second delay element 462 to generate a third waveform w 3. In one example, the third waveform w3 is a delayed copy of the second waveform w 2. In one example, the time delay between the second waveform w2 and the third waveform w3 is given by T2. Next, the third waveform w3 is sent to the third delay element 463 to generate a fourth waveform w 4. The fourth waveform w4 is a delayed copy of the third waveform w 3. In one example, the time delay between the third waveform w3 and the fourth waveform w4 is given by T3. In the example of fig. 4, the fourth waveform w4 and the first waveform w1 are input to the OR gate 415. In one example, the OR gate output is the fifth waveform w 5.

As shown in fig. 4, the fifth waveform w5 is input to the gated ring oscillator 420. In one example, the input of the gated ring oscillator 420 is used as the enable signal labeled "en" in FIG. 4. In one example, the gated ring oscillator 420 outputs a first state word a < n:0> 421. In one example, the first state word a < n:0>421 includes (n +1) bits. For example, a first state word a < n:0>421 represents an accumulated count of gated ring oscillator state transitions. In one example, the gated ring oscillator state transition is a state transition of a gated ring oscillator. A state transition is a change of state of a digital electronic circuit. In a digital electronic circuit having two states, the state transition is a transition from LOW to HIGH or HIGH to LOW. In one example, the gated ring oscillator 420 has two states. In one example, when the input of the gated ring oscillator 420 is HIGH (i.e., start-up), the gated ring oscillator 420 has an oscillation period T.

Next, a first state word a < n:0>421 may be used as an input to the first flip-flop 430. In one example, the first flip-flop 430 receives a first waveform w1 being used as the first clock signal c1 and a fourth waveform w4 being used as the first reset signal labeled "rst _ b" in the first flip-flop 430. In one example, the first flip-flop 430 is a falling edge triggered flip-flop. In one example, the first flip-flop output is a second state word b < n:0> 431. In one example, the second state word b < n:0>431 includes (n +1) bits. For example, the second state word b < n:0>431 may represent a latched accumulated count of gated ring oscillator state transitions.

Next, a second state word b < n:0>431 may be used as an input to binary translator 440. The binary converter may convert the phase into thermometer code and then into binary code. In one example, binary translator 440 translates second state word b < n:0>431 into thermometer code and then into binary code. The output of the binary translator 440 is a third state word c < log2(n) -1:0> 441. In one example, the third state word c < log2(n) -1:0>441 includes log2(n) bits. For example, the third state word c < log2(n) -1:0>441 may represent a binary accumulated count of gated ring oscillator state transitions.

Next, a third state word c < log2(n) -1:0>441 may be used as an input to the second flip-flop 450. In one example, the second flip-flop 450 receives the third waveform w3 being used as the second clock signal c2, and the second flip-flop 450 also receives a second reset signal (labeled "ext _ rst" in the second flip-flop 450) from the external reset signal ext _ reset 412. In one example, the second flip-flop 450 is a falling edge triggered flip-flop. In one example, the second flip-flop output is a fourth state word d < log2(n) -1:0> 451. In one example, the fourth state word d < log2(n) -1:0>451 includes log2(n) bits. For example, the fourth state word d < log2(n) -1:0>451 represents a synchronous binary accumulated count of gated ring oscillator state transitions.

In one example, the fractional elements of the pulse-to-digital converter (PDC)400 include: a gated ring oscillator 420, a first flip-flop 430, a binary converter 440, and a second flip-flop 450. For example, the fractional element measures the pulse width of the input pulse signal 411 (as a fraction of the oscillation period T) using an internal interpolation state of the gated ring oscillator state transitions to produce a fractional measurement given by the fourth state word d < log2(n) -1:0> 451. The fractional element provides a fractional pulse width measurement of the input pulse signal 411. In one example, the fractional pulse width measurement provides fine time resolution of the pulse width measurement of the input pulse signal 411. In one example, fine temporal resolution is measured relative to the temporal resolution of a gated ring oscillator without an interpolator.

Additionally, for example, the first state word a < n:0>421 AND the second waveform w2 are input to the second AND gate 416. The second AND gate 416 may generate clock signals as illustrated by a third clock signal c3 AND a fourth clock signal c 4. In one example, the third clock signal c3 and the fourth clock signal c4 are the same clock signal. The third clock signal c3 is used as a clock input to a Most Significant Bit (MSB) counter 470. Additionally, the MSB counter 470 may receive a fourth waveform w4, which is used as a third reset signal labeled "rst _ b" in the MSB counter 470, w 4. In one example, MSB counter 470 output is fifth state word e < k:0> 471. In one example, fifth state word e < k:0>471 includes (k +1) bits. For example, fifth state word e < k:0>471 represents the MSB count of gated ring oscillator MSB transitions. In one example, the MSB transition of the gated ring oscillator is a state change of the Most Significant Bit (MSB) of the first state word a < n:0>421 from a HIGH state to a LOW state.

Since first status word a < n:0>421 is derived from the fractional element of PDC AND since the clock input of MSB counter 470 is derived from first status word a < n:0>421 (via second AND gate 416), the clock input of MSB counter 470 is derived from the fractional element of PDC 400. Thus, there is a coupling between the fractional element and the integral element of PDC400 via third clock signal c 3.

Next, a fifth state word e < k:0>471 is used as an input to third flip-flop 480. In one example, the third flip-flop 480 receives the fourth clock signal c4 from the second AND gate 416, AND the third flip-flop 480 receives a fourth waveform w4, which fourth waveform w4 is used as the fourth reset signal labeled "rst _ b" in the third flip-flop 480. In one example, the third flip-flop 480 is a falling edge triggered flip-flop. In one example, the third flip-flop 480 output is a sixth state word f < k:0> 481. In one example, the sixth state word f < k:0>481 includes (k +1) bits. For example, the sixth state word f < k:0>481 may represent a latched MSB count of gated ring oscillator MSB transitions.

Next, fifth state word e < k:0>471 can be used as a first input to multiplexer 490, and sixth state word f < k:0>481 can be used as a second input to multiplexer 490. The output of the multiplexer 490 may be selected by the multiplexer controller 495. In one example, multiplexer 490 uses comparison logic to select the multiplexer output. In one example, multiplexer controller 495 may use comparison logic to compare fifth state word e < k:0>471 and sixth state word f < k:0>481 to select the output of multiplexer 490. In one example, the multiplexer controller 495 may select the multiplexer output using the following comparison logic:

if(f<k:0>＝e<k:0>)then mux control＝1,or

if(f<k:0>≠e<k:0>)then:

if a<(n+1)/2-1>＝1then mux control＝0or

if a<(n+1)/2-1>＝0then mux control＝1

in this example, mux control 0 selects the output as the second input of multiplexer 490 and mux control 1 selects the output as the first input of multiplexer 490. In addition, in this example, a < (n +1)/2-1> represents the middle bit of the first state word a < n:0>421 having (n +1) bits. For example, if n ═ 7 then the first state word is the intermediate bit a < (n +1)/2-1> ═ a <3 >.

In one example, multiplexer 490 outputs a seventh state word h < k:0> 491. In one example, the seventh state word h < k:0>491 comprises (k +1) bits. For example, the seventh state word h < k:0>491 represents a selected latched MSB count of gated ring oscillator MSB transitions.

Next, a seventh state word h < k:0>491 may be used as an input to the fourth flip-flop 497. In one example, the fourth flip-flop 497 receives the third waveform w3 used as the fifth clock signal c5, and the fourth flip-flop 497 receives the fifth reset signal (labeled "ext _ rst" in the fourth flip-flop) from the external reset signal ext _ reset 412. In one example, the fourth flip-flop 497 is a falling edge triggered flip-flop. In one example, the output of the fourth flip-flop 497 is an eighth state word i < k:0> 498. In one example, eighth state word i < k:0>498 includes (k +1) bits. For example, eighth state word i < k:0>498 represents a synchronized MSB count of gated ring oscillator MSB transitions.

In one example, the integrating element of the pulse-to-digital converter (PDC)400 includes: MSB counter 470, third flip-flop 480, multiplexer 490, and fourth flip-flop 497. MSB counter 470, together with third flip-flop 480, multiplexer 490, and fourth flip-flop 497, provides an increased linear range for pulse width measurements of input pulse signal 411. For example, the integrating element measures the pulse width of input pulse signal 411 as a multiple of oscillation period T using the MSB transitions of the gated ring oscillator state transitions to produce the integration measurement given by eighth state word i < k:0> 498. The integrating element provides an integrated pulse width measurement of the input pulse signal 411. In one example, the integrated pulse width measurement provides a time range of pulse width measurements of the input pulse signal 411 that can be widened by adding a scalable q number of bits to the MSB counter; i.e. a wider time range. In one example, q is an integer.

In one example, the output of the pulse-to-digital converter (PDC)400 may be represented as a cascade of a synchronized MSB count of gated ring oscillator MSB transitions and a synchronized binary accumulated count of gated ring oscillator state transitions. In one example, the output of PDC400 may be represented as { i < k:0>, d < log2(n) -1:0 }, where { x, y } represents a concatenation of a state word x and a state word y. In one example, cascading is joining two ordered elements into one larger single ordered element. In one example, the cascade may be implemented by a cascade of two registers (e.g., two shift registers).

In one example, the immunity circuit 485 of the PDC400 includes: a third flip-flop 480, a multiplexer 490, and a multiplexer controller 495. The immunity circuit synchronizes the input pulse signal 411 with the timing of the gated ring oscillator 420. That is, if more than one counter bit is changing state at the same clock transition, the multiplexer controller 495 compares the current counter state with the previous counter state to disambiguate the counter transition. The immunity circuit 485 takes a monotonic input-output relationship to avoid problems associated with asynchrony between the input pulse signal 411 and the timing of the gated ring oscillator 420. The components of the immunity circuit 485 are shown within the dashed rectangle in fig. 4.

Fig. 5 illustrates a simulation graph 500 of a first relative time shift (in picoseconds) of an in-phase clock signal Iclk (e.g., Iclk 291 shown in fig. 2) and a quadrature clock signal Qclk (e.g., Qclk 292 shown in fig. 2) as a function of time, and a simulation graph 500 of a second relative time shift (in picoseconds) of a complementary in-phase clock signal Ibclk (e.g., Ibclk293 shown in fig. 2) and a complementary quadrature clock signal Qbclk (e.g., Qbclk 294 shown in fig. 2) as a function of time.

In one example, simulation plot 500 shows the results of DLL calibration using a pulse-to-digital converter. For example, a clock signal having a frequency of 3GHz will cause an interval between the in-phase clock signal Iclk and the quadrature clock signal Qclk to be 83 picoseconds. Also, the interval between the complementary in-phase clock signal Iclk and the complementary quadrature clock signal Qclk is 83 picoseconds. In simulation diagram 500, Delay Locked Loop (DLL)200 (as shown in fig. 2) reaches steady state operation in less than 200 nanoseconds. In the simulation diagram 500, the divider block 230 setting is set to 10, and the digital loop filter 240 and the two PDCs 212, 222 each operate at a frequency of 300 MHz.

Fig. 6 illustrates an example flow diagram 600 for generating a quadrature clock signal from an in-phase clock signal using a Delay Locked Loop (DLL) that includes a pulse-to-digital converter (PDC) for the DLL input section. In block 610, an in-phase clock signal is received. In one example, the in-phase clock signal is received by a divider block (e.g., divider block 230 shown in fig. 2).

In block 620, the in-phase clock signal is divided by an integer M to generate a first masking pulse Imask and a second masking pulse Qmask. In one example, a divider block (e.g., divider block 230 shown in fig. 2) divides the in-phase clock signal. In one example, the value of the integer M may be any integer value greater than or equal to one ("1"). For example, the value of integer M may be selected based on device capabilities.

In one example, the divider block generates a first masking pulse Imask by dividing the in-phase clock signal by an integer M, and the divider block generates a second masking pulse Qmask by shifting the first masking pulse Imask by 90 degrees. In another example, a divider block interpolates an in-phase clock signal and a complementary in-phase clock (e.g., Ibclk293 as shown in fig. 2) to generate the second masking pulse Qmask.

In block 630, a first latch clock output is generated based on the in-phase clock signal and a second latch clock output is generated based on the pseudo-quadrature clock signal. In one example, the first latch clock output and the second latch clock output are generated by two set-reset (SR) latches, respectively. The two SR latches may be the SR latches 210, 220 shown in fig. 2. In one example, prior to generating the quadrature clock signal (as described in block 670), the pseudo-quadrature clock signal may be a clock signal having an arbitrary phase relative to the in-phase clock signal. Once the quadrature clock signal (as described in block 670) is generated, the pseudo quadrature clock signal is the quadrature clock signal.

In block 640, a first logical AND operation of the second masking pulse Qmask AND the first latch clock output is performed to generate a first clock output, AND a second logical AND operation of the first masking pulse Imask AND the second latch clock is performed to output to generate a second clock output. In one example, the first AND second logical AND operations are performed by two AND gates (e.g., AND gates 211, 221 shown in fig. 2).

In block 650, generating a first pulse width measurement of the first clock output, wherein the first pulse width measurement comprises a first sign and a first magnitude; and generating a second pulse width measurement of the second clock output, wherein the second pulse width measurement includes a second sign and a second magnitude. In one example, the first and second pulse width measurements are generated by two pulse-to-digital converters (PDCs) (e.g., PDCs 212, 222 shown in fig. 2). In one example, each of the two PDCs includes a fractional element and an integral element. Also, in one example, one or more of the two PDCs includes a jamming immunity circuit.

In one example, the PDC generates a fractional pulse width measurement and an integrated pulse width measurement of the clock output, and the PDC concatenates the fractional pulse width measurement and the integrated pulse width measurement to generate a pulse width measurement with a sign and an amplitude.

In block 660, a filtered comparison output is generated based on the first pulse width measurement and the second pulse width measurement. In one example, the filtered comparison output is generated by a digital loop filter (e.g., digital loop filter 240 shown in fig. 2 and 3). As shown in fig. 3, the digital loop filter may include a subtractor and an integrator/decimator. In one example, a filtered comparison output is generated by taking the difference between the first pulse width measurement and the second pulse width measurement, and then integrating and decimating the difference. In one example, the difference is the subtractor output 311 shown in fig. 3.

In block 670, a quadrature clock signal is generated based on the in-phase clock signal and the filtered comparison output. In one example, the quadrature clock signals are generated by a delay generation block (e.g., the first delay generation block 250 shown in fig. 2). In one example, a complementary quadrature clock signal is also generated based on the complementary in-phase clock signal and the filtered comparison output. In one example, the complementary quadrature clock signals are generated by a delay generation block (e.g., the second delay generation block 260 shown in fig. 2).

In block 680, a quadrature clock signal is provided to replace the pseudo quadrature clock signal in block 630. In one example, the quadrature clock signal is provided to one or more of the two SR latches through a feedback loop (e.g., feedback loop 270 as shown in fig. 2).

In an aspect, one or more of the steps for generating a quadrature clock signal from an in-phase clock signal using a Delay Locked Loop (DLL) in fig. 6, which includes a pulse to digital converter (PDC) for a DLL input section, may be performed by one or more processors (which may include hardware, software, firmware, etc.). In an aspect, one or more of the steps in fig. 6 may be performed by one or more processors, which may include hardware, software, firmware, etc. For example, one or more processors may be used to execute software or firmware required to perform the steps in the flowchart of fig. 14. Software should be interpreted broadly to mean: instructions, instruction sets, code segments, program code, programs, subroutines, software modules, applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, and the like, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside on a computer readable medium. The computer readable medium may be a non-transitory computer readable medium. Non-transitory computer readable media include, for example: magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips), optical disks (e.g., Compact Disk (CD) or Digital Versatile Disk (DVD)), smart cards, flash memory devices (e.g., card, stick or key drive), Random Access Memory (RAM), Read Only Memory (ROM), programmable ROM (prom), erasable prom (eprom), electrically erasable prom (eeprom), registers, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. For example, a computer-readable medium may also include a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. The computer readable medium may reside in a processing system, external to the processing system, or distributed across multiple entities including the processing system. The computer readable medium may be embedded in a computer program product. By way of example, the computer program product may comprise a computer-readable medium in a packaging material. The computer readable medium may include software or firmware for generating a quadrature clock signal from an in-phase clock signal. Depending on the particular application and the overall design constraints imposed on the overall system, those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure.

Any circuitry included in the processor(s) is provided merely as an example, and other means for carrying the described functionality may be included within aspects of the present disclosure, including but not limited to any other suitable means or devices stored in a computer-readable medium or described herein, and utilizing the processes and/or algorithms described herein, e.g., in connection with the example flowcharts.

Within this disclosure, the word "exemplary" is used to define "serving as an example, instance, or illustration. Any implementation or aspect of "exemplary" described herein is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C may be considered to be coupled to each other even if they are not in direct physical contact with each other. For example, a first die may be coupled to a second die in a package even though the first die is never in direct physical contact with the second die. The terms "circuit" and "loop" are used broadly and are intended to include both hardware implementations of both electrical devices and conductors that when connected and configured enable the functions described in this disclosure to be performed without limitation to the type of electronic circuitry, as well as software implementations of information and instructions that when executed by a processor enable the functions described in this disclosure to be performed.

One or more components, steps, features and/or functions illustrated in the drawings may be rearranged and/or combined into a single component, step, feature or function or embedded in several components, steps or functions. Additional elements, components, steps, and/or functions may also be added without departing from the novel features disclosed herein. The apparatus, devices, and/or components illustrated in the figures may be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein may also be usefully implemented in software and/or embedded in hardware.

It should be understood that the specific order or hierarchy of steps in the methods disclosed is an illustration of exemplary processes. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited therein.