阅读说明：本技术 Pll电路 (PLL circuit ) 是由 堤恒次 柳原裕贵 下泽充弘 于 2017-07-04 设计创作，主要内容包括：相位频率比较器(4)对基准信号和可变分频器(3)的输出信号进行比较，输出与比较结果对应的频率的上升信号和下降信号。与门电路(9)进行上升信号与下降信号的逻辑与运算，输出运算结果作为重定时用信号CLKretime。触发器电路(10)在与门电路(9)的输出信号的定时保持频率控制电路(8)的输出信号并进行输出。ΔΣ调制器(7)与触发器电路(10)的输出对应地决定可变分频器(3)的分频比。(A phase frequency comparator (4) compares the reference signal with the output signal of the variable frequency divider (3), and outputs a rising signal and a falling signal of a frequency corresponding to the comparison result. The AND circuit (9) performs a logical AND operation of the up signal and the down signal, and outputs the operation result as a retiming signal CLKRTIME. The flip-flop circuit (10) holds and outputs the output signal of the frequency control circuit (8) at the timing of the output signal of the AND circuit (9). The delta-sigma modulator (7) determines the division ratio of the variable frequency divider (3) in accordance with the output of the flip-flop circuit (10).)

1. A PLL circuit characterized in that a PLL circuit,

the PLL circuit includes:

a voltage-controlled oscillator that outputs a signal of a frequency corresponding to a given frequency control voltage;

a variable divider that divides an output signal of the voltage controlled oscillator corresponding to a signal of a given division ratio;

a phase frequency comparator that compares a reference signal with an output signal of the variable frequency divider and outputs an up signal and a down signal of a frequency corresponding to a comparison result;

an and circuit that outputs a logical and operation result of the rising signal and the falling signal;

a frequency control circuit that operates the reference signal as a clock and outputs a signal corresponding to an output frequency of the voltage-controlled oscillator;

a flip-flop circuit that holds and outputs an output signal of the frequency control circuit at a timing of an output signal of the and circuit;

a delta-sigma modulator that operates the output of the variable frequency divider as a clock, and determines a division ratio of the variable frequency divider in accordance with the output of the flip-flop circuit;

a charge pump that outputs currents corresponding to the rising signal and the falling signal; and

a loop filter that outputs a signal obtained by current-voltage converting and smoothing an output of the charge pump to the voltage-controlled oscillator as the frequency control voltage.

2. A PLL circuit characterized in that a PLL circuit,

the PLL circuit includes:

a voltage-controlled oscillator that outputs a signal of a frequency corresponding to a given frequency control voltage;

a variable divider that divides an output signal of the voltage controlled oscillator corresponding to a signal of a given division ratio;

a phase frequency comparator that compares a reference signal with an output signal of the variable frequency divider and outputs an up signal and a down signal of a frequency corresponding to a comparison result;

a frequency control circuit that operates the reference signal as a clock and outputs a signal corresponding to an output frequency of the voltage-controlled oscillator;

a flip-flop circuit that holds and outputs an output signal of the frequency control circuit at a timing of a reset signal of a flip-flop inside the phase frequency comparator;

a delta-sigma modulator that operates the output of the variable frequency divider as a clock, and determines a division ratio of the variable frequency divider in accordance with the output of the flip-flop circuit;

a charge pump that outputs currents corresponding to the rising signal and the falling signal; and

a loop filter that outputs a signal obtained by current-voltage converting and smoothing an output of the charge pump to the voltage-controlled oscillator as the frequency control voltage.

3. The PLL circuit of claim 2,

the PLL circuit is provided with a 2 nd phase frequency comparator which compares the reference signal with an output signal of the variable frequency divider,

the 2 nd phase frequency comparator has a delay circuit which outputs a reset signal of an internal flip-flop with a pulse width of a set amount of time,

the flip-flop circuit uses the reset signal of the 2 nd phase frequency comparator in place of the reset signal of the phase frequency comparator.

4. A PLL circuit characterized in that a PLL circuit,

the PLL circuit includes:

a voltage-controlled oscillator that outputs a signal of a frequency corresponding to a given frequency control voltage;

a variable divider that divides an output signal of the voltage controlled oscillator corresponding to a signal of a given division ratio;

a phase frequency comparator that compares a reference signal with an output signal of the variable frequency divider and outputs an up signal and a down signal of a frequency corresponding to a comparison result;

a 2 nd phase frequency comparator that compares the reference signal and the output signal of the variable frequency divider and has a delay circuit that outputs a reset signal of an internal flip-flop in a pulse width of a set amount of time;

a frequency control circuit that operates the reference signal as a clock and outputs a signal corresponding to an output frequency of the voltage-controlled oscillator;

a delta-sigma modulator that operates with the reset signal from the 2 nd phase frequency comparator as a clock, and determines the division ratio of the variable frequency divider in accordance with the output of the frequency control circuit;

a charge pump that outputs a current corresponding to the rising signal and the falling signal of the phase frequency comparator; and

a loop filter that outputs a signal obtained by current-voltage converting and smoothing an output of the charge pump to the voltage-controlled oscillator as the frequency control voltage.

Technical Field

The present invention relates to a PLL circuit that generates a Chirp (Chirp) signal used as an FMCW (Frequency Modulated Continuous Wave) radar transmission Wave, for example.

Background

The PLL circuit compares the phase of an output signal of a voltage controlled oscillator (hereinafter, referred to as VCO) with the phase of a reference signal, and feeds back the result to a frequency control voltage of the VCO, thereby stabilizing the oscillation frequency of the VCO. In this PLL circuit, a phase-modulated signal can be output from the VCO by time-controlling the ratio of the VCO frequency to the reference signal frequency. This enables a PLL circuit to generate a chirp signal used as an FMCW radar transmission wave, for example.

As a conventional PLL circuit for generating a chirp signal, a delta-sigma modulator controls a frequency division ratio at which the output of a VCO is divided by a variable frequency divider to realize a fractional frequency division ratio, and sets the output of the VCO to a frequency that is a multiple of the fraction of a reference signal. The data input to the delta-sigma modulator is a value corresponding to the output frequency of the VCO generated by the frequency control circuit, and for example, if data that gradually increases with time is used, a chirp signal whose frequency increases with time is output from the VCO.

Here, since the Δ Σ modulator generally needs to operate in synchronization with the variable frequency divider, the divided signal (CLKdiv) which is the output of the variable frequency divider operates as a clock. On the other hand, since the frequency control circuit externally controls the modulation timing of the chirp signal, the reference signal (CLKref) inputted from the outside is operated as a clock. Therefore, the data is transferred from the frequency control circuit to the Δ Σ modulator between different circuits in the clock domain, and it is necessary to sufficiently consider the timing. Conventionally, as a countermeasure against such timing, there is a circuit that inverts a reference signal input to a phase frequency comparator to perform data transfer stably as a clock of a frequency control circuit (for example, see non-patent document 1).

Disclosure of Invention

Problems to be solved by the invention

However, in the conventional circuit described in non-patent document 1, it is not sufficient to simply invert the clock (delay of half clock) when the fluctuation range of the Δ Σ modulator is large or when the output of the VCO is phase-shifted, and there is a problem that a data transfer error occurs in some cases.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a PLL circuit capable of preventing occurrence of a data transfer error even when a timing difference between CLKref and CLKdiv is large.

Means for solving the problems

The PLL circuit of the present invention includes: a voltage-controlled oscillator that outputs a signal of a frequency corresponding to a given frequency control voltage; a variable divider that divides an output signal of the voltage controlled oscillator corresponding to a signal of a given division ratio; a phase frequency comparator that compares the reference signal with an output signal of the variable frequency divider and outputs an up signal and a down signal of a frequency corresponding to the comparison result; an AND gate circuit that outputs a logical AND operation result of the up signal and the down signal; a frequency control circuit that operates using the reference signal as a clock and outputs a signal corresponding to an output frequency of the voltage-controlled oscillator; a flip-flop circuit that holds and outputs an output signal of the frequency control circuit at a timing of an output signal of the and circuit; a delta-sigma modulator that operates with the output of the variable frequency divider as a clock, and determines a division ratio of the variable frequency divider in accordance with the output of the flip-flop circuit; a charge pump that outputs a current corresponding to the rising signal and the falling signal; and a loop filter that outputs a signal obtained by current-voltage converting and smoothing an output of the charge pump to the voltage-controlled oscillator as a frequency control voltage.

Effects of the invention

A PLL circuit of the present invention performs retiming of a frequency value Freq _ data output from a frequency control circuit using an output of an AND gate circuit that outputs a logical AND operation result of a rising signal and a falling signal of a phase frequency comparator. Thus, even when the timing difference between CLKref and CLKdiv is large, it is possible to prevent the occurrence of a data transfer error.

Drawings

Fig. 1 is a block diagram showing a PLL circuit according to embodiment 1 of the present invention.

Fig. 2 is a timing chart showing operation waveforms of each part of the PLL circuit according to embodiment 1 of the present invention.

Fig. 3A is a configuration diagram showing a PLL circuit according to embodiment 2 of the present invention, and fig. 3B is a configuration diagram of a phase frequency comparator.

Fig. 4 is a timing chart showing operation waveforms of each part of the PLL circuit according to embodiment 2 of the present invention.

Fig. 5 is a block diagram showing a PLL circuit according to embodiment 3 of the present invention.

Fig. 6 is a timing chart showing operation waveforms of each part of the PLL circuit according to embodiment 3 of the present invention.

Fig. 7 is a block diagram showing a PLL circuit according to embodiment 4 of the present invention.

Detailed Description

Hereinafter, in order to explain the present invention in more detail, a mode for carrying out the present invention will be described with reference to the drawings.