阅读说明：本技术 源极驱动器的通道电路及其操作方法 (Channel circuit of source driver and operation method thereof ) 是由 郑彦诚 宋光峰 于 2019-05-15 设计创作，主要内容包括：本发明提供一种源极驱动器的通道电路及其操作方法。所述通道电路包括数字模拟转换器、第一开关、输出缓冲电路以及预充电电路。第一开关的两端分别耦接至数字模拟转换器的第一输出端与输出缓冲电路的第一输入端。预充电电路耦接至输出缓冲电路的第一输入端。在一些实施例中,当第一开关在预充电期间为截止(turn off)时,预充电电路用以对输出缓冲电路的第一输入端进行预充电。当第一开关在正常操作期间为导通(turn on)时,预充电电路对输出缓冲电路的第一输入端不进行预充电。(The invention provides a channel circuit of a source driver and an operation method thereof. The channel circuit comprises a digital-analog converter, a first switch, an output buffer circuit and a pre-charging circuit. Two ends of the first switch are respectively coupled to the first output end of the digital-to-analog converter and the first input end of the output buffer circuit. The pre-charge circuit is coupled to the first input terminal of the output buffer circuit. In some embodiments, the precharge circuit is configured to precharge the first input of the output buffer circuit when the first switch is off during the precharge period. The precharge circuit does not precharge the first input terminal of the output buffer circuit when the first switch is on (turn on) during normal operation.)

1. A channel circuit of a source driver, the channel circuit comprising:

a digital-to-analog converter;

a first switch having a first terminal coupled to the first output terminal of the digital-to-analog converter;

an output buffer circuit having a first input terminal coupled to the second terminal of the first switch, wherein an output terminal of the output buffer circuit is used for driving a data line of a display panel; and

a precharge circuit coupled to the first input of the output buffer circuit, wherein the precharge circuit is configured to precharge the first input of the output buffer circuit when the first switch is off during a precharge period, and the precharge circuit is configured not to precharge the first input of the output buffer circuit when the first switch is on during normal operation.

2. The channel circuit of claim 1, further comprising:

a detection circuit coupled to the pre-charge circuit for providing a detection result to the pre-charge circuit, wherein the pre-charge circuit is used for pre-charging the first input terminal of the output buffer circuit according to the detection result during the pre-charge period.

3. The channel circuit of claim 2, wherein the precharge circuit is configured to determine a precharge voltage level in accordance with the detection result to precharge the first input terminal of the output buffer circuit in accordance with the precharge voltage level.

4. The channel circuit of claim 2, wherein the detection circuit is coupled to the first output terminal of the digital-to-analog converter for detecting the first output terminal of the digital-to-analog converter during the pre-charging to obtain the detection result.

5. The channel circuit of claim 4, wherein the detection circuit is further coupled to the first input terminal of the output buffer circuit to detect an input of the output buffer circuit, the detection circuit to obtain the detection result according to a difference between a voltage of the first output terminal of the digital-to-analog converter and a voltage of the first input terminal of the output buffer circuit.

6. The channel circuit of claim 5, wherein the detection result comprises a first bias voltage and a second bias voltage.

7. The channel circuit of claim 6, wherein the detection circuit comprises:

a first transistor having a control terminal coupled to the first output terminal of the digital-to-analog converter, wherein a first terminal of the first transistor is coupled to a current supply terminal of a first current source, a second terminal of the first transistor is coupled to the first input terminal of the output buffer circuit, and a voltage of the first terminal of the first transistor is used as the first bias voltage; and

a second transistor having a control terminal coupled to the first output terminal of the digital-to-analog converter, wherein a first terminal of the second transistor is coupled to a current-drawing terminal of a second current source, a second terminal of the second transistor is coupled to the first input terminal of the output buffer circuit, and a voltage of the first terminal of the second transistor is used as the second bias voltage.

8. The channel circuit of claim 7, wherein the precharge circuit comprises:

a third transistor having a control terminal coupled to the detection circuit to receive the first bias voltage, wherein a first terminal of the third transistor is coupled to a first voltage and a second terminal of the third transistor is coupled to the first input terminal of the output buffer circuit; and

a fourth transistor having a control terminal coupled to the detection circuit for receiving the second bias voltage, wherein a first terminal of the fourth transistor is coupled to a second voltage, and a second terminal of the fourth transistor is coupled to the first input terminal of the output buffer circuit.

9. The channel circuit of claim 2, further comprising a second switch having first and second terminals coupled to the second output terminal of the digital-to-analog converter and the second input terminal of the output buffer circuit, respectively.

10. The channel circuit of claim 9, wherein the precharge circuit comprises:

a first transistor having a control terminal coupled to the detection circuit for receiving a first bias voltage, wherein a first terminal of the first transistor is coupled to a first voltage, and a second terminal of the first transistor is coupled to the second input terminal of the output buffer circuit; and

a second transistor having a control terminal coupled to the detection circuit for receiving a second bias voltage, wherein a first terminal of the second transistor is coupled to a second voltage, and a second terminal of the second transistor is coupled to the second input terminal of the output buffer circuit.

11. The channel circuit of claim 2, further comprising:

the first enabling switch circuit is coupled to the detection circuit and is used for being controlled by a first enabling signal; and

the second enabling switch circuit is coupled to the pre-charging circuit and is used for being controlled by a second enabling signal.

12. The channel circuit of claim 11, wherein the first enable signal and the second enable signal disable the detection circuit and the pre-charge circuit, respectively, when the first switch is turned on, and the first enable signal and the second enable signal enable the detection circuit and the pre-charge circuit, respectively, when the first switch is turned off.

13. A method of operating a channel circuit of a source driver, the method comprising:

providing an analog signal to a first input end of an output buffer circuit through a first switch by a first output end of a digital-to-analog converter during normal operation, wherein the output end of the output buffer circuit is used for driving a data line of a display panel;

precharging the first input terminal of the output buffer circuit by a precharge circuit when the first switch is off during precharge; and

the first input terminal of the output buffer circuit is not precharged by the precharge circuit when the first switch is conductive during the normal operation.

14. The method of operation of claim 13, further comprising:

providing a detection result to the pre-charging circuit by a detection circuit, wherein the pre-charging circuit is used for pre-charging the first input terminal of the output buffer circuit according to the detection result during the pre-charging period.

15. The method of operation of claim 14, wherein the step of precharging comprises:

determining, by the precharge circuit, a precharge voltage level according to the detection result to precharge the first input terminal of the output buffer circuit according to the precharge voltage level.

16. The method of operation of claim 14, further comprising:

detecting, by the detection circuit, the first output terminal of the digital-to-analog converter during the pre-charging to obtain the detection result.

17. The method of operation of claim 16, further comprising:

detecting, by the detection circuit, an input of the output buffer circuit; and

obtaining, by the detection circuit, the detection result in accordance with a difference between a voltage of the first output terminal of the digital-to-analog converter and a voltage of the first input terminal of the output buffer circuit.

18. The method of operation of claim 14 wherein the detection circuit is controlled by a first enable signal and the pre-charge circuit is controlled by a second enable signal, the method further comprising:

when the first switch is conducted, the detection circuit and the pre-charging circuit are respectively disabled by the first enabling signal and the second enabling signal; and

when the first switch is turned off, the detection circuit and the pre-charge circuit are respectively enabled by the first enabling signal and the second enabling signal.

19. A channel circuit of a source driver, the channel circuit comprising:

a digital-to-analog converter;

a switch having a first terminal coupled to a first output terminal of the digital-to-analog converter;

an output buffer circuit having a first input terminal coupled to the second terminal of the switch, wherein an output terminal of the output buffer circuit is used for driving a data line of a display panel;

a precharge circuit coupled to the first input of the output buffer circuit; and

a detection circuit coupled to the pre-charge circuit for providing a detection result to the pre-charge circuit, wherein the pre-charge circuit is used for pre-charging the first input terminal of the output buffer circuit according to the detection result during the pre-charge period.

Technical Field

The present invention relates to an electronic circuit, and more particularly, to a channel circuit of a source driver and a method for operating the same.

Background

Fig. 1 is a schematic circuit block diagram of a channel circuit 10 of a conventional source driver. The channel circuit 10 includes a digital-to-analog converter (DAC) 11 and an output buffer circuit 12. The output terminal of the output buffer circuit 12 is coupled to the data line 21 of the display panel 20. The output terminal of the digital-to-analog converter 11 is directly coupled to the input terminal of the output buffer circuit 12 via a metal line 13. The digital-analog converter 11 may convert the digital pixel data D11 into an analog signal and output the analog signal to the output buffer circuit 12 via the metal line 13. The output buffer circuit 12 may output a driving signal corresponding to the analog signal to the data line 21 of the display panel 20.

After the analog signal output by the digital-to-analog converter 11 is transited, the signal level of the metal line 13 needs a period of time to be stabilized (transited to a new level). Generally, the metal line 13 has a parasitic capacitance (trace capacitance) C13, and the input terminal of the output buffer circuit 12 has a parasitic capacitance (input capacitance) C12. The parasitic capacitances C12 and C13 are one of factors that determine the Slew Rate (Slew Rate) of the input signal of the output buffer circuit 12. In any case, the operating frequency of the display panel 20 is higher and higher, i.e. one line driving period of the data line 21 is shorter and shorter. The slew rate of the input signal of the output buffer circuit 12 tends to limit the increase in the operating frequency of the display panel 20.

In any case, the thrust (driving capability) of the digital-analog converter 11 is limited. In the trend of higher and higher operating frequencies of the display panel 20, the thrust of the digital-to-analog converter 11 often cannot meet the design requirement of recovery time (recovery).

It should be noted that the contents of the "prior art" section are provided to aid in understanding the present invention. Some (or all) of the disclosure in the "prior art" section may not be known to those skilled in the art. What is disclosed in the "prior art" section is not a representation that this content was known to a person skilled in the art before the present application.

Disclosure of Invention

The invention provides a channel circuit of a source driver and an operation method thereof, which are beneficial to improving the operation frequency of a display panel.

An embodiment of the invention provides a channel circuit of a source driver. The channel circuit comprises a digital-analog converter, a first switch, an output buffer circuit and a pre-charging circuit. The first switch has a first terminal coupled to the first output terminal of the digital-to-analog converter. The first input terminal of the output buffer circuit is coupled to the second terminal of the first switch. The output end of the output buffer circuit is used for driving the data lines of the display panel. The pre-charge circuit is coupled to the first input terminal of the output buffer circuit. The precharge circuit is configured to precharge the first input terminal of the output buffer circuit when the first switch is turned off during the precharge period. The precharge circuit does not precharge the first input terminal of the output buffer circuit when the first switch is on (turn on) during normal operation.

An embodiment of the invention provides an operation method of a channel circuit of a source driver. The operation method comprises the following steps: providing an analog signal to a first input end of an output buffer circuit by a first output end of the digital-to-analog converter through a first switch during normal operation, wherein the output end of the output buffer circuit is used for driving a data line of a display panel; when the first switch is turned off during the precharge period, precharging the first input terminal of the output buffer circuit by the precharge circuit; and not precharging the first input terminal of the output buffer circuit by the precharge circuit when the first switch is on during normal operation.

An embodiment of the invention provides a channel circuit of a source driver. The channel circuit comprises a digital-analog converter, a switch, an output buffer circuit, a pre-charging circuit and a detection circuit. The first terminal of the switch is coupled to the first output terminal of the digital-to-analog converter. The first input terminal of the output buffer circuit is coupled to the second terminal of the first switch. The output end of the output buffer circuit is used for driving the data lines of the display panel. The pre-charge circuit is coupled to the first input terminal of the output buffer circuit. The detection circuit is coupled to the pre-charge circuit. The detection circuit is used for providing a detection result to the pre-charging circuit. The pre-charging circuit is used for pre-charging the first input end of the output buffer circuit according to the detection result during the pre-charging period.

Based on the above, the channel circuit of the source driver and the operating method thereof according to the embodiments of the present invention can precharge the input terminal of the output buffer circuit with the precharge circuit having a sufficient push force during the precharge period before the normal operation period. During the normal operation period after the pre-charging period is over, the output end of the digital-analog converter can provide the analog signal to the input end of the output buffer circuit through the switch. Therefore, the recovery time (recovery time) of the output of the digital-analog converter can be effectively shortened. The reduction of the recovery time of the output of the digital-to-analog converter is beneficial to the improvement of the operating frequency of the display panel.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic circuit block diagram of a channel circuit of a conventional source driver.

Fig. 2 is a block diagram of a channel circuit of a source driver according to an embodiment of the invention.

Fig. 3 is a signal waveform diagram illustrating a channel circuit according to an embodiment of the invention.

Fig. 4 is a flow chart illustrating an operation method of a channel circuit of a source driver according to an embodiment of the invention.

Fig. 5 is a block diagram of a channel circuit of a source driver according to another embodiment of the invention.

Fig. 6 is a block diagram of a channel circuit of a source driver according to another embodiment of the invention.

Fig. 7 is a signal waveform diagram illustrating a channel circuit according to an embodiment of the invention.

Fig. 8 is a block diagram of a channel circuit of a source driver according to another embodiment of the invention.

Fig. 9 is a signal waveform diagram illustrating a channel circuit according to an embodiment of the invention.

Fig. 10 is a block diagram of a channel circuit of a source driver according to a further embodiment of the invention.

Fig. 11 is a block diagram of a channel circuit of a source driver according to another embodiment of the invention.

Fig. 12 is a block diagram of a channel circuit of a source driver according to another embodiment of the invention.

[ notation ] to show

10: channel circuit

11: digital-to-analog converter

12: output buffer circuit

13: metal wire

20. 40: display panel

21. 41: data line

30: source driver

200. 500, 600, 800, 1000, 1100, 1200: channel circuit

210. 610, 810, 1110, 1210: digital-to-analog converter

220. 820, 1120, 1220A, 1220B, 1220C, SWA, SWB, SWC: switch with a switch body

230. 630, 830, 1130, 1230: output buffer circuit

240. 640, 840, 1140, 1240: pre-charging circuit

550. 650, 850, 1150: detection circuit

C12, C13: parasitic capacitance

D11: pixel data

DAC _ OUT, DAC _ OUTA, DAC _ OUTB, DAC _ OUTC, DACO: analog signal

EN _ SW: control signal

EN _ SW _ B, EN _ SW _ C, EN _ SW _ D, EN _ SW _ E, EN _ SW _ F: enabling signal

In, Ip: current source

MN, MN1, MN2, MN3, MN4, MN5, MN6, MNA, MNB, MNC, MP1, MP2, MP3, MP4, MP5, MP6, MPA, MPB, MPC: transistor with a metal gate electrode

OP _ IN, OP _ INA, OP _ INB, OP _ INC, OPI: input voltage

OP _ OUT: voltage of

P1: during precharge period

P2: during normal operation

PSL: during the scanning line

S310, S320: step (ii) of

SWB1, SWB2, SWB3, SWB4, SWB5, SWB6, SWC1, SWC2, SWC5, SWC 6: enabling switch

VDDA, VSSA: voltage of

VBa, VBb, VBc, VBd, VBe, VBf: bias voltage

Detailed Description

The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or some connection means. The terms "first," "second," and the like, as used throughout this specification, including the claims, are used to designate elements (elements) or to distinguish between different embodiments or ranges, and are not intended to limit the number of elements, either to the upper or lower limit or to limit the order of the elements. Further, wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. Elements/components/steps in different embodiments using the same reference numerals or using the same terms may be referred to one another in relation to the description.

Fig. 2 is a circuit block diagram of a channel circuit 200 of a source driver 30 according to an embodiment of the invention. The source driver 30 includes a plurality of channel circuits, such as the channel circuit 200 shown in fig. 2. The number of channel circuits in the source driver 30 can be determined according to design requirements. Any one of the channel circuits may be coupled to at least one corresponding data line of a plurality of data lines of the display panel 40. For example, the output terminal of the channel circuit 200 is coupled to the data line 41 of the display panel 40. Based on the driving operation of the data lines by these channel circuits, the display panel 40 can display an image. The display panel 40 shown in fig. 2 can refer to the display panel 20 shown in fig. 1, and the data lines 41 shown in fig. 2 can refer to the data lines 21 shown in fig. 1, and therefore, the description thereof is omitted.

Details of the implementation of the channel circuit 200 shown in fig. 2 will be described below. The other channel circuits in the source driver 30 can be analogized with reference to the description of the channel circuit 200, and therefore, the description thereof is omitted. In the embodiment shown in fig. 2, the channel circuit 200 includes a digital-to-analog converter (DAC) 210, a switch 220, an output buffer circuit 230, and a precharge circuit 240. The embodiment does not limit the implementation of the digital-to-analog converter 210 and the output buffer circuit 230. For example, the digital-to-analog converter 210 may be a conventional digital-to-analog converter in a source driver or other digital-to-analog conversion circuit, and the output buffer circuit 230 may be a conventional output buffer in a source driver or other output buffer according to design requirements.

As shown IN fig. 2, the precharge circuit 240 may be coupled to the input terminal OP _ IN of the output buffer circuit 230. Further, the precharge circuit 240 may be configured such that the precharge circuit 240 precharges the input terminal OP _ IN of the output buffer circuit 230 when the switch 220 is turned off during the precharge, and the precharge circuit 240 does not precharge the input terminal OP _ IN of the output buffer circuit 230 when the first switch is turned on during the normal operation later than the precharge. During normal operation after the precharge period, the output terminal DAC _ OUT of the digital-analog converter 210 may provide an analog signal to the input terminal of the output buffer circuit through the switch. Therefore, the input terminal OP _ IN of the output buffer circuit 230 can be precharged with sufficient thrust by the precharge circuit 240 during the precharge period prior to the normal operation period. Advantageously, the recovery time (recovery time) of the output DAC _ OUT of the digital-to-analog converter 210 can be effectively shortened. The shortened recovery time of the output terminal DAC _ OUT of the digital-to-analog converter 210 may help to increase the operating frequency of the display panel 40. This will be explained in more detail in the following examples.

Fig. 3 is a signal waveform diagram illustrating a channel circuit according to an embodiment of the invention. Fig. 3 will be explained together with fig. 2 below. In any case, the waveform diagram of fig. 3 is not limited to be applied to the channel circuit of fig. 2, and may be applied to other channel circuits. Also, the channel circuit of fig. 2 is not limited to operating with the signal waveforms shown in fig. 3, and may operate using signals having different waveforms. The horizontal axis of fig. 3 represents time, while the vertical axis represents signal level (e.g., voltage level). In the embodiment shown in FIG. 3, one scan line period PSL is divided into at least a precharge period P1 and a normal operation period P2.

Please refer to fig. 2 and fig. 3. A first terminal of the switch 220 is coupled to the output terminal of the digital-to-analog converter 210. The second terminal of the switch 220 is coupled to the input terminal of the output buffer circuit 230. The output end of the output buffer circuit 230 is used for driving the data line 41 of the display panel 40. The control terminal of the switch 220 is controlled by the control signal EN _ SW. The switch 220 may be designed to be OFF during the precharge period P1 (i.e., turn OFF). The switch 220 is ON during normal operation P2.

Fig. 4 is a flow chart illustrating an operation method of a channel circuit of a source driver according to an embodiment of the invention. Please refer to fig. 2 to 4. In step S310, i.e., during the precharge period P1, the switch 220 is turned off, and the precharge circuit 240 may precharge the input terminal of the output buffer circuit 230. Because the switch 220 is turned off, the transition of the analog signal DAC _ OUT at the output terminal of the digital-to-analog converter 210 during the precharge period P1 can be accelerated (due to the reduction of the parasitic capacitance). When the switch 220 is turned off, the pre-charge circuit 240 can pre-charge the input voltage OP _ IN of the input terminal of the output buffer circuit 230 to a predetermined level, so that the voltage OP _ OUT of the output terminal of the output buffer circuit 230 is also pre-pulled high.

In step S320, i.e., during the normal operation period P2, the switch 220 is turned on and the pre-charge circuit 240 does not pre-charge the input terminal of the output buffer circuit 230. For example, during normal operation P2, the output of precharge circuit 240 is in a high Impedance (Hi Impedance, Hi-z) state. When the switch 220 is turned on, the output terminal of the digital-to-analog converter 210 provides the analog signal to the input terminal of the output buffer circuit 230 through the switch 220.

In summary, in the precharge period P1 before the normal operation period P2, the input terminal of the output buffer circuit 230 is precharged with the precharge circuit 240 having a sufficient thrust. During the normal operation period P2 after the precharge period P1 ends, the output terminal of the digital-to-analog converter 210 provides the analog signal to the input terminal of the output buffer circuit 230 through the switch 220. Therefore, the recovery time (recovery time) of the output of the digital-analog converter 210 can be effectively shortened. The reduction of the recovery time of the output of the digital-to-analog converter 210 is advantageous for the increase of the operating frequency of the display panel 40.

Fig. 5 is a block diagram of a channel circuit 500 of a source driver according to another embodiment of the invention. The channel circuit 500 shown in fig. 5 can be analogized with the related description of the channel circuit 200 shown in fig. 2, and thus the description thereof is omitted. In the embodiment shown in fig. 5, the channel circuit 500 includes a digital-to-analog converter 210, a switch 220, an output buffer circuit 230, a precharge circuit 240, and a detection circuit 550. The digital-to-analog converter 210, the switch 220, the output buffer circuit 230 and the precharge circuit 240 shown in fig. 5 can be analogized with reference to the related descriptions of fig. 2 to 4, and therefore, the description thereof is omitted.

Please refer to fig. 3 and 5. The detection circuit 550 shown in fig. 5 is coupled to the control terminal of the precharge circuit 240. The detection circuit 550 may provide the detection result to the precharge circuit 240. The precharge circuit 240 may precharge the input terminal of the output buffer circuit 230 according to the detection result during the precharge period P1. For example, the detection circuit 550 may be coupled to the output terminal of the digital-to-analog converter 210 to detect the analog signal DAC _ OUT at the output terminal of the digital-to-analog converter 210 to obtain the detection result. The detection circuit 550 may be configured to enable the precharge circuit 240 when the analog signal satisfies a predetermined condition. In some embodiments, when the analog signal DAC _ OUT at the output terminal of the digital-to-analog converter 210 is transited, the detection circuit 550 may notify the precharge circuit 240, so that the precharge circuit 240 may precharge the input terminal of the output buffer circuit 230 according to the detection result during the precharge period P1.

In some embodiments, the precharge circuit 240 may be configured to determine the precharge voltage level according to the detection result of the detection circuit 550. The precharge circuit 240 may precharge the input terminal of the output buffer circuit 230 in accordance with the precharge voltage level.

IN some embodiments, the detection circuit 550 is further coupled to the input terminal of the output buffer circuit 230 to detect the input (the input voltage OP _ IN) of the output buffer circuit 230. The detection circuit 550 is used for obtaining the detection result according to the difference between the voltage at the output terminal of the digital-to-analog converter 210 (analog signal DAC _ OUT) and the voltage at the input terminal of the output buffer circuit 230 (input voltage OP _ IN). IN some embodiments, the detection circuit 550 may be configured to detect whether a level difference between a level of the analog signal DAC _ OUT of the digital-to-analog converter 210 and a level of the input terminal OP _ IN of the output buffer circuit 230 exceeds a predetermined difference. If the level difference exceeds the predetermined difference, the detection circuit 550 may enable the precharge circuit to precharge the input terminal OP _ IN of the output buffer circuit 230.

Fig. 6 is a block diagram of a channel circuit 600 of a source driver according to another embodiment of the invention. In the embodiment shown in fig. 6, the channel circuit 600 includes a digital-to-analog converter 610, a switch SWA, a switch SWB, a switch SWC, an output buffer circuit 630, at least one precharge circuit 640, and at least one detection circuit 650. The channel circuit 600, the digital-analog converter 610, the output buffer circuit 630, the precharge circuit 640 and the detection circuit 650 shown in fig. 6 can be analogized by referring to the related description of the channel circuit 500, the digital-analog converter 210, the output buffer circuit 230, the precharge circuit 240 and the detection circuit 550 shown in fig. 5, and the switches SWA, SWB and SWC shown in fig. 6 can be analogized by referring to the related description of the switch 220 shown in fig. 5, and thus are not described again.

In the embodiment shown in fig. 6, the first terminal and the second terminal of the switch SWA are respectively coupled to the first output terminal of the digital-to-analog converter 610 and the first input terminal of the output buffer circuit 630, the first terminal and the second terminal of the switch SWB are respectively coupled to the second output terminal of the digital-to-analog converter 610 and the second input terminal of the output buffer circuit 630, and the first terminal and the second terminal of the switch SWC are respectively coupled to the third output terminal of the digital-to-analog converter 610 and the third input terminal of the output buffer circuit 630.

In some embodiments, during the precharge period P1, the precharge circuit 640 may precharge the first input terminal OP _ INA, the second input terminal OP _ INB, and the third input terminal OP _ INC of the output buffer circuit 630. In addition, the precharge circuit 640 may precharge the input voltage OP _ INA of the first input terminal, the input voltage OP _ INB of the second input terminal, and the input voltage OP _ INC of the third input terminal of the output buffer circuit 630 to different preset levels (or the same preset level).

During the precharge period, the switch SWA, the switch SWB, and the switch SWC are preferably turned off. By turning off the switches SWA, SWB and SWC during the precharge period, the states of the analog signals DAC _ OUTA at the first output terminal, DAC _ OUTB at the second output terminal and DAC _ OUTC at the third output terminal of the digital-to-analog converter 610 can be accelerated due to the reduction of the parasitic capacitance.

During a normal operation period later in the precharge period, the switches SWA, SWB and SWC are turned on, and the precharge circuit 640 does not precharge the first input terminal, the second input terminal and the third input terminal of the output buffer circuit 630. For example, during normal operation period P2, the output terminal of the precharge circuit 640 is in a high impedance state. When the switches SWA, SWB and SWC are turned on, the output terminal of the digital-to-analog converter 610 provides analog signals to the input terminal of the output buffer circuit 630 through the switches SWA, SWB and SWC.

In the embodiment shown in fig. 6, the detection result output by the detection circuit 650 includes the bias voltage VBa and the bias voltage VBb.

In the embodiment shown in fig. 6, the detection circuit 650 shown in fig. 6 includes a transistor MN and a transistor MP. The transistor MN and the transistor MP are configured to control the level of the bias voltage VBa and the level of the bias voltage VBb according to the difference between the analog signal DAC _ OUTA and the input voltage OP _ INA. A control terminal (e.g., a gate) of the transistor MN is coupled to the first output terminal of the digital-to-analog converter 610 to receive the analog signal DAC _ OUTA. A first terminal (e.g., a drain) of the transistor MN is coupled to a current supply terminal of the current source Ip. The voltage at the first terminal of the transistor MN acts as the bias voltage VBa. A second terminal (e.g., a source) of the transistor MN is coupled to the first input terminal of the output buffer circuit 630 for receiving the input voltage OP _ INA. A control terminal (e.g., a gate) of the transistor MP is coupled to the first output terminal of the digital-to-analog converter 610 to receive the analog signal DAC _ OUTA. A first terminal (e.g., a drain) of the transistor MP is coupled to a current-drawing terminal of the current source In. The voltage at the first terminal of the transistor MP is used as the bias voltage VBb. A second terminal (e.g., a source) of the transistor MP is coupled to the first input terminal of the output buffer circuit 630 for receiving the input voltage OP _ INA. In one embodiment, the transistor MN and the transistor MP can correspondingly determine the level of the bias voltage VBa and the level of the bias voltage VBb according to the difference between the analog signal DAC _ OUTA and the input voltage OP _ INA.

In the embodiment shown in fig. 6, the precharge circuit 640 includes a transistor MPA, a transistor MPB, a transistor MPC, a transistor MNA, a transistor MNB, and a transistor MNC. The control terminals (e.g., gates) of the transistors MPA, MPB and MPC are coupled to the detection circuit 650 for receiving the bias voltage VBa. The first terminals (e.g., sources) of the transistors MPA, MPB and MPC are coupled to the voltage VDDA. The control terminals (e.g., gates) of the transistors MNA, MNB and MNC are coupled to the detection circuit 650 for receiving the bias voltage VBb. First terminals (e.g., sources) of the transistors MNA, MNB, and MNC are coupled to the voltage VSSA. Second terminals (e.g., drains) of the transistor MPA and the transistor MNA are coupled to a first input terminal of the output buffer circuit 630. A second terminal (e.g., drain) of the transistors MPB and MNB is coupled to a second input terminal of the output buffer circuit 630. Second terminals (e.g., drains) of the transistors MPC and MNC are coupled to the third input terminal of the output buffer circuit 630. In one embodiment, the precharge circuit 640 may determine the precharge voltage level according to the detection result of the detection circuit 650. The precharge circuit 640 may precharge a plurality of input terminals of the output buffer circuit 630 according to the precharge voltage level.

Fig. 7 is a signal waveform diagram illustrating a channel circuit according to an embodiment of the invention. Fig. 7 will be explained together with fig. 6 below. In any case, the waveform diagram of fig. 7 is not limited to being applied to the channel circuit of fig. 6, and may be applied to other channel circuits. The channel circuit of fig. 6. Also, the channel circuit of fig. 6 is not limited to the signal waveforms shown in fig. 7, and may operate using signals having different waveforms.

Referring to fig. 6 and 7, during the precharge period P1, the switches SWA, SWB and SWC are turned OFF (OFF), and the precharge circuit 640 may precharge the first input terminal, the second input terminal and the third input terminal. Since the switches SWA, SWB, and SWC are off, the conversion of the analog signal DAC _ OUTA of the first output terminal, the analog signal DAC _ OUTB of the second output terminal, and the analog signal DAC _ OUTC of the third output terminal of the digital-analog converter 610 is accelerated (due to the reduction of the parasitic capacitance) during the precharge period P1. When the switches SWA, SWB, and SWC are OFF (OFF), the precharge circuit 640 may precharge the input voltage OP _ INA of the first input terminal, the input voltage OP _ INB of the second input terminal, and the input voltage OP _ INC of the third input terminal of the output buffer circuit 630 to different preset levels (or the same preset level).

During the normal operation period P2, the switches SWA, SWB and SWC are turned ON (ON), and the precharge circuit 640 does not precharge the first input terminal, the second input terminal and the third input terminal of the output buffer circuit 630. For example, during normal operation P2, the output of precharge circuit 640 is in the Hi-z state. When the switches SWA, SWB and SWC are ON (ON), the output terminal of the digital-to-analog converter 610 may provide analog signals to the input terminal of the output buffer circuit 630 through the switches SWA, SWB and SWC.

Fig. 8 is a block diagram of a channel circuit 800 of a source driver according to another embodiment of the invention. In the embodiment shown in fig. 8, the channel circuit 800 includes a digital-to-analog converter 810, a switch 820, an output buffer circuit 830, a pre-charge circuit 840, a detection circuit 850, an enable switch circuit 860, and an enable switch circuit 870. The channel circuit 800, the digital-analog converter 810, the output buffer circuit 830, the precharge circuit 840 and the detection circuit 850 shown in fig. 8 can be analogized by referring to the descriptions of the channel circuit 500, the digital-analog converter 210, the output buffer circuit 230, the precharge circuit 240 and the detection circuit 550 shown in fig. 5, or analogized by referring to the descriptions of the channel circuit 600, the digital-analog converter 610, the output buffer circuit 630, the precharge circuit 640 and the detection circuit 650 shown in fig. 6, and thus the description thereof is omitted. The switch 820 shown in fig. 8 can be analogized with reference to the switch 220 shown in fig. 5 or the switches SWA, SWB and SWC shown in fig. 6, and thus, the description thereof is omitted.

During the precharge period, the switch is preferably turned OFF (OFF), and the precharge circuit 840 may precharge the input terminal of the output buffer circuit 830. During normal operation later than the precharge period, the switch 820 is ON (ON), and the precharge circuit 840 does not precharge the input terminal of the output buffer circuit 830.

In the embodiment shown in FIG. 8, the enable switch circuit 860 is coupled to the detection circuit 850. The enable switch circuit 860 is controlled by the enable signal EN _ SW _ B to determine whether to transmit the voltage VDDA and the voltage VSSA to the detection circuit 850, i.e., whether to enable (enable) the detection circuit 850. The enable switch circuit 870 is coupled to the precharge circuit 840. Enable switch circuit 870 is controlled by enable signal EN _ SW _ C to determine whether to transmit voltage VDDA and voltage VSSA to precharge circuit 840, i.e., whether to enable precharge circuit 840. When the switch 820 is turned ON, the enable signal EN _ SW _ B and the enable signal EN _ SW _ C disable (disable) the detection circuit 850 and the pre-charge circuit 840, respectively. When the switch 820 is turned OFF (OFF), the enable signal EN _ SW _ B and the enable signal EN _ SW _ C enable the detection circuit 850 and the precharge circuit 840, respectively.

Fig. 9 is a signal waveform diagram illustrating a channel circuit according to an embodiment of the invention. Fig. 9 will be explained together with fig. 8 below. In any case, the waveform diagram of fig. 9 is not limited to being applied to the channel circuit of fig. 8, and may be applied to other channel circuits. Also, the channel circuit of fig. 8 is not limited to the signal waveforms shown in fig. 9, and may operate using signals having different waveforms.

Please refer to fig. 8 and 9. In the precharge period P1, the switch 820 is turned off, and the precharge circuit 840 may precharge the input terminal of the output buffer circuit 830. During normal operation P2, switch 820 is on and precharge circuit 840 does not precharge the input of output buffer circuit 830.

In the embodiment shown in fig. 8, the enable switch circuit 860 is coupled to the detection circuit 850. The enable switch circuit 860 is controlled by the enable signal EN _ SW _ B to determine whether to transmit the voltage VDDA and the voltage VSSA to the detection circuit 850, i.e., whether to enable the detection circuit 850. The enable switch circuit 870 is coupled to the precharge circuit 840. Enable switch circuit 870 is controlled by enable signal EN _ SW _ C to determine whether to transmit voltage VDDA and VSSA to precharge circuit 840, i.e., whether to enable precharge circuit 840. When the switch 820 is turned on, the enable signal EN _ SW _ B and the enable signal EN _ SW _ C disable (disable) the detection circuit 850 and the pre-charge circuit 840, respectively. When the switch 820 is turned off, the enable signal EN _ SW _ B and the enable signal EN _ SW _ C enable the detection circuit 850 and the pre-charge circuit 840, respectively.

Fig. 10 is a block diagram of a channel circuit 1000 of a source driver according to a further embodiment of the invention. In the embodiment shown in fig. 10, the channel circuit 1000 includes a digital-to-analog converter 810, a switch 820, an output buffer circuit 830, a pre-charge circuit 840, a detection circuit 850, an enable switch circuit 860, and an enable switch circuit 870. The digital-to-analog converter 810, the switch 820, the output buffer circuit 830, the pre-charge circuit 840, the detection circuit 850, the enable switch circuit 860 and the enable switch circuit 870 shown in fig. 10 can be analogized with reference to the related description of fig. 8, and thus are not repeated herein.

In the embodiment shown In fig. 10, the detection result output by the detection circuit 850 includes the bias voltage VBc and the bias voltage VBd, the enabling switch circuit 860 includes the enabling switch SWB1 and the enabling switch SWB2, and the detection circuit 850 includes the current source Ip, the transistor MN1, the current source In, and the transistor MP 1. The control terminal of the enable switch SWB1 may receive an enable signal EN _ SW _ B. A first terminal of enable switch SWB1 is coupled to voltage VDDA. The current sink of current source Ip is coupled to the second terminal of enable switch SWB 1. A first terminal (e.g., drain) of the transistor MN1 is coupled to the current supply terminal of the current source Ip. A control terminal (e.g., a gate) of the transistor MN1 is coupled to the first terminal of the transistor MN 1. A second terminal (e.g., a source) of the transistor MN1 is coupled to the output terminal of the digital-to-analog converter 810. The voltage at the control terminal of transistor MN1 acts as the bias voltage VBc.

The control terminal of the enable switch SWB2 may receive an enable signal EN _ SW _ B. A first terminal of enable switch SWB2 is coupled to voltage VSSA. The current supply terminal of the current source In is coupled to the second terminal of the enable switch SWB 2. A first terminal (e.g., a drain) of the transistor MP1 is coupled to a current drawing terminal of the current source In. A control terminal (e.g., a gate) of the transistor MP1 is coupled to the first terminal of the transistor MP 1. A second terminal (e.g., a source) of the transistor MP1 is coupled to the output terminal of the digital-to-analog converter 810. The voltage at the control terminal of the transistor MP1 is used as the bias voltage VBd.

In the embodiment shown in fig. 10, the enable switch circuit 870 includes an enable switch SWC1 and an enable switch SWC2, and the precharge circuit 840 includes a transistor MN2 and a transistor MP 2. The control terminal of the enable switch SWC1 is configured to receive an enable signal EN _ SW _ C. A first terminal of enable switch SWC1 is coupled to voltage VDDA. A control terminal (e.g., a gate) of the transistor MN2 is coupled to the detection circuit 850 to receive the bias voltage VBc. A first terminal (e.g., a drain) of the transistor MN2 is coupled to the second terminal of the enable switch SWC1, and a second terminal (e.g., a source) of the transistor MN2 is coupled to the input terminal of the output buffer circuit 830. The control terminal of the enable switch SWC2 is configured to receive an enable signal EN _ SW _ C. A first terminal of enable switch SWC2 is coupled to voltage VSSA. A control terminal (e.g., a gate) of the transistor MP2 is coupled to the detection circuit 850 to receive the bias voltage VBd. A first terminal (e.g., a drain) of the transistor MP2 is coupled to a second terminal of the enable switch SWC 2. A second terminal (e.g., a source) of the transistor MP2 is coupled to the input terminal of the output buffer circuit 830.

Fig. 11 is a block diagram of a channel circuit 1100 of a source driver according to another embodiment of the invention. In the embodiment shown In fig. 11, the channel circuit 1100 includes a digital-to-analog converter 1110, a switch 1120, an output buffer circuit 1130, at least one precharge circuit 1140, at least one detection circuit 1150, an enable switch SWB3, a current source Ip, a current source In, and an enable switch SWB 4. The channel circuit 1100, the digital-to-analog converter 1110, the switch 1120, the output buffer circuit 1130, the precharge circuit 1140 and the detection circuit 1150 shown in fig. 11 can be analogized by referring to the related descriptions of the channel circuit 500, the digital-to-analog converter 210, the switch 220, the output buffer circuit 230, the precharge circuit 240 and the detection circuit 250 shown in fig. 5, and thus are not described again.

In the embodiment shown in fig. 11, the control terminal of the enable switch SWB3 is configured to receive an enable signal EN _ SW _ D. A first terminal of enable switch SWB3 is coupled to voltage VDDA. The current sink of current source Ip is coupled to the second terminal of enable switch SWB 3. The current supply terminal of the current source Ip is coupled to the detection circuit 1150 and the pre-charge circuit 1140. The control terminal of the enable switch SWB4 receives an enable signal EN _ SW _ D. A first terminal of enable switch SWB4 is coupled to voltage VSSA. The current supply terminal of the current source In is coupled to the second terminal of the enable switch SWB 4. The current sink of the current source In is coupled to the detection circuit 1150 and the pre-charge circuit 1140.

In the embodiment shown in fig. 11, the detection result output by the detection circuit 1150 includes a bias VBe and a bias VBf, and the detection circuit 1150 includes a transistor MP3, a transistor MN3, an enable switch SWB5, a transistor MP4, a transistor MN4, and an enable switch SWB 6. A first terminal (e.g., a source) of the transistor MP3 is coupled to the current supply terminal of the current source Ip. A control terminal (e.g., a gate) of the transistor MP3 is coupled to the output terminal of the digital-to-analog converter 1110 for receiving the analog signal DACO. A first terminal (e.g., a drain) of the transistor MN3 is coupled to a second terminal (e.g., a drain) of the transistor MP 3. A control terminal (e.g., a gate) of the transistor MN3 is coupled to the first terminal of the transistor MN 3. The voltage at the control terminal of transistor MN3 acts as bias VBe. The control terminal of the enable switch SWB5 is configured to receive an enable signal EN _ SW _ E. A first terminal of enable switch SWB5 is coupled to a second terminal (e.g., source) of transistor MN 3. The second terminal of enable switch SWB5 is coupled to voltage VSSA.

A first terminal (e.g., source) of the transistor MN4 is coupled to the current drawing terminal of the current source In. A control terminal (e.g., a gate) of the transistor MN4 is coupled to the output terminal of the digital-to-analog converter 1110 to receive the analog signal DACO. A first terminal (e.g., a drain) of the transistor MP4 is coupled to a second terminal (e.g., a drain) of the transistor MN 4. The control terminal of the transistor MP4 is coupled to the first terminal of the transistor MP 4. The voltage at the control terminal of the transistor MP4 acts as the bias voltage VBf. The control terminal of the enable switch SWB6 is configured to receive an enable signal EN _ SW _ E. A first terminal of the enable switch SWB6 is coupled to a second terminal (e.g., source) of the transistor MP 4. The second terminal of enable switch SWB6 is coupled to voltage VDDA.

In the embodiment shown in fig. 11, the precharge circuit 1140 includes a transistor MP5, a transistor MN5, an enable switch SWC5, a transistor MN6, a transistor MP6, and an enable switch SWC 6. A first terminal (e.g., a source) of the transistor MP5 is coupled to the current supply terminal of the current source Ip. A second terminal (e.g., a drain) of the transistor MP5 is coupled to the input terminal of the output buffer circuit 1130. The control terminal (e.g., the gate) of the transistor MP5 is coupled to the second terminal of the transistor MP5, and is coupled to the input terminal of the output buffer circuit 1130 for receiving the input voltage OPI. A control terminal (e.g., a gate) of the transistor MN5 is coupled to the detection circuit 1150 for receiving the bias voltage VBe. A first terminal (e.g., a drain) of the transistor MN5 is coupled to a second terminal of the transistor MP 5. The control terminal of the enable switch SWC5 is configured to receive an enable signal EN _ SW _ F. A first terminal of enable switch SWC5 is coupled to a second terminal (e.g., source) of transistor MN 5. The second terminal of enable switch SWC5 is coupled to voltage VSSA.

A first terminal (e.g., source) of the transistor MN6 is coupled to the current drawing terminal of the current source In. A second terminal (e.g., a drain) of the transistor MN6 is coupled to the input terminal of the output buffer circuit 1130. The control terminal (e.g., gate) of the transistor MN6 is coupled to the second terminal of the transistor MN6 and to the input terminal of the output buffer circuit 1130 for receiving the input voltage OPI. A control terminal (e.g., a gate) of the transistor MP6 is coupled to the detection circuit 1150 for receiving the bias voltage VBf. A first terminal (e.g., a drain) of the transistor MP6 is coupled to a second terminal of the transistor MN 6. The control terminal of the enable switch SWC6 is configured to receive an enable signal EN _ SW _ F. A first terminal of the enable switch SWC6 is coupled to a second terminal (e.g., source) of the transistor MP 6. A second terminal of enable switch SWC6 is coupled to voltage VDDA.

Fig. 12 is a block diagram of a channel circuit 1200 of a source driver according to another embodiment of the invention. In the embodiment shown In fig. 12, the channel circuit 1200 includes a digital-to-analog converter 1210, a switch 1220A, a switch 1220B, a switch 1220C, an output buffer circuit 1230, at least one pre-charge circuit 1240, at least one detection circuit 1150, an enable switch SWB3, a current source Ip, a current source In, and an enable switch SWB 4. The digital-to-analog converter 1210, the switch 1220A, the switch 1220B, the switch 1220C and the output buffer circuit 1230 shown In fig. 12 can be analogized by referring to the descriptions of the digital-to-analog converter 610, the switch SWA, the switch SWB, the switch SWC and the output buffer circuit 630 shown In fig. 6, and the descriptions of the precharge circuit 1240, the detection circuit 1150, the enable switch SWB3, the current source Ip, the current source In and the enable switch SWB4 shown In fig. 12 can be analogized by referring to the descriptions of the precharge circuit 1140, the detection circuit 1150, the enable switch SWB3, the current source Ip, the current source In and the enable switch SWB4 shown In fig. 11, so that the descriptions thereof are omitted.

In summary, the channel circuit of the source driver and the operating method thereof according to some embodiments of the present invention can precharge the input terminal of the output buffer circuit with the precharge circuit having sufficient push force during the precharge period P1 before the normal operation period P2. During the normal operation period P2 after the precharge period P1 ends, the output terminal of the digital-to-analog converter provides an analog signal to the input terminal of the output buffer circuit through the switch. Therefore, the recovery time of the output of the digital-to-analog converter can be effectively shortened. The reduction of the recovery time of the output of the digital-to-analog converter is advantageous for the increase of the operating frequency of the display panel 40.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.