阅读说明：本技术 存储器电路 (Memory circuit ) 是由 W·军林 于 2018-07-09 设计创作，主要内容包括：在一些实施例中,存储器电路包括其间具有横向空间的一对紧邻的存储器阵列。所述存储器阵列个别地包括存储器单元,所述存储器单元个别地具有上部竖向延伸晶体管和下部竖向延伸晶体管以及在其间的竖向电容器。所述存储器阵列包括个别行,所述行(a)具有在下部存取线上方且直接电耦合到所述下部存取线的上部存取线,且(b)跨越所述空间直接彼此电耦合。所述行中的一者中的所述下部存取线从所述存储器阵列中的一者跨越所述空间延伸到所述存储器阵列中的另一者。所述行中的另一者包括跨越所述空间的一部分延伸的导电互连件。所述导电互连件包含在所述空间内从所述另一行横向偏移的水平延伸部分。公开其它方面和实施方案。(In some embodiments, a memory circuit includes a pair of immediately adjacent memory arrays having a lateral space therebetween. The memory array individually includes memory cells individually having upper and lower vertically extending transistors and a vertical capacitor therebetween. The memory array includes individual rows that (a) have upper access lines above and directly electrically coupled to lower access lines, and (b) are directly electrically coupled to one another across the spaces. The lower access line in one of the rows extends from one of the memory arrays across the space to the other of the memory arrays. Another of the rows includes a conductive interconnect extending across a portion of the space. The conductive interconnects include horizontally extending portions laterally offset from the other row within the space. Other aspects and embodiments are disclosed.)

1. A memory circuit, comprising:

a pair of immediately adjacent memory arrays having a lateral space therebetween, the memory arrays individually comprising memory cells individually having upper and lower vertically extending transistors and a vertical capacitor therebetween;

the memory array comprises individual rows that (a) have upper access lines above and directly electrically coupled to lower access lines, and (b) are directly electrically coupled to each other across the space;

the lower access line in one of the rows extends from one of the memory arrays across the space to the other of the memory arrays; and is

Another of the rows includes a conductive interconnect extending across a portion of the space, the conductive interconnect including a horizontally extending portion laterally offset from the other row within the space.

2. The memory circuit of claim 1, wherein the upper access line is directly above the lower access line at least within the one and the other of the memory arrays.

3. The memory circuit of claim 1, wherein the upper vertically extending transistor and the lower vertically extending transistor are vertical or within 10 ° of vertical.

4. The memory circuit of claim 3, wherein the upper and lower vertically extending transistors in the individual memory cells share a common linear axis along which, in operation, current flows through channels of the respective upper and lower vertically extending transistors.

5. The memory circuit of claim 1, wherein the upper access line in the one row does not extend across the space from the one memory array to the other memory array.

6. The memory circuit of claim 1, wherein the horizontally extending portions of the conductive interconnects are in a common horizontal plane with horizontally extending portions of the upper access lines.

7. The memory circuit of claim 1, wherein the horizontally extending portion of the conductive interconnect is within the one row.

8. The memory circuit of claim 7, wherein the horizontally extending portion of the conductive interconnect is directly above the lower access line in the one row.

9. The memory circuit of claim 1, wherein the upper access lines and the lower access lines in the individual rows are electrically coupled directly to each other with conductive material over the upper access lines.

10. The memory circuit of claim 9, wherein the conductive material is directly above the upper access line in the space.

11. The memory circuit of claim 10, wherein the conductive material is directly above the lower access line in the space.

12. The memory circuit of claim 1, wherein the upper access line and the lower access line in the individual row are directly electrically coupled to each other with a first conductive via contacting an uppermost surface of the upper access line and a second conductive via contacting an uppermost surface of the lower access line.

13. The memory circuit of claim 12, wherein the upper access line and the lower access line in the individual row are directly electrically coupled to each other with conductive material over the upper access line and directly against an uppermost surface of each of the first and second conductive vias.

14. The memory circuit of claim 1, wherein the horizontally extending portions of the conductive interconnects are horizontally elongate.

15. The memory circuit of claim 14, the horizontally elongated portions of the conductive interconnects are all laterally offset from the other row.

16. The memory circuit of claim 1, wherein the memory cells are individually two transistor-two capacitor 2T-1C memory cells.

17. The memory circuit of claim 1, comprising a plurality of conductive vias extending within the space from an upper digit line level to a lower digit line level transverse to the horizontally extending portion of the conductive interconnect.

18. A memory circuit, comprising:

a pair of immediately adjacent memory arrays having a lateral space therebetween, the memory arrays individually comprising memory cells individually having upper and lower vertically extending transistors and a vertical capacitor therebetween;

the memory array comprises individual rows that (a) have upper access lines above and directly electrically coupled to lower access lines, and (b) are directly electrically coupled to each other across the space;

the lower access line in one of the rows extends from one of the memory arrays across the space to the other of the memory arrays; and is

Another of the rows includes a conductive interconnect including a horizontally elongated portion extending across a portion of the space and in and longitudinally aligned with the one row.

19. A memory circuit comprising a two transistor-capacitor 2T-1C memory cell, comprising:

a pair of immediately adjacent 2T-1C memory arrays having a lateral space therebetween, the 2T-1C memory arrays individually comprising 2T-1C memory cells, the 2T-1C memory cells individually comprising upper and lower vertically extending transistors having a vertical capacitor therebetween;

the 2T-1C memory array comprises columns of first comparison digit lines at an upper digit line level that are above and electrically coupled to columns of the upper vertically-extending transistors, the 2T-1C memory array comprises columns of second comparison digit lines at a lower digit line level that are below and electrically coupled to columns of the lower vertically-extending transistors;

the 2T-1C memory arrays sharing first alternating rows and second alternating rows, the second alternating rows individually between immediately adjacent of the first alternating rows, the first alternating rows and the second alternating rows individually having upper access lines in an upper access line level that are above lower access lines in a lower access line level, the upper access lines in the individual first alternating rows and the individual second alternating rows being electrically coupled together directly with the lower access lines by conductor interconnects including horizontally extending portions within the upper digit line level that are directly above both the upper access lines and the lower access lines in the individual first alternating rows or the individual second alternating rows, the individual first alternating rows in the 2T-1C memory arrays being electrically coupled to each other directly across the space, the individual second alternating rows in the 2T-1C memory array are not directly electrically coupled to each other across the space;

the lower access lines in alternating ones of the first alternating rows extend across the space from one of the 2T-1C memory arrays to another one of the 2T-1C memory arrays, the lower access lines in alternating ones of the first alternating rows do not extend across the space from one of the 2T-1C memory arrays to another one of the 2T-1C memory arrays, alternating other first alternating rows being individually between immediately adjacent ones of the alternating rows of the first alternating rows; and is

The alternating other first alternating rows in the one 2T-1C memory array and the other 2T-1C memory array are individually electrically coupled directly to each other across the space by conductive interconnects including one horizontal elongate portion in the space in the upper digit line level and another horizontal elongate portion in the space in the upper access line level, the another horizontal elongate portion in the space being directly above the lower access line in an immediately adjacent one of the alternating rows of the first alternating rows.

20. The memory circuit of claim 19 comprising a plurality of conductive vias extending within the space from the upper digit line level to the lower digit line level laterally between two immediately adjacent ones of alternating ones of the first alternating rows.

Technical Field

Embodiments disclosed herein relate to memory circuits.

Background

Memory is a type of collection and is used in computer systems to store data. The memory may be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which can also be referred to as bit lines, data lines, sense lines) and access lines (which can also be referred to as word lines). The digit lines can conductively interconnect memory cells along columns of the array, and the access lines can conductively interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of a digit line and an access line.

The memory cells may be volatile, semi-volatile, or nonvolatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. Regardless, the memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the state is considered to be either "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two bits or states of information.

Capacitors are one type of electronic component that can be used in memory cells. The capacitor has two electrical conductors separated by an electrically insulating material. Energy such as an electric field may be stored electrostatically within such materials. Depending on the composition of the insulating material, the stored field will be volatile or non-volatile. For example, comprising SiO only₂The capacitor insulating material of (a) will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor having a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized as programmable materials having two stable polarization states and thus may include capacitors and/or memory cells. Of ferroelectric materialsThe polarization state can be changed by applying a suitable programming voltage and remains (at least for a time) after the programming voltage is removed. Each polarization state has a different capacitance storing charge from the others and is ideally useful for writing (i.e., storing) and reading (i.e., determining) memory states without reversing the polarization state until it is desired to reverse such polarization state. Less desirably, in a certain memory having ferroelectric capacitors, the act of reading the memory state may reverse polarization. Thus, after the polarization state is determined, rewriting of the memory cell is performed to place the memory cell in a pre-read state immediately after its determination. Regardless, memory cells incorporating ferroelectric capacitors are ideally non-volatile due to the bistable nature of the ferroelectric material forming part of the capacitor.

A field effect transistor is another type of electronic component that can be used in a memory cell. These transistors include a pair of source/drain regions having a semiconductor channel region therebetween. A conductive gate is adjacent to and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The field effect transistor may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. The field effect transistor may be ferroelectric, with at least some portion of the gate construction (e.g., the gate insulator) comprising a ferroelectric material. The two different polarization states of the ferroelectric material in the transistor may be characterized by different threshold voltages (V) of the transistor_t) Or different channel conductivity at a selected operating voltage.

One type of volatile memory is Dynamic Random Access Memory (DRAM). It is used in modern computing architectures and can offer the advantages of simple structure, low cost, and fast speed compared to other types of memory. Currently, DRAMs typically have individual memory cells with one capacitor combined with one field effect transistor (so-called 1T-1C memory cells), where the capacitor is coupled to one of the source/drain regions of the transistor. One limitation of the scalability of the current 1T-1C configuration is that it is difficult to incorporate capacitors with sufficiently high capacitance into a highly integrated architecture.

Drawings

FIG. 1 is a schematic diagram of a 2T-1C memory cell.

FIG. 2 is a diagrammatic hybrid schematic and partial construction view of a memory circuit in accordance with an embodiment of the invention.

FIG. 3 is a hybrid configuration and partially schematic cross-sectional view taken through line 3-3 in FIG. 2.

Fig. 4 is a fragmentary cross-sectional view taken through line 4-4 in fig. 2.

Fig. 5 is a diagrammatic enlarged top view of the portion shown in fig. 2 and in fig. 4.

Fig. 6 is a cross-sectional view taken through line 6-6 in fig. 5.

Fig. 7 is a cross-sectional view taken through line 7-7 in fig. 5.

Fig. 8 is a cross-sectional view taken through line 8-8 in fig. 5.

Fig. 9 is a cross-sectional view taken through line 9-9 in fig. 5.

FIG. 10 is a diagrammatic hybrid schematic and partial construction view of a memory circuit.

Fig. 11 is a diagrammatic enlarged top view of a portion of fig. 10.

Fig. 12 is a cross-sectional view taken through line 12-12 in fig. 11.

Detailed Description

Embodiments of the invention include memory circuits comprising memory cells individually having at least two transistors and at least one capacitor. In some such embodiments, an individual memory cell has no more than a total of two transistors and no more than a total of one capacitor, and it is commonly referred to by those skilled in the art as a two transistor-one capacitor (2T-1C) memory cell and is shown schematically in fig. 1. Example 2T-1C memory cell MC has two transistors T1 and T2 and a capacitor CAP. A source/drain region of T1 is connected with a first node of the capacitor CAP, and another source/drain region of T1 is connected with a first comparison digit line (e.g., DL-T). The gate of T1 is connected to access line AL (i.e., word line). The source/drain region of T2 is connected with the second node of capacitor CAP, and the other source/drain region of T2 is connected with a second compare digit line (e.g., DL-C). The gate of T2 is connected to access line AL. The compare digit lines DL-T and DL-C extend to circuit 4, which compares the electrical properties (e.g., voltages) of the two to confirm the memory state of memory cell MC. The 2T-1C configuration of fig. 1 may be used in DRAM and/or other types of memory.

2-9 show memory circuits including 2T-1C memory cells 12, but memory circuits including memory cells individually having more than two transistors in total and/or more than one capacitor in total, whether existing or yet to be developed, are contemplated. Example memory circuitry includes a substrate, construction, or device 10 over a base substrate 15, which may include any one or more of conductive/conductor/conducting (i.e., conductive herein), semiconductive/semiconductive or insulative/insulator/insulative (i.e., electrically insulative herein) materials. Various materials have been formed on base substrate 15. The material may be alongside, vertically inside, or vertically outside of the material depicted in fig. 2-9. For example, other partially or fully fabricated components of the integrated circuit may be provided over, around, or somewhere within the base substrate 15. Control and/or other peripheral circuitry for operating components within the memory cell array may also be fabricated, and may or may not be entirely or partially within the array or sub-array. Furthermore, a plurality of sub-arrays may also be fabricated and operated independently, sequentially (in tandem), or otherwise with respect to each other. As used in this document, "subarrays" may also be considered arrays. An example base substrate 15 may comprise a suitably doped semiconductor material (e.g., monocrystalline silicon).

Construction 10 and memory circuitry in accordance with the present invention includes a pair of immediately adjacent memory arrays 300 and 400 (e.g., 2T-1C memory arrays) having a lateral space 250 therebetween. With respect to memory arrays 300 and 400, reference to "immediately adjacent" means that there are no other memory arrays in between. With respect to other regions, features, or components, reference to "immediately adjacent" also means that there are no other such regions, such features, or such components therebetween. Memory arrays 300 and 400 are shown to include respective perimeter profiles 305 and 405, shown as respective equally sized squares as an example. Of course, alternative sizes and shapes may be used, and the example arrays 300 and 400 need not be the same size and/or shape relative to each other. Additionally, perimeter profiles 305 and 405 may not be defined by physical features. Rather, as an example, it may include a narrow interface region/portion at the edge of the memory array where the repeated arrangement of individual memory cells stops and the space 250 begins, regardless of the space 250 not having the same repeated arrangement of components within the memory array 300 and/or 400. Only two side-by- side memory arrays 300 and 400 are shown in fig. 2, but it is likely that tens, hundreds, thousands, etc. will be provided to the left, right, and above and below the memory arrays 300 and 400 (not shown). The space 250 is shown with lateral expanses 255 and 265, which may be the same size relative to each other or may be different sizes from each other. The space 250 is shown as being quadrilateral in shape, although any alternative shape may be used.

The memory arrays 300 and 400 individually comprise memory cells 12 that individually comprise an upper vertically extending transistor TU (fig. 3 and 4) and a lower vertically extending transistor TL with a vertical capacitor 14 therebetween.

The memory arrays 300 and 400 include columns 16 of first comparison digit lines DL-C at an upper digit line level 17 that are over (in one embodiment, directly over) and electrically coupled (in one embodiment, directly electrically coupled) to columns 18 of upper vertically extending transistors TU. The memory arrays 300 and 400 include a column 20 of second comparison digit lines DL-T at a lower digit line level 19 that is below (in one embodiment, directly below) and electrically coupled (in one embodiment, directly electrically coupled) to a column 22 of lower vertically extending transistors TL. The example transistors TU and TL individually include upper source/drain regions 26, lower source/drain regions 28, and vertical channel regions 30 therebetween. Transistor gates 32 are shown on opposite sides of channel region 30, and by gatesSpaced therefrom is a pole insulator 34. The source/ drain regions 26, 28 may be heavily doped with conductivity-enhancing impurities to conduct, e.g., having a conductivity of at least 10²⁰Atom/cm³Dopant concentration of (a). Channel region 30 may be appropriately doped with a conductivity modifying impurity, possibly of the opposite conductivity type as the dopant in regions 26 and 28, e.g., to less than or equal to about 10¹⁶Atom/cm³The channel dopant concentration of (a). Conductive components, features, regions, and materials herein can comprise, consist essentially of, and/or consist of one or more of conductively doped semiconductive materials and/or metallic materials.

In one embodiment and as shown, the upper vertically extending transistor TU is vertical or within 10 ° of vertical and the lower vertically extending transistor TL is vertical or within 10 ° of vertical. In one such embodiment and as shown, the upper and lower vertically extending transistors in an individual memory cell 12 share a common linear axis 35 along which, in operation, current flows through the channels 30 of the respective upper and lower vertically extending transistors. In one embodiment and as shown, the lower source/drain region 28 of the lower transistor TL is electrically coupled directly to the comparison digit line DL-T, and in one embodiment, the upper source/drain region 26 of the upper transistor TU is electrically coupled directly to the comparison digit line DL-C. The vertical positions of DL-T and DL-C may be reversed.

The capacitor 14 includes an upper electrode 38, a lower electrode 40, and a capacitor insulator 41 therebetween. The lower capacitor electrode 40 is shown as a conductive pillar and the upper capacitor electrode 38 is shown as a downward facing container surrounding the upper portion of the lower electrode pillar 40. This relationship may be reversed, for example, with the lower capacitor electrode being the container facing upward and the upper capacitor electrode being the downwardly projecting post. Any alternative capacitor configuration may be used, for example, not including a container-like structure and/or not including a post.

Memory arrays 300 and 400 share first alternating rows 50, 51 and second alternating rows 60. Second alternating rows 60 are individually between immediately adjacent first alternating rows 50 and 51. Individual of the first alternating rows 50, 51 and the second alternating rows 60 have upper access lines 52 in an upper access line level 53 above lower access lines 54 in a lower access line level 55. The individual upper access lines 52 and lower access lines 54 are shown in FIG. 5 at least laterally offset from one another, at least for clarity of this figure. The lines 52 and 54 may not be so offset and need not be the same size and shape as each other.

The upper access lines 52 and the lower access lines 54 in the respective first alternating rows 50, 51 and the respective second alternating rows 60 are directly electrically coupled together by conductor interconnects 58. Such interconnects include horizontally extending portions 62 within the upper digit line level 17, directly above both the upper access lines 52 and the lower access lines 54 in the respective first 50, 51 or second 60 alternating rows. The individual first alternating rows 50 in the memory arrays 300 and 400 are directly coupled to each other across the space 250. The individual first alternating rows 51 in memory arrays 300 and 400 are directly electrically coupled to each other across space 250. The individual second alternating rows 60 in memory arrays 300 and 400 are not directly electrically coupled to each other across space 250.

The lower access lines 54 in alternating rows 50 of the first alternating rows 50, 51 extend from one of the memory arrays 300, 400 across the space 250 to the other of the memory arrays 300, 400. The lower access lines 54 in alternating rows 51 of the first alternating rows 50, 51 do not extend from one of the memory arrays 300, 400 across the space 250 to the other of the memory arrays 300, 400. Alternating rows 51 of the first alternating rows 50, 51 are individually between immediately adjacent ones of the alternating rows 50 of the first alternating rows 50, 51. The individual ones of alternate other first alternate rows 51 in the memory arrays 300, 400 are directly electrically coupled to each other across the space 250 by conductive interconnects 66. Such interconnects include one horizontally elongate portion 65 in space 250 in the upper digit line level 17 and another horizontally elongate portion 67 in space 250 in the upper access line level 53. Such further horizontal elongated portions 67 in the space 250 are directly above the lower access lines 54 in the immediately adjacent ones of the alternating rows 50 in the first alternating rows 50, 51. The individual conductor interconnect 58 and the conductive interconnect 66 can be end-to-end and/or otherwise integral with one another.

In one embodiment, a plurality of conductive vias 95 extend laterally within the space 250 from the upper digit line level 17 to the lower digit line level 19 (in one embodiment, from above the level 17 to below the level 19) between two immediately adjacent alternating rows 50, 51 of the first alternating rows 50, 51.

Example insulative materials 48 (e.g., silicon dioxide and/or silicon nitride) are shown encapsulating the various features and components described above.

In some embodiments, and unless stated otherwise independently of one or more aspects described above, a memory circuit includes a pair of immediately adjacent memory arrays (e.g., 300 and 400) having space (e.g., 250) laterally therebetween. However, any other attributes or aspects illustrated in the figures and/or described herein with respect to other embodiments may be used. The memory array individually comprises memory cells (e.g., 12) individually having upper vertically extending transistors (e.g., TUs) and lower vertically extending transistors (e.g., TLs) and vertical capacitors (e.g., 14) therebetween. The memory array includes individual rows (e.g., any two or more of rows 50, 51, 60) that (a) have upper access lines (e.g., 52) over and directly electrically coupled to lower access lines (e.g., 54), and (b) are directly electrically coupled to one another across the spaces. A lower access line in one of the rows (e.g., any of rows 50) extends from one of the memory arrays across the space to another of the memory arrays. Another of the rows (e.g., any of rows 51) includes a conductive interconnect (e.g., 66) including a horizontally extending portion (e.g., 67) laterally offset from the other row within the space.

In one embodiment, the upper access line is directly above the lower access line at least within the one and the other of the memory arrays. In one embodiment, the upper access lines in one row (e.g., 50) do not extend across the space from the one memory array to the other memory array. In one embodiment, the horizontally extending portions of the conductive interconnects are in a common horizontal plane (e.g., a horizontal plane as exemplified by level 53) with the horizontally extending portions of the upper access lines. In one embodiment, the horizontally extending portion of the conductive interconnect is within the one row (e.g., 67 within any one of the rows 50). In one such embodiment, the horizontally extending portion of the conductive interconnect is directly above the lower access line in the one row.

In one embodiment, the upper and lower access lines in an individual row are directly electrically coupled to each other with conductive material (e.g., 72 and/or 74) over the upper access line. In one such embodiment, such conductive material (e.g., 74) is directly above the upper access lines in the space. Additionally, in this latter embodiment, conductive material (e.g., 74) is directly above the lower access lines in the space. In one embodiment, the upper access lines and lower access lines in an individual row are directly electrically coupled to one another with a first conductive via (e.g., 71) that contacts an uppermost surface (e.g., 81) of the upper access line and a second conductive via (e.g., 73) that contacts an uppermost surface (e.g., 83) of the lower access line. In one such embodiment, the upper and lower access lines in an individual row are directly electrically coupled to one another with conductive material (e.g., 72, in combination with 74) over the upper access line and directly against an uppermost surface of each of the first and second conductive vias.

In one embodiment, the horizontally extending portions (e.g., 67) of the conductive interconnects are horizontally elongated. In one such embodiment, the horizontally elongated portions of the conductive interconnects are all laterally offset from another row (e.g., 51). In one embodiment, the memory cells are individually 2T-1C memory cells.

Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

In some embodiments, and unless stated otherwise independently of one or more aspects described above, a memory circuit comprises a pair of immediately adjacent memory arrays (e.g., 300 and 400) having a lateral space (e.g., 250) therebetween. However, any other attributes or aspects shown and/or described herein for other embodiments may be used. The memory array individually comprises memory cells (e.g., 12) individually having upper vertically extending transistors (e.g., TUs) and lower vertically extending transistors (e.g., TLs) and vertical capacitors (e.g., 14) therebetween. The memory array includes individual rows (e.g., any of rows 50, 51, or 60) that (a) have upper access lines (e.g., 52) over and directly electrically coupled to lower access lines (e.g., 54), and (b) are directly coupled to one another across the space. A lower access line in one of the rows (e.g., any of rows 50) extends from one of the memory arrays across the space to another of the memory arrays. Another of the rows (e.g., any of rows 51) includes a conductive interconnect (e.g., 66) including a horizontally elongated portion (e.g., 67) extending across a portion of the space and in and longitudinally aligned with the one row. Any other attributes or aspects shown and/or described herein for other embodiments may be used.

In some embodiments, the embodiments described above may provide advantages over the embodiments described below with respect to configuration 10a of fig. 10-12. Like numerals from the above-described embodiments have been used for like construction, features and materials. In many cases, conductive interconnects (e.g., 95 in fig. 5 and 7) are provided in regions between immediately adjacent memory arrays to interconnect circuitry above such arrays to circuitry below such arrays. As the rows of particular access lines extending between immediately adjacent arrays become closer together, the trend is for the available area between those rows for positioning array conductive vias for such electrical interconnections to become smaller. For example and by way of example only, fig. 10 and 11 show expanses 900 between immediately adjacent rows 50 and 51 that may be used for making such conductive via interconnects. The corresponding expanse 900 shown in fig. 2 and 5 in the embodiments described above may be significantly increased, in one embodiment approximately doubled, compared to that available in configuration 10 a.

Herein, "vertical," higher, "" upper, "" lower, "" top, "" bottom, "" above, "" below, "" in. "horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees) and may be relative to the substrate being processed during fabrication, and vertical is a direction generally orthogonal thereto. Reference to "exactly horizontal" refers to a direction along the main substrate surface (i.e., not forming degrees from that surface) and in which the processing substrate may be opposite during fabrication. Further, "vertical" and "horizontal" as used herein are generally vertical directions relative to each other, and are independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "vertically extending" refer to directions that deviate at least 45 ° from exactly horizontal. Additionally, "vertically extending" and "vertically extending" with respect to a field effect transistor are orientations with reference to the transistor channel length along which current flows when operating between source/drain regions. For bipolar junction transistors, "vertically extending" and "vertically extending" are orientations with reference to the base length along which current flows when operating between the emitter and collector.

Additionally, "directly above" and "directly below" require that there is at least some lateral overlap (i.e., horizontally) of the two recited zones/materials/components with respect to each other. Also, the use of "over" without "right before merely requires that some portion of the stated region/material/component above the other stated region/material/component be vertically outward from the other stated region/material/component (i.e., independent of whether there is any lateral overlap of the two stated regions/material/components). Similarly, use of "under" without "being ahead merely requires that some portion of a recited zone/material/component under another recited zone/material/component be vertically inward of the other recited zone/material/component (i.e., independent of whether there is any lateral overlap of the two recited zones/materials/components).

Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any event may be continuous or discontinuous over any material it overlies. Additionally, unless otherwise noted, each material may be formed using any suitable or yet to be developed technique, examples of which are atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

Additionally, "thickness" (the preceding non-directional adjectives), used alone, is defined as the average straight-line distance perpendicularly through a given material or region from the nearest surface of the immediately adjacent material or region of different composition. In addition, the various materials or regions described herein can have a substantially constant thickness or have a variable thickness. If there is a variable thickness, the thickness refers to an average thickness unless otherwise specified, and the material or region will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different components" only requires that those portions of the two discussed materials or regions that can be directly against each other be chemically and/or physically different, such as where the materials or regions are not uniform. If two recited materials or regions are not directly against each other, then "different compositions" merely requires that those portions of the two recited materials or regions that are closest to each other be chemically and/or physically different, where such materials or regions are not heterogeneous. In this document, a material, region or structure is "directly against" another material, region or structure when the stated materials, regions or structures are in at least some physical contact with respect to each other. In contrast, the absence of "directly" above, "on," "adjacent," "along," and "against" preceding encompasses "directly against" and configurations in which intervening materials, regions, or structures are not in physical contact with one another.

Herein, zone-material-components are "electrically coupled" with respect to each other if, in normal operation, an electrical current is able to flow continuously from one zone-material-component to another zone-material-component, and, when sufficiently producing subatomic positive and/or negative charges, flows predominantly by movement of the subatomic positive and/or negative charges. Another electronic component may be between and electrically coupled to the zone-material-component. In contrast, when a region-material-component is referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-component.

The use of "rows" and "columns" in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or will be formed. "Row" and "column" are used synonymously with respect to any series of regions, components, and/or features that are not related to function. In any case, the rows may be straight and/or curved and/or parallel and/or non-parallel with respect to each other, as may the columns. Further, the rows and columns may intersect at 90 ° or at one or more other angles with respect to each other.

Additionally, a "metallic material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any conductive metal compound.

Summary of the invention

In some embodiments, a memory circuit includes a pair of immediately adjacent memory arrays having a lateral space therebetween. The memory array individually includes memory cells individually having upper and lower vertically extending transistors and a vertical capacitor therebetween. The memory array includes individual rows that (a) have upper access lines above and directly electrically coupled to lower access lines, and (b) are directly electrically coupled to one another across the spaces. The lower access line in one of the rows extends from one of the memory arrays across the space to the other of the memory arrays. Another of the rows includes a conductive interconnect extending across a portion of the space. The conductive interconnects include horizontally extending portions laterally offset from the other row within the space.

In some embodiments, a memory circuit includes a pair of immediately adjacent memory arrays having a lateral space therebetween. The memory array individually includes memory cells individually having upper and lower vertically extending transistors and a vertical capacitor therebetween. The memory array includes individual rows that (a) have upper access lines above and directly electrically coupled to lower access lines, and (b) are directly electrically coupled to one another across the spaces. The lower access line in one of the rows extends from one of the memory arrays across the space to the other of the memory arrays. Another of the rows includes a conductive interconnect including a horizontally elongated portion extending across a portion of the space and in and longitudinally aligned with the one row.

In some embodiments, a memory circuit including a two transistor-capacitor (2T-1C) memory cell includes a pair of immediately adjacent 2T-1C memory arrays having a lateral space therebetween. The 2T-1C memory array individually comprises 2T-1C memory cells, the 2T-1C memory cells individually having upper and lower vertically extending transistors with a vertical capacitor therebetween. The 2T-1C memory array includes a column of first compare digit lines at an upper digit line level that is above and electrically coupled to a column of the upper vertically extending transistors. The 2T-1C memory array includes a column of second comparison digit lines at a lower digit line level that is below and electrically coupled to a column of the lower vertically extending transistors. The 2T-1C memory array shares first and second alternating rows. The second alternating rows are individually between immediately adjacent ones of the first alternating rows. The first alternating rows and the second alternating rows individually have upper access lines in an upper access line level that are above lower access lines in a lower access line level. The upper access lines and the lower access lines in the respective first alternating rows and the respective second alternating rows are directly electrically coupled together by conductor interconnects including horizontally extending portions within the upper digit line level directly above both the upper access lines and the lower access lines in the respective first alternating rows or second alternating rows. The individual first alternating rows in the 2T-1C memory array are directly electrically coupled to each other across the space. The individual second alternating rows in the 2T-1C memory array are not directly electrically coupled to each other across the space. The lower access lines in alternating ones of the first alternating rows extend from one of the 2T-1C memory arrays across the space to another one of the 2T-1C memory arrays. The lower access lines in alternating ones of the first alternating rows do not extend from one of the 2T-1C memory arrays across the space to another one of the 2T-1C memory arrays. Alternating other first alternating rows are individually between immediately adjacent ones of the alternating rows of the first alternating rows. Alternating other first alternating rows in the one 2T-1C memory array and the other 2T-1C memory array are individually electrically coupled directly to one another across the space by conductive interconnects including one horizontally elongated portion in the space in the upper digit line level and another horizontally elongated portion in the space in the upper access line level. The other horizontally elongate portion in the space is directly above the lower access line in an immediately adjacent alternate row of the first alternate row.