阅读说明：本技术 一种具有多稳态的忆阻纠缠非线性电路 (Memristor entanglement nonlinear circuit with multiple stable states ) 是由 雷腾飞 付海燕 李春彪 于 2019-11-14 设计创作，主要内容包括：本发明适用于电路领域,提供了一种具有多稳态的忆阻纠缠非线性电路,所述具有多稳态的忆阻纠缠非线性电路包括：第一、第二、第三以及第四通道,通过四个通道的电路连接,实现无量纲数学模型的模拟,采用电源V1,电源V2,电源V3以及电源V4与开关K1,开关K2,开关K3以及开关K4配合实现；若实现初值任意确定,可采用开关K1,开关K2,开关K3以及开关K4闭合,使其电容C1,电容C2,电容C3以及电容C4充电达到相应的电压值,实现电路多稳态的共存,电路结构简单,容易实现,可以产生多种状态波形,在不改变参数的情况下,将该输出信号作为载波信号,与目标信号通过相关算法调制,可达到保密通信、抗破解、图像加密等目的。(The invention is suitable for the field of circuits, and provides a memristor entangled nonlinear circuit with multiple stable states, which comprises: the first channel, the second channel, the third channel and the fourth channel are connected through circuits of the four channels to realize simulation of a dimensionless mathematical model, and the simulation is realized by matching a power supply V1, a power supply V2, a power supply V3, a power supply V4, a switch K1, a switch K2, a switch K3 and a switch K4; if the initial value is determined arbitrarily, the switch K1, the switch K2, the switch K3 and the switch K4 can be adopted to be closed, so that the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 of the circuit are charged to reach corresponding voltage values, multi-stable coexistence of the circuit is realized, the circuit structure is simple and easy to realize, various state waveforms can be generated, under the condition that parameters are not changed, the output signal is used as a carrier signal and is modulated with a target signal through a related algorithm, and the purposes of secret communication, cracking resistance, image encryption and the like can be achieved.)

1. A memristive entangled nonlinear circuit with multiple stable states, the memristive entangled nonlinear circuit comprising:

the output signal of the first channel is fed back to the input end of the first channel circuit and used as an input signal, the output signal of the first channel is also used as an input signal in the second channel circuit, and a previous-stage signal of the output signal of the first channel is used as an input signal of a trigonometric function converter S3 in the third channel circuit; the output signal of the second channel circuit is fed back to the input end of the second channel circuit as a path of input signal, the output signal of the previous stage of the output signal of the second channel circuit is used as the input signal of the first channel circuit, and is used as the input signal of the trigonometric function converter S1 in the first channel circuit, and is also used as the input signal of the multiplier A2 in the first channel, and is also used as a path of signal input of the fourth channel; the output signal of the third channel circuit is fed back to the input end of the third channel circuit, and the output signal of the previous stage of the output signal of the third channel circuit is amplified by three times and then serves as the input signal of the trigonometric function converter S2 in the second channel circuit; the output signal of the fourth channel circuit is used as two input ends of a multiplier A2 in the first channel, and the output of a multiplier A3 is used as one input signal of a multiplier A2, wherein the first, second, third and fourth channels realize the following dimensionless mathematical models:

wherein the content of the first and second substances,x、y、zin order to be a state variable, the state variable,a、b、c、d、hthe first, second, third and fourth channels and the fourth circuit realize the first, second, third and fourth functions in the dimensionless mathematical model in a time sharing mode.

2. The memristive entangled nonlinear circuit with multistability according to claim 1, wherein the memristive entangled nonlinear circuit with multistability comprises:

a first channel, which includes inverters U1, U2, an inverse integrator U3, multipliers a2, A3, a trigonometric function converter S1, resistors R1, R11, R12, R13, R14, R15, R16, R17, a capacitor C1, a power supply V1, and double-pole single-throw switches K1-1 and K1-2, wherein a pin 2 of the inverter U1 is connected with resistors R1, R11, R12, R13, and a resistor R14, the other end of the resistor R1 is connected with an output end of the multiplier a2, one input end of the multiplier a2 is connected with an output end of the multiplier A3, the other end of the resistor R13 is connected with an output end of the trigonometric function converter S1, the other end of the resistor R14 is connected with a pin 6 of the inverter U1, and a pin 6 of the inverter U1 is connected with an inverse pin 2 of the integrator U3 through a resistor R15; one end of a capacitor C1 is connected with a pin 2 of an inverting integrator U3, the other end of a capacitor C1 is connected with a pin 6 of the inverting integrator U3, and the pin 6 of the inverting integrator U3 is connected with a pin 2 of an inverter U2 through a resistor R16; pin 2 of the inverter U2 is connected with one end of a resistor R17, and the other end of the resistor R17 is connected with pin 6 of the inverter U2; two ends of a power supply V1 are connected to two ends of a capacitor C1 through double-pole single-throw, two switches of the double-pole single-throw are K1-1 and K1-2 respectively, and a pin 3 of a switch inverter U1, a pin 3 of a U2 of the inverter and a pin 3 of an inverse integrator U3 are grounded; pin 4 of the inverter U1, pin 4 of the inverter U2 and pin 4 of the inverse integrator U3 are connected with a negative voltage, pin 7 of the inverter U1, pin 7 of the inverter U2 and pin 7 of the inverse integrator U3 are connected with a positive voltage, the output end of the inverter U2 is a signal-x, and the output end of the inverse integrator U3 is a signal x;

a second channel, which comprises inverters U4, U5, an inverse integrator U6, a trigonometric function converter S2, resistors R21, R22, R23, R24, R25, R26, a power supply V2, a capacitor C2, and double-pole single-throw switches K2-1 and K2-2, wherein pin 2 of the inverter U4 is connected with resistors R21, R22, R27 and resistor R23, the other end of the resistor R27 is connected with the output end of the trigonometric function converter S2, the other end of the resistor R23 is connected with pin 6 of the inverter U4, and pin 6 of the inverter U4 is connected with pin 2 of the inverse integrator U6 through a resistor R24; the capacitor C2 has one end connected to pin 2 of the inverting integrator U6 and the other end connected to pin 6 of the inverting integrator U6, and the pin 6 of the inverting integrator U6 is connected to pin 2 of the inverter U5 through a resistor R25; pin 2 of the inverter U5 is connected with one end of a resistor R26, and the other end of the resistor R26 is connected with pin 6 of the inverter U5; two ends of a power supply V2 are connected to two ends of a capacitor C2 through a double-pole single-throw K2, two switches of the double-pole single-throw K2 are K2-1 and K2-2 respectively, and a pin 3 of an inverter U4, a pin 3 of an inverter U5 and a pin 3 of an inverting integrator U6 are grounded; pin 4 of the inverter U4, pin 4 of the inverter U5 and pin 4 of the inverse integrator U6 are connected with a negative voltage, pin 7 of the inverter U4, pin 7 of the inverter U5 and pin 7 of the inverse integrator U6 are connected with a positive voltage, the signal of the output end of the inverter U5 is-y, and the signal of the output end of the inverse integrator U6 is y;

a third channel which comprises inverters U9, U10, an inverse integrator U11, resistors R34, R35, R36, R37, R38, R39, a trigonometric function converter S3, a power supply V3, a capacitor C3 and double-pole single-throw switches K3-1 and K3-2, wherein a pin 2 of the inverter U9 is connected with the resistors R35 and R34 and the resistor R36, the other end of the resistor R35 is connected with the output end of the trigonometric function converter S3, the other end of the resistor R36 is connected with a pin 6 of the inverter U9, and a pin 6 of the inverter U9 is connected with a pin 2 of the inverse integrator U11 through the resistor R37; the capacitor C3 has one end connected to pin 2 of the inverting integrator U9 and the other end connected to pin 6 of the inverting integrator U11, and the pin 6 of the inverting integrator U11 is connected to pin 2 of the inverter U10 through a resistor R38; pin 2 of the inverter U10 is connected with one end of a resistor R39, and the other end of the resistor R39 is connected with pin 6 of the inverter U10; two ends of a power supply V3 are connected to two ends of a capacitor C3 through a double-pole single-throw K3, and two switches of the double-pole single-throw K3 are K3-1 and K3-2 respectively; pin 3 of inverter U9, pin 3 of inverter U10, and pin 3 of inverting integrator U11 are grounded; pin 4 of the inverter U9, pin 4 of the inverter U10 and pin 4 of the inverse integrator U11 are connected with a negative voltage, pin 7 of the inverter U9, pin 7 of the inverter U10 and pin 7 of the inverse integrator U11 are connected with a positive voltage, the signal of the output end of the inverter U10 is-z, and the signal of the output end of the inverse integrator U11 is z; and

a fourth channel, which comprises an inverter U7, an inverting integrator U8, resistors R2, R5, R4, a power supply V4, a capacitor C4, and double-pole single-throw switches K4-1 and K4-2, wherein a pin 2 of the inverter U7 is connected with the resistor R5 and the resistor R2, the other end of the resistor R5 is connected with a pin 6 of the inverter U7, and the pin 6 of the inverter U7 is connected with a pin 2 of the inverting integrator U8 through the resistor R4; one end of the capacitor C4 is connected with a pin 2 of the inverse integrator U8, and the other end of the capacitor C4 is connected with a pin 6 of the inverse integrator U8; two ends of a power supply V4 are connected to two ends of a capacitor C4 through a double-pole single-throw K4, and two switches of the double-pole single-throw K4 are K4-1 and K4-2 respectively; pin 3 of inverter U7 and pin 3 of inverting integrator U8 are grounded; pin 4 of the inverter U7 and pin 8 of the inverting integrator U11 are connected to a negative voltage, pin 7 of the inverter U7 and pin 8 of the inverting integrator U11 are connected to a positive voltage, and the output of the inverting integrator U8 is the signal w;

the other input end of the multiplier a2, the other end of the resistor R11, the input end of the trigonometric function converter, and the other end of the resistor R2 are all connected to the output end of the inverse integrator U6, the other end of the resistor R22 is connected to the output end of the inverter U5, the resistors R12 and R21 are connected to the output end of the inverter U2, the trigonometric function converter is connected to the output end of the inverse integrator U3, the output signal of the inverse integrator U11 is amplified by three times and then connected to the input end of the trigonometric function converter, the output signal of the inverter U10 is connected to the other end of the resistor R34, and both input ends of the multiplier A3 are connected to the output end of the inverse.

3. The memristive entangled nonlinear circuit with multiple stable states as claimed in claim 1, wherein the inverter U1, the inverter U2, the inverse integrator U3, the inverter U4, the inverter U5, the inverse integrator U6, the inverter U7, the inverter U8 and the inverse integrator U9 are all implemented by an op amp LM 741.

4. A memristive-entangled nonlinear circuit with multiple stable states as in claim 1, wherein the trigonometric function converter S1, the trigonometric function converter S2 and the trigonometric function converter S3 are all chip AD 639.

5. The memristive entangled nonlinear circuit with multiple stable states as claimed in claim 1, wherein the multiplier a2 and the multiplier A3 both use a chip AD 633.

6. A memristive entangled nonlinear circuit with multiple stable states as in claim 1, wherein the first channel circuit has a resistance of R11=100K Ω, R12=50K Ω, R13=5.56K Ω, R14= R15= R16= R17=10K Ω, a capacitance of C1=10 nF; the second channel circuit has the following characteristics that the resistance R21=100K Ω, R22=50K Ω, R27=55.6K Ω, R23= R24=10K Ω, R25= R26=33K Ω, and the capacitance C2=10 nF; a resistor R34=33.3K Ω, a resistor R35=55.6K Ω, a resistor R36=10K Ω, a resistor R37=100K Ω, a resistor R38= R39=50K Ω, a capacitor C3=100nF, a resistor R2=100K Ω, a resistor R5= R4=10K Ω, and a capacitor C3=0nF in the third channel circuit; a power supply V1= -12V-12; a power supply V2= -12V-12; a power supply V3= -12V-12; a power supply V4= -12V; VCC =15, VDD = -15V.

Technical Field

The invention belongs to the field of circuits, and particularly relates to a memristor entangled nonlinear circuit with multiple stable states.

Background

In 1971, when the relation among voltage, current, magnetic flux and charge was studied by professor zeriana, according to the mutual relation among them, a undefined and discovered circuit component, namely memristor, was discovered and used for representing the relation between charge and magnetic flux. Since the HP laboratory in 2008 successfully prepares the nano-scale memristor object for the first time, the wide attention of numerous scientific researchers is attracted. The unique volt-ampere characteristic and the memory characteristic of the memristor are easy to realize chaos and oscillation in a circuit, so that the memristor nonlinear circuit is widely interested in building the memristor nonlinear circuit, and particularly has a great development space in the aspects of memristor chaotic circuit, memristor neural synapse circuit and the like.

Two or more linear systems are entangled through some nonlinear functions to obtain the latest system with chaotic characteristics, the system is a chaotic entanglement system, a technical scheme capable of realizing a memristive entanglement circuit from the chaotic entanglement system does not exist in the prior art, and the multi-stable circuit is provided and designed to be chaotic secret encryption and the like, so that the chaotic secret encryption system has important significance.

Therefore, the design of the multi-stable circuit in the prior art is not mature enough, and is difficult to realize, so that the problem is urgently needed to be solved.

Disclosure of Invention

The embodiment of the invention aims to provide a memristor entangled nonlinear circuit with multiple stable states, and aims to solve the technical problems that the design of the multiple stable state circuit is not mature enough, the initial value is difficult to determine, and the circuit parameters are difficult to select in the prior art.

The embodiment of the invention is realized in such a way that the memristor entangled nonlinear circuit with multiple stable states comprises:

the output signal of the first channel is fed back to the input end of the first channel circuit and used as an input signal, the output signal of the first channel is also used as an input signal in the second channel circuit, and a previous-stage signal of the output signal of the first channel is used as an input signal of a trigonometric function converter S3 in the third channel circuit; the output signal of the second channel circuit is fed back to the input end of the second channel circuit as a path of input signal, the output signal of the previous stage of the output signal of the second channel circuit is used as the input signal of the first channel circuit, and is used as the input signal of the trigonometric function converter S1 in the first channel circuit, and is also used as the input signal of the multiplier A2 in the first channel, and is also used as a path of signal input of the fourth channel; the output signal of the third channel circuit is fed back to the input end of the third channel circuit, and the output signal of the previous stage of the output signal of the third channel circuit is amplified by three times and then serves as the input signal of the trigonometric function converter S2 in the second channel circuit; the output signal of the fourth channel circuit is used as two input ends of a multiplier A2 in the first channel, and the output of a multiplier A3 is used as one input signal of a multiplier A2, wherein the first, second, third and fourth channels realize the following dimensionless mathematical models:

wherein the content of the first and second substances,x、y、zin order to be a state variable, the state variable,a、b、c、d、hthe first, second, third and fourth channels and the fourth circuit realize the first, second, third and fourth functions in the dimensionless mathematical model in a time sharing mode.

The memristor entangled nonlinear circuit with the multiple stable states provided by the embodiment of the invention has the advantages of reliable and stable circuit performance, simple circuit structure and easy realization, can realize the design of the multiple stable circuits, is suitable for college circuits, automatic control principle experiment teaching and the like, and has important engineering value in the fields of secret communication, electromechanical coupling systems and the like.

Drawings

FIG. 1 is a circuit diagram of a memristive entangled nonlinear circuit with multiple stable states according to an embodiment of the present invention;

fig. 2 shows an x-y output phase diagram of the circuit when V1=1V, V2=2V, V3=0.5V, and V4=1V in the embodiment of the present invention;

fig. 3 shows an x-z output phase diagram of the circuit with V1=1V, V2=2V, V3=0.5V, and V4=1V in an embodiment of the invention;

fig. 4 shows the circuit when V1=1V, V2=2V, V3=0.5V, and V4=1V in the embodiment of the present inventiony-zOutputting a phase diagram;

fig. 5 shows the circuit when V1=1V, V2=2V, V3=0.5V, and V4=1V in the embodiment of the present inventionx-wOutputting a phase diagram;

fig. 6 shows the circuit when V1=1V, V2=2V, V3=0.5V, and V4= -6V in the embodiment of the present inventionx-yOutputting a phase diagram;

fig. 7 shows a circuit with V1=1V, V2=2V, V3=0.5V, and V4= -6V in the embodiment of the present inventionx-zOutputting a phase diagram;

fig. 8 shows a circuit with V1=1V, V2=2V, V3=0.5V, and V4= -6V in the embodiment of the present inventiony-zAnd outputting a phase diagram.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms unless otherwise specified. These terms are only used to distinguish one element from another. For example, a first channel may be referred to as a second channel, and similarly, a second channel may be referred to as a first channel, without departing from the scope of the present application.

Fig. 1 shows a circuit diagram of a memristive entangled nonlinear circuit with multiple stable states, as shown in fig. 1, and includes:

the output signal of the first channel is fed back to the input end of the first channel circuit and used as an input signal, the output signal of the first channel is also used as an input signal in the second channel circuit, and a previous-stage signal of the output signal of the first channel is used as an input signal of a trigonometric function converter S3 in the third channel circuit; the output signal of the second channel circuit is fed back to the input end of the second channel circuit as a path of input signal, the output signal of the previous stage of the output signal of the second channel circuit is used as the input signal of the first channel circuit, and is used as the input signal of the trigonometric function converter S1 in the first channel circuit, and is also used as the input signal of the multiplier A2 in the first channel, and is also used as a path of signal input of the fourth channel; the output signal of the third channel circuit is fed back to the input end of the third channel circuit, and the output signal of the previous stage of the output signal of the third channel circuit is amplified by three times and then serves as the input signal of the trigonometric function converter S2 in the second channel circuit; the output signal of the fourth channel circuit is used as two input ends of a multiplier A2 in the first channel, and the output of a multiplier A3 is used as one input signal of a multiplier A2, wherein the first, second, third and fourth channels realize the following dimensionless mathematical models:

wherein the content of the first and second substances,x、y、zin order to be a state variable, the state variable,a、b、c、d、hthe first, second, third and fourth channels and the fourth circuit realize the first, second, third and fourth functions in the dimensionless mathematical model in a time sharing mode.

In the embodiment of the present invention, the first channel includes inverters U1, U2, inverse integrator U3, multipliers a2, A3, trigonometric function converter S1, resistors R1, R11, R12, R13, R14, R15, R16, R17, capacitor C1, power supply V1, and double-pole single-throw switches K1-1 and K1-2, where pin 2 of inverter U1 is connected to resistors R1, R11, R12, R13, and resistor R14, the other end of resistor R1 is connected to the output end of multiplier a2, one input end of multiplier a2 is connected to the output end of multiplier A3, the other end of resistor R13 is connected to the output end of trigonometric function converter S1, the other end of resistor R14 is connected to pin 6 of inverter U1, and pin 6 of inverter U1 is connected to the inverse integrator U3 through resistor R15; one end of a capacitor C1 is connected with a pin 2 of an inverting integrator U3, the other end of a capacitor C1 is connected with a pin 6 of the inverting integrator U3, and the pin 6 of the inverting integrator U3 is connected with a pin 2 of an inverter U2 through a resistor R16; pin 2 of the inverter U2 is connected with one end of a resistor R17, and the other end of the resistor R17 is connected with pin 6 of the inverter U2; two ends of a power supply V1 are connected to two ends of a capacitor C1 through double-pole single-throw, two switches of the double-pole single-throw are K1-1 and K1-2 respectively, and a pin 3 of a switch inverter U1, a pin 3 of a U2 of the inverter and a pin 3 of an inverse integrator U3 are grounded; pin 4 of the inverter U1, pin 4 of the inverter U2 and pin 4 of the inverse integrator U3 are connected with a negative voltage, pin 7 of the inverter U1, pin 7 of the inverter U2 and pin 7 of the inverse integrator U3 are connected with a positive voltage, the output end of the inverter U2 is a signal-x, and the output end of the inverse integrator U3 is a signal x; a second channel, which comprises inverters U4, U5, an inverse integrator U6, a trigonometric function converter S2, resistors R21, R22, R23, R24, R25, R26, a power supply V2, a capacitor C2, and double-pole single-throw switches K2-1 and K2-2, wherein pin 2 of the inverter U4 is connected with resistors R21, R22, R27 and resistor R23, the other end of the resistor R27 is connected with the output end of the trigonometric function converter S2, the other end of the resistor R23 is connected with pin 6 of the inverter U4, and pin 6 of the inverter U4 is connected with pin 2 of the inverse integrator U6 through a resistor R24; the capacitor C2 has one end connected to pin 2 of the inverting integrator U6 and the other end connected to pin 6 of the inverting integrator U6, and the pin 6 of the inverting integrator U6 is connected to pin 2 of the inverter U5 through a resistor R25; pin 2 of the inverter U5 is connected with one end of a resistor R26, and the other end of the resistor R26 is connected with pin 6 of the inverter U5; two ends of a power supply V2 are connected to two ends of a capacitor C2 through a double-pole single-throw K2, two switches of the double-pole single-throw K2 are K2-1 and K2-2 respectively, and a pin 3 of an inverter U4, a pin 3 of an inverter U5 and a pin 3 of an inverting integrator U6 are grounded; pin 4 of the inverter U4, pin 4 of the inverter U5 and pin 4 of the inverse integrator U6 are connected with a negative voltage, pin 7 of the inverter U4, pin 7 of the inverter U5 and pin 7 of the inverse integrator U6 are connected with a positive voltage, the signal of the output end of the inverter U5 is-y, and the signal of the output end of the inverse integrator U6 is y; a third channel which comprises inverters U9, U10, an inverse integrator U11, resistors R34, R35, R36, R37, R38, R39, a trigonometric function converter S3, a power supply V3, a capacitor C3 and double-pole single-throw switches K3-1 and K3-2, wherein a pin 2 of the inverter U9 is connected with the resistors R35 and R34 and the resistor R36, the other end of the resistor R35 is connected with the output end of the trigonometric function converter S3, the other end of the resistor R36 is connected with a pin 6 of the inverter U9, and a pin 6 of the inverter U9 is connected with a pin 2 of the inverse integrator U11 through the resistor R37; the capacitor C3 has one end connected to pin 2 of the inverting integrator U9 and the other end connected to pin 6 of the inverting integrator U11, and the pin 6 of the inverting integrator U11 is connected to pin 2 of the inverter U10 through a resistor R38; pin 2 of the inverter U10 is connected with one end of a resistor R39, and the other end of the resistor R39 is connected with pin 6 of the inverter U10; two ends of a power supply V3 are connected to two ends of a capacitor C3 through a double-pole single-throw K3, and two switches of the double-pole single-throw K3 are K3-1 and K3-2 respectively; pin 3 of inverter U9, pin 3 of inverter U10, and pin 3 of inverting integrator U11 are grounded; pin 4 of the inverter U9, pin 4 of the inverter U10 and pin 4 of the inverse integrator U11 are connected with a negative voltage, pin 7 of the inverter U9, pin 7 of the inverter U10 and pin 7 of the inverse integrator U11 are connected with a positive voltage, the signal of the output end of the inverter U10 is-z, and the signal of the output end of the inverse integrator U11 is z; and a fourth channel, which comprises an inverter U7, an inverting integrator U8, resistors R2, R5, R4, a power supply V4, a capacitor C4 and double-pole single-throw switches K4-1 and K4-2, wherein a pin 2 of the inverter U7 is connected with the resistor R5 and the resistor R2, the other end of the resistor R5 is connected with a pin 6 of the inverter U7, and the pin 6 of the inverter U7 is connected with a pin 2 of the inverting integrator U8 through the resistor R4; one end of the capacitor C4 is connected with a pin 2 of the inverse integrator U8, and the other end of the capacitor C4 is connected with a pin 6 of the inverse integrator U8; two ends of a power supply V4 are connected to two ends of a capacitor C4 through a double-pole single-throw K4, and two switches of the double-pole single-throw K4 are K4-1 and K4-2 respectively; pin 3 of inverter U7 and pin 3 of inverting integrator U8 are grounded; pin 4 of the inverter U7 and pin 8 of the inverting integrator U11 are connected to a negative voltage, pin 7 of the inverter U7 and pin 8 of the inverting integrator U11 are connected to a positive voltage, and the output of the inverting integrator U8 is the signal w; the other input end of the multiplier a2, the other end of the resistor R11, the input end of the trigonometric function converter, and the other end of the resistor R2 are all connected to the output end of the inverse integrator U6, the other end of the resistor R22 is connected to the output end of the inverter U5, the resistors R12 and R21 are connected to the output end of the inverter U2, the trigonometric function converter is connected to the output end of the inverse integrator U3, the output signal of the inverse integrator U11 is amplified by three times and then connected to the input end of the trigonometric function converter, the output signal of the inverter U10 is connected to the other end of the resistor R34, and both input ends of the multiplier A3 are connected to the output end of the inverse.

In the multi-stable memristor entangled nonlinear circuit provided by the embodiment of the invention, the circuit structure is simple and easy to realize, a dimensionless mathematical model is simulated through the circuit structure of four channels, various state waveforms can be generated, the output signal is used as a carrier signal under the condition of not changing parameters, and the carrier signal and a target signal are modulated through a related algorithm, so that the purposes of secret communication, cracking resistance, image encryption and the like can be achieved.

In the embodiment of the present invention, in the first channel circuit, the resistance R11=100K Ω, R12=50K Ω, R13=5.56K Ω, R14= R15= R16= R17=10K Ω, and the capacitance C1=10 nF; the second channel circuit has the following characteristics that the resistance R21=100K Ω, R22=50K Ω, R27=55.6K Ω, R23= R24=10K Ω, R25= R26=33K Ω, and the capacitance C2=10 nF; a resistor R34=33.3K Ω, a resistor R35=55.6K Ω, a resistor R36=10K Ω, a resistor R37=100K Ω, a resistor R38= R39=50K Ω, a capacitor C3=100nF, a resistor R2=100K Ω, a resistor R5= R4=10K Ω, and a capacitor C3=0nF in the third channel circuit; a power supply V1= -12V-12; a power supply V2= -12V-12; a power supply V3= -12V-12; a power supply V4= -12V; VCC =15, VDD = -15V. An operational amplifier LM741 is adopted by the inverter U1, the inverter U2, the inverse integrator U3, the inverter U4, the inverter U5, the inverse integrator U6, the inverter U7, the inverter U8 and the inverse integrator U9. The trigonometric function converter S1, the trigonometric function converter S2 and the trigonometric function converter S3 all employ a chip AD 639. Both multiplier a2 and multiplier A3 employ chip AD 633. The selection of the above components is only one embodiment of the present invention, and those skilled in the art can select components autonomously according to actual implementation conditions to achieve corresponding purposes.

Fig. 2 shows the embodiment of the present invention in fig. 1 when V1=1V, V2=2V, V3=0.5V, and V4=1Vx-yFig. 3 shows the output phase diagram of fig. 1 when V1=1V, V2=2V, V3=0.5V, and V4=1V in the embodiment of the present inventionx-zFig. 4 shows the output phase diagram of fig. 1 when V1=1V, V2=2V, V3=0.5V, and V4=1V in the embodiment of the present inventiony-zFig. 5 shows the output phase diagram of fig. 1 when V1=1V, V2=2V, V3=0.5V, and V4=1V in the embodiment of the present inventionx-wFig. 6 shows the output phase diagram of fig. 1 when V1=1V, V2=2V, V3=0.5V, and V4= -6V in the embodiment of the present inventionx-yFig. 7 shows the output phase diagram of fig. 1 when V1=1V, V2=2V, V3=0.5V, and V4= -6V in the embodiment of the present inventionx-zOutput phase diagram, FIG. 8 shows an implementation of the inventionFig. 1 for example with V1=1V, V2=2V, V3=0.5V, and V4= -6Vy-zAnd outputting a phase diagram. As can be seen from fig. 2 to 8, for the implementation of multi-stable coexistence, the power supply V1, the power supply V2, the power supply V3, the power supply V4, the switch K1, the switch K2, the switch K3, and the switch K4 may be used in cooperation, and if the initial value is determined arbitrarily, the switch K1, the switch K2, the switch K3, and the switch K4 may be closed, so that the capacitor C1, the capacitor C2, the capacitor C3, and the capacitor C4 may be charged to reach corresponding voltage values.

In the entangled nonlinear circuit with multiple stable states provided by the embodiment of the invention, the coexistence of multiple stable states of the circuit can be realized through the matching adjustment among the resistors, the switches and the capacitors, the circuit structure is simple and easy to realize, a dimensionless mathematical model is simulated through the circuit structure of four channels, various state waveforms can be generated, and the output signal is used as a carrier signal and modulated with a target signal through a related algorithm under the condition of not changing parameters, so that the purposes of secret communication, anti-cracking, image encryption and the like can be achieved.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.