Latch circuit
阅读说明:本技术 锁存器电路 (Latch circuit ) 是由 林见儒 雷良焕 于 2018-11-08 设计创作,主要内容包括:一种锁存器电路,包含输入电路、输出电路和开关电路。输入电路用于接收时钟信号和数据信号。输出电路耦接于输入电路,并耦接于第一电源端和第二电源端之间,用于依据时钟信号和数据信号产生输出信号。开关电路耦接于输出电路,其中当数据信号的电压电平切换时,开关电路断开第一电源端和第二电源端之间的导电路径。(A latch circuit includes an input circuit, an output circuit, and a switching circuit. The input circuit is used for receiving a clock signal and a data signal. The output circuit is coupled to the input circuit, coupled between the first power source terminal and the second power source terminal, and configured to generate an output signal according to the clock signal and the data signal. The switching circuit is coupled to the output circuit, wherein the switching circuit breaks a conductive path between the first power source terminal and the second power source terminal when a voltage level of the data signal is switched.)
1. A latch circuit, comprising:
a switch circuit, coupled between a first power source terminal and a second power source terminal, including a positive phase output terminal and a negative phase output terminal;
an input circuit, coupled to the forward output terminal and the reverse output terminal, for receiving a clock signal and a data signal, and for turning on the forward output terminal and the second power terminal according to the clock signal and the data signal; and
the output circuit is coupled to the positive phase output end and the negative phase output end, coupled to the first power end and the second power end, and used for conducting the positive phase output end and the first power end according to the clock signal and the data signal so as to generate an output signal at the positive phase output end;
wherein the switching circuit breaks an electrically conductive path between the first power supply terminal and the second power supply terminal when the voltage level of the data signal switches.
2. The latch circuit of claim 1, wherein the output circuit is further configured to generate an inverted output signal that is inverted with respect to the output signal,
wherein the output circuit controls a cross point of the output signal and the inverted output signal when the voltage level of the clock signal is switched.
3. The latch circuit of claim 1, wherein the output circuit comprises:
a first transistor coupled between the first power terminal and a first node, and having a control terminal coupled to the positive phase output terminal;
a second transistor, coupled between the first power terminal and a second node, and having a control terminal coupled to the inverted output terminal;
a third transistor, coupled between the second power terminal and a third node, and having a control terminal coupled to the positive phase output terminal; and
a fourth transistor, coupled between the second power terminal and a fourth node, and having a control terminal coupled to the inverted output terminal.
4. The latch circuit of claim 3, wherein the switch circuit comprises:
a fifth transistor, coupled between the first node and the inverted output terminal, and having a control terminal for receiving the data signal;
a sixth transistor, coupled between the second node and the positive phase output terminal, having a control terminal for receiving an inverted data signal inverted from the data signal;
a seventh transistor, coupled between the third node and the inverted output terminal, having a control terminal for receiving an inverted clock signal inverted from the clock signal; and
an eighth transistor, coupled between the fourth node and the positive phase output terminal, having a control terminal for receiving the inverted clock signal.
5. The latch circuit of claim 1, wherein the output circuit comprises:
a first transistor coupled between a first node and the inverted output terminal, and having a control terminal coupled to the normal output terminal;
a second transistor coupled between a second node and the positive phase output terminal, and having a control terminal coupled to the negative phase output terminal;
a third transistor coupled between a third node and the inverted output terminal, and having a control terminal coupled to the non-inverted output terminal; and
a fourth transistor coupled between a fourth node and the positive phase output terminal, and having a control terminal coupled to the negative phase output terminal.
6. The latch circuit of claim 5, wherein the switch circuit comprises:
a fifth transistor, coupled between the first node and the first power terminal, and having a control terminal for receiving the data signal;
a sixth transistor, coupled between the second node and the first power terminal, having a control terminal for receiving an inverted data signal inverted from the data signal;
a seventh transistor, coupled between the third node and the second power terminal, having a control terminal for receiving the clock signal; and
an eighth transistor, coupled between the fourth node and the second power terminal, having a control terminal for receiving the clock signal.
7. A latch circuit as claimed in claim 3 or 5, wherein the output circuit is further arranged to generate an inverted output signal which is inverted with respect to the output signal,
wherein the output signal rises to a cross point of the output signal and the inverted output signal over a time period negatively related to an aspect ratio of the second transistor when the voltage level of the clock signal switches.
8. A latch circuit as claimed in claim 4 or 6, wherein the input circuit comprises:
a ninth transistor, a control terminal of which is used for receiving the clock signal;
a tenth transistor having a control terminal for receiving the data signal, wherein the ninth transistor and the tenth transistor are serially connected between the inverted output terminal and the second power terminal;
an eleventh transistor, a control terminal of which is used for receiving the clock signal; and
a twelfth transistor having a control terminal for receiving the inverted data signal, wherein the eleventh transistor and the twelfth transistor are serially connected between the non-inverting output terminal and the second power terminal.
9. A latch circuit as claimed in claim 8, wherein the fifth transistor switches to an off state to break the conductive path before the ninth transistor switches to an on state.
10. The latch circuit of claim 8 wherein the data signal is switched from a first low voltage level to a first high voltage level before the clock signal is switched from a second low voltage level to a second high voltage level.
Technical Field
The present disclosure relates to a latch circuit, and more particularly, to a latch circuit having a switch circuit capable of preventing a short-circuit current.
Background
When the output signal of the conventional latch circuit is transited (e.g., from a value of 1 to a value of 0), the coupled high voltage source and low voltage source are conducted to each other, thereby generating a short-circuit current. The short circuit current may cause ripple (ripple) in the output signal, which may damage components of the back-end circuit (e.g., digital-to-analog converter). In addition, the ripple causes a signal to noise ratio (signal to noise ratio) to decrease, and a total harmonic distortion (total harmonic distortion) to increase.
Disclosure of Invention
The present disclosure provides a latch circuit including an input circuit, an output circuit, and a switch circuit. The input circuit is used for receiving a clock signal and a data signal. The output circuit is coupled to the input circuit, coupled between the first power source terminal and the second power source terminal, and configured to generate an output signal according to the clock signal and the data signal. The switching circuit is coupled to the output circuit, wherein the switching circuit breaks a conductive path between the first power source terminal and the second power source terminal when a voltage level of the data signal is switched.
The latch circuit can improve the signal-to-noise ratio and reduce the total harmonic distortion.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the disclosure more comprehensible, the following description is given:
fig. 1 is a simplified functional block diagram of a digital-to-analog conversion unit according to an embodiment of the disclosure.
Fig. 2 is a circuit schematic of a latch circuit according to an embodiment of the present disclosure.
FIG. 3 is a simplified timing diagram of an embodiment of an operation of the latch circuit of FIG. 2.
Fig. 4 is a partially enlarged timing variation diagram of the first transition stage.
Fig. 5 is a circuit schematic of a latch circuit according to another embodiment of the present disclosure.
Detailed Description
The embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.
Fig. 1 is a simplified functional block diagram of a digital-to-
The
In practice, the digital-to-
Fig. 2 is a circuit diagram of a
In addition, the
The
The
The
The
In other words, the ninth transistor M9 and the tenth transistor M10 are disposed in series between the inverting output terminal QB and the second power terminal Vn2, and the eleventh transistor M11 and the twelfth transistor M12 are disposed in series between the non-inverting output terminal Q and the second power terminal Vn 2.
In some embodiments, the positions of the ninth transistor M9 and the tenth transistor M10 may be interchanged with each other, and the positions of the eleventh transistor M11 and the twelfth transistor M12 may also be interchanged with each other.
In practice, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 may be implemented with various suitable P-type transistors. The third transistor M3, the fourth transistor M4, and the seventh through twelfth transistors M7 through M12 may be implemented by various suitable N-type transistors.
FIG. 3 is a timing diagram of an embodiment of the operation of the
When the data signal Din is switched from the first low level L1 to the first high level H1, the clock signal Clk is maintained at the second low level L2. At this time, the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, and the eleventh transistor M11 are turned on, and the second transistor M2, the third transistor M3, the fifth transistor M5, the ninth transistor M9, and the twelfth transistor M12 are turned off.
Then, the clock signal Clk is switched from the second low voltage level L2 to the second high voltage level H2. Therefore, the ninth transistor M9 and the eleventh transistor M11 are switched to the on state, and the seventh transistor M7 and the eighth transistor M8 are switched to the off state. Therefore, the inverted output signal Sb of the inverted output terminal QB is equal to the second reference voltage VSS, So that the output signal So of the non-inverting output terminal Q is equal to the first reference voltage VDD (i.e., the non-inverting output terminal Q outputs a
In other words, the data signal Din is switched from the first low voltage level L1 to the first high voltage level H1 before the clock signal Clk is switched from the second low voltage level L2 to the second high voltage level H2.
Therefore, the fifth transistor M5 is switched to the off state first, and the ninth transistor M9 is switched to the on state, so that the conducting path from the first power terminal Vn1 to the second power terminal Vn2 is kept open during the first
In the first sustain phase TH1, the data signal Din is maintained at the first high voltage level H1. At this time, even though the clock signal Clk switches its voltage level, the output signal So is maintained at the first reference voltage VDD, and the inverted output signal Sb is maintained at the second reference voltage VSS (i.e., the positive phase output terminal Q stores a
In the second transition period TR2, when the data signal Din is switched from the first high voltage level H1 to the first low voltage level L1, the clock signal Clk is maintained at the second low voltage level L2. At this time, the second transistor M2, the third transistor M3, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, and the twelfth transistor M12 are in an on state, and the first transistor M1, the fourth transistor M4, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are in an off state.
Then, the clock signal Clk is switched from the second low voltage level L2 to the second high voltage level H2. Therefore, the ninth transistor M9 and the eleventh transistor M11 are switched to the on state, and the seventh transistor M7 and the eighth transistor M8 are switched to the off state. Therefore, the output signal So of the positive phase output terminal Q is equal to the second reference voltage VSS, such that the inverted output signal Sb of the inverted output terminal QB is equal to the first reference voltage VDD (i.e., the positive phase output terminal Q outputs a
In other words, the data signal Din is switched from the first high voltage level H1 to the first low voltage level L1 before the clock signal Clk is switched from the second low voltage level L2 to the second high voltage level H2.
Therefore, the sixth transistor M6 is switched to the off state first, and the eleventh transistor M11 is switched to the on state, so that the conducting path from the first power terminal Vn1 to the second power terminal Vn2 is kept open during the second transition period TR 2. Thus, a short-circuit current flowing from the first power terminal Vn1 to the second power terminal Vn2 is prevented.
In addition, in the second transition period TR2, after the voltage of the data signal Din changes and before the voltage of the clock signal Clk changes, the non-inverting output terminal Q is in a floating state for a short time because the sixth transistor M6 is switched to an off state. However, since the
In the second sustain period TH2, the data signal Din is maintained at the first low voltage level L1. At this time, even though the clock signal Clk switches its voltage level, the output signal So is maintained at the second reference voltage VSS, and the inverted output signal Sb is maintained at the first reference voltage VDD (i.e., the positive phase output terminal Q stores a
In the present embodiment, the position of the cross point (cross point) of the output signal So and the inverted output signal Sb can be controlled by adjusting the width-to-length ratio of the first transistor M1 and/or the second transistor M2, and the following description will be made with reference to fig. 2 and fig. 4. Fig. 4 is a partially enlarged timing diagram of the first
By adjusting the width-to-length ratio (width-to-length ratio) of the second transistor M2, the reaction time required for the second transistor M2 to switch from the off state to the on state and the charging speed of the second transistor M2 to the positive phase output terminal Q can be controlled. In detail, the reaction time and the charging speed of the second transistor M2 are both inversely related to the width-to-length ratio of the second transistor M2.
Therefore, in the first transition stage TR1, when the voltage level of the clock signal Clk is switched, the time length T1 required for the output signal So to rise to the crossing point is inversely related to the width-to-length ratio of the second transistor T2.
Similarly, in the second transition period TR2, when the voltage level of the clock signal Clk switches, the length of time required for the inverted output signal Sb to rise to the crossing point is inversely related to the width-to-length ratio of the first transistor T1.
If the
Similarly, if
Fig. 5 is a circuit schematic of a latch circuit 500 according to another embodiment of the present disclosure. Latch circuit 500 may be
The output circuit 520 includes first to fourth transistors M1 to M4. The first transistor M1 is coupled between the first node N1 and the inverted output terminal QB, and has a control terminal coupled to the non-inverted output terminal Q. The second transistor M2 is coupled between the second node N2 and the non-inverting output terminal Q, and has a control terminal coupled to the inverting output terminal QB. The third transistor M3 is coupled between the third node N3 and the inverted output terminal QB, and has a control terminal coupled to the non-inverted output terminal Q. The fourth transistor M4 is coupled between the fourth node N4 and the non-inverting output terminal Q, and has a control terminal coupled to the inverting output terminal QB.
The switch circuit 530 includes fifth to eighth transistors M5 to M8. The fifth transistor M5 is coupled between the first node N1 and the first power terminal Vn1, and has a control terminal for receiving the data signal Din. The sixth transistor M6 is coupled between the second node N2 and the first power terminal Vn1, and has a control terminal for receiving the inverted data signal Dip. The seventh transistor M7 is coupled between the third node N3 and the second power terminal Vn2, and has a control terminal for receiving the inverted clock signal Clkb. The eighth transistor M8 is coupled between the fourth node N4 and the second power terminal Vn2, and has a control terminal for receiving the inverted clock signal Clkb.
The operation and advantages of the latch circuit 500 and the connection of other elements are similar to those of the
In summary, the
In other words, the
Certain terms are used throughout the description and following claims to refer to particular components. However, as one of ordinary skill in the art will appreciate, identical components may be referred to by different names. The description and the claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" as used herein includes any direct or indirect connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.
As used herein, the description of "and/or" includes any combination of one or more of the items listed. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.
The above are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made by the claims of the present disclosure should be covered by the scope of the present disclosure.
Description of the symbols
100: digital-to-analog conversion unit
110. 120, 200: latch circuit
130: digital-to-analog converter
210: input circuit
220. 520, the method comprises the following steps: output circuit
230. 530: switching circuit
Iref1 to Iref 2: current source
M1-M12: first to twelfth transistors
N1-N6: first to sixth nodes
N1, N2, P1, P2: transistor with a metal gate electrode
Clk: clock signal
Clkb: inverted clock signal
Din: data signal
Dip: inverted data signal
Fb: feedback signal
Fp: inverted feedback signal
Q: normal phase output end
QB: inverting output terminal
Vn 1-Vn 2: first power supply terminal to second power supply terminal
VDD: a first reference voltage
VSS: second reference voltage
So: output signal
Sb: inverted output signal
TR 1-TR 2: first to second transition stages
TH 1-TH 2: first maintenance stage to second maintenance stage
T1: length of time
L1-L2: first to second low voltage levels
H1-H2: first to second high voltage levels.
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