阅读说明：本技术 跨导放大器和芯片 (Transconductance amplifier and chip ) 是由 王文祺 于 2019-09-26 设计创作，主要内容包括：本申请公开了一种跨导放大器以及相关芯片,所述种跨导放大器用来依据正端输入电压(V<Sub>IP</Sub>)与负端输入电压(V<Sub>IN</Sub>)产生输出电流,跨导放大器包括：输入级(102),接收正端输入电压与负端输入电压并产生正端输出电流(I<Sub>OP</Sub>)与负端输出电流(I<Sub>ON</Sub>),输入级包括：第一晶体管(110),其闸极耦接至正端输入电压；第二晶体管(120),其闸极耦接至负端输入电压；第一电阻(109),串接于第一晶体管和第二晶体管之间；第三晶体管(114),第三晶体管的源极耦接至第一电阻和第一晶体管之间,第三晶体管的漏极用以输出正端输出电流；以及第四晶体管(124),第四晶体管的源极耦接至第一电阻和第二晶体管之间,第四晶体管的漏极用以输出负端输出电流。(A transconductance amplifier for relying on a positive input voltage (V) and related chip IP ) Input voltage (V) with negative terminal IN ) Generating an output current, the transconductance amplifier comprising: an input stage (102) receiving a positive side input voltage and a negative side input voltage and generating a positive side output current (I) OP ) And negative terminal output current (I) ON ) The input stage includes: a first transistor (110) having a gate coupled to the positive side input voltage; a second transistor (120) having a gate coupled to the negative side input voltage; a first resistor (109) connected in series between the first transistor and the second transistor; a third transistor (114), a source of the third transistor is coupled between the first resistor and the first transistor, and a drain of the third transistor is used for outputting a positive terminal output current; and a fourth transistor (124), a source of the fourth transistor is coupled between the first resistor and the second transistor, and a drain of the fourth transistor is used for outputting a negative terminal output current.)

1. A transconductance amplifier for generating an output current according to a positive side input voltage and a negative side input voltage, said transconductance amplifier comprising:

an input stage receiving the positive side input voltage and the negative side input voltage and generating a positive side output current and a negative side output current, the input stage comprising:

a first transistor having a gate coupled to the positive side input voltage;

a second transistor having a gate coupled to the negative side input voltage;

a first resistor connected in series between the first transistor and the second transistor;

a third transistor, a source of the third transistor being coupled between the first resistor and the first transistor, a drain of the third transistor being used to output the positive side output current; and

a fourth transistor, a source of the fourth transistor being coupled between the first resistor and the second transistor, a drain of the fourth transistor being configured to output the negative side output current; and

an output stage for generating the output current according to the positive side output current and the negative side output current.

2. The transconductance amplifier of claim 1, wherein said input stage further comprises:

a first current source coupled between a first reference voltage and a source of the first transistor for generating a first bias current in a direction from the first reference voltage to the source of the first transistor;

a second current source coupled between a second reference voltage and the drain of the first transistor for generating a second bias current, the second bias current flowing from the drain of the first transistor to the second reference voltage;

a third current source coupled between the first reference voltage and a source of the second transistor for generating a third bias current in a direction from the first reference voltage to the source of the second transistor; and

a fourth current source coupled between the second reference voltage and the drain of the second transistor for generating a fourth bias current, the fourth bias current flowing from the drain of the second transistor to the second reference voltage.

3. A transconductance amplifier as claimed in claim 2, wherein said first transistor, said second transistor, said third transistor and said fourth transistor are all P-type transistors.

4. A transconductance amplifier as claimed in claim 3, wherein said input stage further comprises:

a fifth transistor coupled between a gate of the third transistor and the second reference voltage; and

a sixth transistor coupled between a gate of the fourth transistor and the second reference voltage.

5. A transconductance amplifier as claimed in claim 4, wherein said input stage further comprises:

a first capacitor coupled between a gate of the fifth transistor and a drain of the fifth transistor; and

the second capacitor is coupled between the gate of the sixth transistor and the drain of the sixth transistor.

6. A transconductance amplifier as claimed in claim 5, wherein said input stage further comprises:

a seventh current source coupled between a third reference voltage and the drain of the fifth transistor; and

an eighth current source coupled between a third reference voltage and the drain of the sixth transistor;

wherein the third reference voltage is less than the first reference voltage and greater than the second reference voltage.

7. A transconductance amplifier as claimed in claim 6, wherein said fifth and sixth transistors are N-type transistors.

8. A transconductance amplifier as claimed in claim 7, wherein said output stage comprises:

a seventh transistor having a source coupled to the drain of the third transistor;

an eighth transistor having a source coupled to the drain of the fourth transistor;

a ninth current source coupled between the source of the seventh transistor and the second reference voltage for generating a ninth bias current; and

a tenth current source coupled between the source of the eighth transistor and the second reference voltage for generating a tenth bias current.

9. A transconductance amplifier as claimed in claim 8, wherein said seventh transistor and said eighth transistor are N-type transistors.

10. A transconductance amplifier as claimed in claim 9, further comprising:

a bias current control circuit for generating a first control voltage according to the positive terminal input voltage and the negative terminal input voltage, wherein the first control voltage is used for adjusting the magnitude of the fifth bias current generated by the fifth current source and the magnitude of the sixth bias current generated by the sixth current source.

11. The transconductance amplifier of claim 10, wherein said bias current control circuit is further configured to generate a second control voltage according to said positive input voltage and said negative input voltage, said second control voltage being configured to adjust magnitudes of said ninth bias current generated by said ninth current source and said tenth bias current generated by said tenth current source.

12. A transconductance amplifier as claimed in claim 11, wherein said bias current control circuit includes:

a ninth transistor having a gate coupled to the positive side input voltage;

a tenth transistor having a gate coupled to the negative side input voltage;

a second resistor connected in series between the ninth transistor and the tenth transistor.

13. A transconductance amplifier as claimed in claim 12, wherein said bias current control circuit further comprises:

an eleventh current source coupled between a first reference voltage and a source of the ninth transistor for generating an eleventh bias current in a direction from the first reference voltage to the source of the ninth transistor;

a twelfth current source coupled between a second reference voltage and the drain of the ninth transistor for generating a twelfth bias current in a direction flowing from the drain of the ninth transistor to the second reference voltage;

a thirteenth current source coupled between the first reference voltage and a source of the tenth transistor for generating a thirteenth bias current in a direction flowing from the first reference voltage to the source of the tenth transistor; and

a fourteenth current source coupled between the second reference voltage and the drain of the tenth transistor for generating a fourteenth bias current, the fourteenth bias current flowing from the drain of the tenth transistor to the second reference voltage;

wherein the eleventh bias current is greater than the twelfth bias current and the thirteenth bias current is greater than the fourteenth bias current.

14. A transconductance amplifier as claimed in claim 13, wherein said ninth transistor and said tenth transistor are P-type transistors.

15. A chip, comprising:

a transconductance amplifier as claimed in any one of claims 1 to 14.

Technical Field

The present invention relates to a transconductance amplifier and a chip, and more particularly, to a transconductance amplifier and a chip using the same, which can improve accuracy and linearity of the transconductance amplifier.

Background

In a conventional transconductance amplifier, an ac voltage is applied between the gate and the source of the transistor of the input stage, and the generated drain current is affected by the transconductance of the transistor of the input stage, which causes an error in the transconductance amplifier because the current flows through the transistor of the input stage. In addition, the linearity of the transconductance amplifier is deteriorated due to the transconductance nonlinearity of the transistors of the input stage, and the conventional transconductance amplifier has room for further improvement in power consumption. In view of the above, how to improve the above problems has become an important work item in the field.

Disclosure of Invention

It is an object of the present application to disclose a transconductance amplifier and a chip to solve the above problems.

An embodiment of the present application discloses a transconductance amplifier for generating an output current according to a positive input voltage and a negative input voltage, the transconductance amplifier comprising: an input stage receiving the positive side input voltage and the negative side input voltage and generating a positive side output current and a negative side output current, the input stage comprising: a first transistor having a gate coupled to the positive side input voltage; a second transistor having a gate coupled to the negative side input voltage; a first resistor connected in series between the first transistor and the second transistor; a third transistor, a source of the third transistor being coupled between the first resistor and the first transistor, a drain of the third transistor being used to output the positive side output current; and a fourth transistor, a source of the fourth transistor is coupled between the first resistor and the second transistor, and a drain of the fourth transistor is used for outputting the negative terminal output current; and an output stage for generating the output current according to the positive side output current and the negative side output current.

An embodiment of the present application discloses a chip, including the transconductance amplifier described above.

The embodiment of the application is improved aiming at the transconductance amplifier, so that the accuracy can be improved, and the power consumption can be saved.

Drawings

Fig. 1 is a schematic diagram of a transconductance amplifier according to a first embodiment of the present application.

Fig. 2 is a schematic diagram of an embodiment of an input stage of the transconductance amplifier of fig. 1.

Fig. 3 is a schematic diagram of an embodiment of an output stage of the transconductance amplifier of fig. 1.

Fig. 4 is a schematic diagram of a second embodiment of a transconductance amplifier of the present application.

Fig. 5 is a schematic diagram of an embodiment of an input stage of the transconductance amplifier of fig. 4.

Fig. 6 is a schematic diagram of an embodiment of a bias current control circuit of the transconductance amplifier of fig. 4.

Fig. 7 is a schematic diagram of an embodiment of an output stage of the transconductance amplifier of fig. 4.

Wherein the reference numerals are as follows:

100. 200 transconductance amplifier

102. 202 input stage

104. 304 output stage

109 first resistance

110 first transistor

111 first current source

112 third current source

114 third transistor

115 seventh current source

116 fifth transistor

117 first capacitance

120 second transistor

121 second current source

122 fourth current source

124 fourth transistor

125 eighth current source

126 sixth transistor

127 second capacitor

131 seventh transistor

134 ninth current source

141 eighth transistor

144 tenth current source

132. 133, 142, 143, 334, 344, transistor

118、128、215、216、225、226、

217、227、228、334、344

206 bias current control circuit

211 second resistance

212 ninth transistor

213 eleventh current source

214 twelfth Current Source

222 tenth transistor

223 thirteenth current source

224 fourteenth current source

V _IPPositive side output voltage

V _INNegative terminal output voltage

I _OPPositive side output current

I _ONNegative terminal output current

I _OUTOutput current

V ₁A first reference voltage

V ₂Second reference voltage

V ₃Third reference voltage

V _BP、V _BNReference voltage

V _CTPA first control voltage

V _CTNSecond control voltage

Detailed Description

The following disclosure provides many embodiments, or examples, which can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that this description is intended by way of illustration only and is not intended as a definition of the limits of the invention. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.

Transconductance amplifiers are used in many different circuits, with the input of the transconductance amplifier being a voltage and the output being a current. The output current divided by the input voltage defines the transconductance of the transconductance amplifier. Specifically, an ac voltage is applied between the gate and the source of the transistor of the input stage of the conventional transconductance amplifier, and the generated drain current is affected by the transconductance of the transistor of the input stage. Furthermore, the linearity of the conventional transconductance amplifier is affected by the transconductance nonlinearity of the transistors of the input stage. In addition, the conventional transconductance amplifier consumes a bias current of a fixed magnitude regardless of the magnitude of the output current of the conventional transconductance amplifier, and thus the conventional transconductance amplifier has room for further improvement in power consumption.

The transconductance amplifier can improve the error of the transconductance amplifier and improve the linearity by changing the transistor configuration of the input stage. In addition, the power consumption of the transconductance amplifier can be improved by the additional bias current control circuit.

Fig. 1 is a schematic diagram of a transconductance amplifier according to a first embodiment of the present application. The transconductance amplifier 100 is used for being dependent on a positive input voltage V _IPAnd negativeTerminal input voltage V _INGenerating an output current I _OUT. Transconductance amplifier 100 includes an input stage 102 and an output stage 104. The input stage 102 receives a positive input voltage V _IPInput voltage V with negative terminal _INAnd generates a positive side output current I _OPAnd negative terminal output current I _ONThe output stage 104 outputs a current I according to the positive terminal _OPAnd a negative terminal output current I _ONGenerating an output current I _OUT. In the present embodiment, the transconductance amplifier 100 is a rail-to-rail input/output transconductance amplifier.

Fig. 2 is a schematic diagram of an embodiment of an input stage of the transconductance amplifier of fig. 1. The input stage 102 of fig. 2 includes a first transistor 110, a second transistor 120, a first resistor 109, a third transistor 114, a fourth transistor 124, a fifth transistor 116, a sixth transistor 126, a first current source, a second current source 121, a third current source 112, a fourth current source 122, a seventh current source 115, an eighth current source 125, a first capacitor 117, and a second capacitor 127.

In the present embodiment and the following description, the first transistor 110, the second transistor 120, the third transistor 114, and the fourth transistor 124 are P-type transistors; the fifth transistor 116 and the sixth transistor 126 are N-type transistors. However, the present application is not limited thereto, and in some embodiments, the polarities of the transistors in the input stage 102 may also be changed by changing the input stage, for example, the first transistor 110, the second transistor 120, the third transistor 114, and the fourth transistor 124 are changed to P-type transistors; and the fifth transistor 116 and the sixth transistor 126 are changed to N-type transistors.

In the present embodiment, the transconductance amplifier 100 is a rail-to-rail input/output transconductance amplifier, and therefore, in the input stage 102 of fig. 2, the first reference voltage V ₁Greater than a third reference voltage V ₃And a third reference voltage V ₃Greater than a second reference voltage V ₂. Specifically, the first reference voltage V ₁Is a third reference voltage V ₃Twice the second reference voltage V ₂Is the ground voltage. However, the present application is not limited thereto.

As shown in FIG. 2, the gate of the first transistor 110 is coupled to the positive terminalInput voltage V _IPThe gate of the second transistor 120 is coupled to the negative terminal input voltage V _INThe first resistor 109 is connected in series between the first transistor 110 and the second transistor 120, and has a resistance value R ₁Specifically, one end of the first resistor 109 is coupled to the source of the first transistor 110, and the other end of the first resistor 109 is coupled to the source of the second transistor 120. The source of the third transistor 114 is coupled to the source of the first transistor 110, and the drain of the third transistor 114 is used for outputting a positive side output current I _OP(ii) a A source of the fourth transistor 124 is coupled to the source of the second transistor 120, and a drain of the fourth transistor 124 is used for outputting a negative-side output current I _ON。

The first current source 111 is coupled to a first reference voltage V ₁And the source of the first transistor 110 for generating a first bias current from a first reference voltage V ₁To the source of the first transistor 110; the second current source 112 is coupled to the second reference voltage V ₂And the drain of the first transistor 110, for generating a second bias current flowing from the drain of the first transistor 110 to a second reference voltage V ₂(ii) a The third current source 121 is coupled to the first reference voltage V ₁And the source of the second transistor 120 for generating a third bias current from the first reference voltage V ₁To the source of the second transistor 120; the fourth current source 122 is coupled to the second reference voltage V ₂And the drain of the second transistor 120, for generating a fourth bias current flowing from the drain of the second transistor 120 to the second reference voltage V ₂. Wherein the first bias current is greater than the second bias current, and the third bias current is greater than the fourth bias current.

In this embodiment, the positive input voltage V _IPAnd a negative terminal input voltage V _INThe voltage difference between does not affect the source-to-drain currents of the first transistor 110 and the second transistor 120. That is, the voltage difference between the source of the first transistor 110 and the source of the second transistor 120 (i.e., the voltage difference across the first resistor 109) and the positive side input voltage V _IPInput voltage V with negative terminal _INIs the same voltage difference and is not influenced by the voltage difference with the first transistor 110The transconductance and/or the transconductance of the second transistor 120, and the voltage difference between the source of the third transistor 114 and the source of the fourth transistor 124 is the same as the voltage difference between the source of the first transistor 110 and the source of the second transistor 120. Therefore, the positive side outputs a current I _OPAnd a negative terminal output current I _ONA difference of (I) _OP-I _ONIs locked at 2 x (V) _IP-V _IN)/R ₁. Thus, the transconductance of the first transistor 110 and/or the transconductance of the second transistor 120 will not contribute to the output current I of the transconductance amplifier 100 _OUTThe problem of poor linearity of the transconductance of the first transistor 110 and the transconductance of the second transistor 120 itself does not affect the linearity of the transconductance amplifier 100.

Fig. 2 further includes a fifth transistor 116, a sixth transistor 126, a seventh current source 115, an eighth current source 125, a first capacitor 117, and a second capacitor 127. In the embodiment, the fifth transistor 116 and the sixth transistor 126 are N-type transistors, but the application is not limited thereto. A drain of the fifth transistor 116 is coupled to the gate of the third transistor 114, and a source of the fifth transistor 116 is coupled to the second reference voltage V ₂The gate of the fifth transistor 116 is coupled to the drain of the first transistor 110; a drain of the sixth transistor 126 is coupled to the gate of the fourth transistor 124, and a source of the sixth transistor 126 is coupled to the second reference voltage V ₂The gate of the sixth transistor 126 is coupled to the drain of the second transistor 120; the first capacitor 117 is coupled between the gate and the drain of the fifth transistor 116; the second capacitor 127 is coupled between the gate and the drain of the sixth transistor 126. The first capacitor 117 and the second capacitor 127 serve as loop compensation. The seventh current source 115 is coupled to the third reference voltage V ₃And the drain of the fifth transistor 116; the eighth current source 125 is coupled to the third reference voltage V ₃And the drain of the sixth transistor 126.

Fig. 3 is a schematic diagram of an embodiment of an output stage of the transconductance amplifier of fig. 1. The output stage 104 of the transconductance amplifier 100 of fig. 3 includes a seventh transistor 131, an eighth transistor 141, a ninth current source 134, a tenth current source 144, and transistors 132, 133, 142, 143. The seventh transistor 131 and the eighth transistor 141 are N-type transistors, and the transistors 132, 133, 142, and 143 are P-type transistors, but the present application is not limited thereto.

The source of the seventh transistor 131 is coupled to the drain of the third transistor 114 of the input stage 102 of the transconductance amplifier 100 for receiving the positive side output current I _OP(ii) a The source of the eighth transistor 141 is coupled to the drain of the fourth transistor 124 of the input stage 102 of the transconductance amplifier 100 for receiving the negative-side output current I _ON. The gate of the seventh transistor 131 is coupled to the gate of the eighth transistor 141 and coupled to the reference voltage V _BN. A ninth current source 134 coupled to the source of the seventh transistor 131 and the second reference voltage V ₂For generating a ninth bias current; a tenth current source 144 coupled to the source of the eighth transistor 141 and the second reference voltage V ₂To generate a tenth bias current.

A drain of the transistor 132 is coupled to a drain of the seventh transistor 131, a source of the transistor 132 is coupled to a drain of the transistor 133, a source of the transistor 133 is coupled to a third reference voltage V ₃A drain of the transistor 142 is coupled to a drain of the eighth transistor 141, a source of the transistor 142 is coupled to a drain of the transistor 143, and a source of the transistor 143 is coupled to the third reference voltage V ₃The gate of the transistor 132 is coupled to the gate of the transistor 142 and is coupled to the reference voltage V _BP. The gate of the transistor 133 is coupled to the gate of the transistor 143 and is also coupled to the drain of the transistor 132. The transistor 133 and the transistor 143 constitute a current mirror circuit, and output a current I from the positive terminal _OPAnd a negative terminal output current I _ONIs converted into an output current I _OUTAnd is output from between the drain of the eighth transistor 141 and the drain of the transistor 142.

Fig. 4 is a schematic diagram of a second embodiment of a transconductance amplifier of the present application. The transconductance amplifier 200 is used for outputting a positive input voltage V _IPInput voltage V with negative terminal _INGenerating an output current I _OUT. The difference from transconductance amplifier 100 is that transconductance amplifier 200 further includes a bias current control circuit 206, and in response to the addition of bias current control circuit 206, input stage 102 is also providedThe output stage 104 is changed to the input stage 304 as well as the input stage 202. The input stage 202 receives a positive input voltage V _IPInput voltage V with negative terminal _INAnd generates a positive side output current I _OPAnd negative terminal output current I _ONThe output stage 104 outputs a current I according to the positive terminal _OPAnd a negative terminal output current I _ONGenerating an output current I _ON. The bias current control circuit 206 is based on the positive input voltage V _IPInput voltage V with negative terminal _INGenerating a first control voltage V _CTPFor adjusting the magnitude of the bias current in the input stage 202, simply speaking, when the input voltage V is positive _IPInput voltage V with negative terminal _INThe larger the voltage difference therebetween, the larger the output current I of the transconductance amplifier 200 _OUTThe larger the input stage 202, the larger the bias current required, so that the bias current control circuit 206 depends on the positive input voltage V _IPInput voltage V with negative terminal _INThe voltage difference between them determines the bias current of the input stage 202, compared to the case where the bias current control circuit 206 is not used, i.e. regardless of the positive input voltage V _IPInput voltage V with negative terminal _INThe voltage difference between them, the input stage 102 requires a fixed amount of bias current, and the embodiment of fig. 4 can help to save power consumption of the input stage 202.

The bias current control circuit 206 of the transconductance amplifier 200 is further based on the positive input voltage V _IPInput voltage V with negative terminal _INGenerating a second control voltage V _CTNFor adjusting the magnitude of the bias current in the output stage 304, and in response, the output stage 104 is changed to become the input stage 304. Simply put, when the positive terminal inputs the voltage V _IPInput voltage V with negative terminal _INThe larger the voltage difference therebetween, the larger the output current I of the transconductance amplifier 200 _OUTThe larger the output stage 304, the larger the bias current required, so that the bias current control circuit 206 depends on the positive input voltage V _IPInput voltage V with negative terminal _INThe voltage difference between them determines the bias current of the output stage 304, compared to the case without the bias current control circuit 206, i.e. regardless of the positive input voltage V _IPAnd negative terminal inputVoltage V _INThe voltage difference between them, the output stage 104 requires a fixed amount of bias current, and the embodiment of fig. 4 may further help to save power consumption of the output stage 304.

Fig. 5 is a schematic diagram of an embodiment of the input stage 202 of the transconductance amplifier 200 of fig. 4. The difference between the input stage 202 and the input stage 102 in fig. 2 is that a transistor 118 and a transistor 128 are added, and in this embodiment, the transistor 118 and the transistor 128 are P-type transistors, but the application is not limited thereto. The source of the transistor 118 is coupled to a first reference voltage V ₁The drain of the transistor 118 is coupled to the source of the third transistor 114, and the source of the transistor 128 is coupled to the first reference voltage V ₁The drain of the transistor 128 is coupled to the source of the fourth transistor 124, and the gates of the transistor 118 and the transistor 128 are subjected to the first control voltage V _CTPTo adjust the magnitudes of the fifth bias current and the sixth bias current, thereby helping to save power consumption of the input stage 202.

Fig. 6 is a schematic diagram of an embodiment of the bias current control circuit 206 of the transconductance amplifier 200 of fig. 4. The bias current control circuit 206 includes a ninth transistor 212, a tenth transistor 222, a second resistor 211, an eleventh current source 213, a twelfth current source 214, a thirteenth current source 223, a fourteenth current source 224, and transistors 215, 216, 225, 226, 217, 227, 228. In this embodiment, the ninth transistor 212, the tenth transistor 222, the transistors 217 and 227 are P-type transistors, and the transistors 215, 216, 225, 226 and 228 are N-type transistors, but the present application is not limited thereto.

As shown in FIG. 6, the gate of the ninth transistor 212 is coupled to the positive side input voltage V _IPThe tenth transistor 222 has a gate coupled to the negative terminal input voltage V _INThe second resistor 211 is connected in series between the ninth transistor 212 and the tenth transistor 222, and has a resistance value R ₂Specifically, one end of the second resistor 211 is coupled to the source of the ninth transistor 212, and the other end of the second resistor 211 is coupled to the source of the tenth transistor 222.

The eleventh current source 213 is coupled to the first reference voltage V ₁And the source of the ninth transistor 212 to generate an eleventhThe bias current is derived from a first reference voltage V ₁To the source of the ninth transistor 212; the twelfth current source 214 is coupled to the second reference voltage V ₂And the drain of the ninth transistor 212, for generating a twelfth bias current flowing from the drain of the ninth transistor 212 to the second reference voltage V ₂(ii) a The thirteenth current source 223 is coupled to the first reference voltage V ₁And a source of a tenth transistor 222 for generating a thirteenth bias current from the first reference voltage V ₁To the source of the tenth transistor 222; the fourteenth current source 224 is coupled to the second reference voltage V ₂And the drain of the tenth transistor 222 for generating a fourteenth bias current flowing from the drain of the tenth transistor 222 to the second reference voltage V ₂. Wherein the eleventh bias current is greater than the twelfth bias current, and the thirteenth bias current is greater than the fourteenth bias current.

Unlike the configuration of the input stage 102 or 202, the source-to-drain currents of the ninth transistor 212 and the tenth transistor 222 in the bias current control circuit 206 are not locked-up, so the positive side input voltage V _IPAnd a negative terminal input voltage V _INThe voltage difference between may reflect the twelfth bias current at twelfth current source 214 and the fourteenth bias current at fourteenth current source 224. Since the bias current control circuit 206 is only used to generate the control first control voltage V _CTPRather than as an input stage, the error caused by the transconductance of the ninth transistor 212 and the tenth transistor 222 is not detrimental to the overall accuracy. The transistors 215 and 216 form a first current mirror circuit, the transistors 225 and 226 form a second current mirror circuit, and the transistor 217 and the transistor 227 form a third current mirror circuit. The difference between the drain currents of the ninth transistor 212 and the tenth transistor 222 reflects the drain current of the transistor 217 through the first current mirror circuit and the second current mirror circuit. And reflects the drain current to the transistor 227 by said forming the third current mirror circuit. The gate voltage of the transistor 227 can be used as the first control voltage V _CTP。

For the bias current control circuit 206 of FIG. 4, the gate voltage of the transistor 228 isCan be used as the second control voltage V _CTN. Fig. 7 is a schematic diagram of an embodiment of the output stage 304 of the transconductance amplifier 200 of fig. 4. The difference between the output stage 304 and the output stage 104 of fig. 3 is that the ninth current source 134 and the tenth current source 144 of the output stage 104 of fig. 3 are respectively implemented by a transistor 334 and a transistor 344 in the output stage 304 of fig. 7, and in this embodiment, the transistor 334 and the transistor 344 are N-type transistors, but the present application is not limited thereto. A source of the transistor 334 is coupled to the second reference voltage V ₂A drain of the transistor 334 is coupled to a source of the seventh transistor 131, and a source of the transistor 344 is coupled to the second reference voltage V ₂The drain of the transistor 344 is coupled to the source of the eighth transistor 141, and the gates of the transistor 334 and the transistor 344 are subjected to the second control voltage V _CTNTo adjust the magnitudes of the ninth bias current and the tenth bias current, thereby further saving the power consumption of the output stage 304.

The present application also provides a chip that includes the transconductance amplifier 100/200 described above.

The embodiment of the application is improved aiming at the conventional transconductance amplifier, and the error of the transconductance amplifier is improved and the linearity is improved by changing the transistor configuration of the input stage. In addition, the power consumption of the transconductance amplifier can be improved by the additional bias current control circuit.

The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.