阅读说明：本技术 存算一体装置及其校准方法 (Storage and calculation integrated device and calibration method thereof ) 是由 姚鹏 吴华强 高滨 唐建石 钱鹤 于 2021-07-21 设计创作，主要内容包括：一种存算一体装置及其校准方法。存算一体装置包括第一处理单元,第一处理单元包括：第一计算忆阻器阵列,被配置为接收第一计算输入数据,并对第一计算输入数据进行计算以得到第一输出数据；以及第一校准忆阻器阵列,被配置为接收第一校准输入数据,并根据第一校准输入数据对第一输出数据进行校准,以得到第一校准输出数据；第一处理单元被配置为输出第一校准输出数据。校准方法包括：通过片外训练确定第一计算忆阻器阵列对应的第一计算权重矩阵,将第一计算权重矩阵写入第一计算忆阻器阵列；基于写入了第一计算权重矩阵的第一计算忆阻器阵列和第一计算权重矩阵,对第一校准忆阻器阵列进行片上训练,以调整第一校准忆阻器阵列的权重值。(A storage and computation integrated device and a calibration method thereof. The integrated computing device comprises a first processing unit, and the first processing unit comprises: a first computational memristor array configured to receive first computational input data and to compute the first computational input data to obtain first output data; and a first calibration memristor array configured to receive first calibration input data and calibrate first output data according to the first calibration input data to obtain first calibration output data; the first processing unit is configured to output first calibration output data. The calibration method comprises the following steps: determining a first calculation weight matrix corresponding to the first calculation memristor array through off-chip training, and writing the first calculation weight matrix into the first calculation memristor array; based on the first computational memristor array and the first computational weight matrix written with the first computational weight matrix, on-chip training is performed on the first calibration memristor array to adjust weight values of the first calibration memristor array.)

1. A calibration method for a storage-integrated device, wherein,

the integrated computing device comprises a first processing unit comprising a first compute memristor array and a first calibration memristor array, the first compute memristor array configured to receive first compute input data and compute the first compute input data to obtain first output data; the first calibration memristor array configured to receive first calibration input data and calibrate the first output data according to the first calibration input data to obtain first calibration output data; the first processing unit is configured to output the first calibration output data,

the calibration method comprises the following steps:

determining a first calculation weight matrix corresponding to the first calculation memristor array through off-chip training, and writing the first calculation weight matrix into the first calculation memristor array;

on-chip training the first calibration memristor array to adjust weight values of the first calibration memristor array based on the first computational memristor array to which the first computational weight matrix was written and the first computational weight matrix.

2. The calibration method according to claim 1,

the first computing memristor array comprises M rows by N columns of memristor cells, the first calibration memristor array comprises K rows by N columns of memristor cells, an ith column of the first calibration memristor array is connected in series with the ith column of the first computing memristor array, the memristor cells of the ith column of the first calibration memristor array are configured to calibrate first output data of the ith column of the first computing memristor array according to the first calibration input data to obtain first calibration output data of the ith column, wherein M, N, K, i are positive integers, and 1 ≦ i ≦ N,

on-chip training the first calibration memristor array based on the first computational memristor array written with the first computational weight array and the first computational weight matrix to adjust weight values of the first calibration memristor array, including:

determining first training target output data according to first training calculation input data and the first calculation weight matrix;

inputting the first training computational input data to the first computational memristor array and inputting first training calibration input data to the first calibration memristor array to obtain first training calibration output data;

adjusting weight values of memristor cells in the first calibration memristor array corresponding to a column in the first computational memristor array requiring calibration according to a deviation of the first training calibration output data and the first training target output data.

3. The calibration method according to claim 2,

the first calibration memristor array includes a fixed-offset calibration subarray, the first training calibration input data includes fixed-training calibration input data, the fixed-offset calibration subarray includes 1 row by N columns of memristor cells,

inputting the first training calibration input data to the first calibration memristor array, comprising: inputting the fixed training calibration input data to the fixed offset calibration subarrays.

4. The calibration method according to claim 2,

the first calibration memristor array includes a dynamic offset calibration subarray, the first training calibration input data including dynamic training calibration input data, the dynamic offset calibration subarray including at least 1 row by N columns of memristor cells,

inputting the first training calibration input data to the first calibration memristor array, comprising: determining the dynamic training calibration input data according to the first training calculation input data; and inputting the dynamic training calibration input data to the dynamic bias calibration subarrays.

5. The calibration method according to claim 2,

the first calibrated memristor array includes a fixed-bias calibration subarray and a dynamic-bias calibration subarray, the first training calibration input data including fixed-training calibration input data and dynamic-training calibration input data, the fixed-bias calibration subarray including 1 row by N columns of memristor cells, the dynamic-bias calibration subarray including at least 1 row by N columns of memristor cells,

inputting the first training calibration input data to the first calibration memristor array, comprising:

inputting the fixed training calibration input data to the fixed offset calibration subarrays;

determining the dynamic training calibration input data according to the first training calculation input data; and the number of the first and second groups,

inputting the dynamic training calibration input data to the dynamic bias calibration subarrays.

6. The calibration method of claim 3 or 5, wherein inputting the fixed training calibration input data to the fixed offset calibration subarray comprises: inputting 5% -20% of a maximum value of the first training computational input data to the fixed bias calibration subarray as the fixed training calibration input data.

7. The calibration method according to claim 4 or 5, wherein,

before on-chip training the first calibration memristor array to adjust weight values of the first calibration memristor array based on the first computational memristor array written with the first computational weight matrix and the first computational weight matrix, the calibration method further includes:

determining at least one memristor cell of an ith column of the first computational memristor array in a critical weight position, and setting an input of the at least one memristor cell of the ith column of the dynamic misalignment calibration subarray to be the same as an input of the at least one memristor cell of the ith column of the first computational memristor array in the critical weight position,

wherein determining the dynamic training calibration input data based on the first training computational input data comprises:

taking the first training computational input data of the at least one memristor cell at a critical weight location of the ith column of the first computational memristor array as dynamic training calibration input data of the at least one memristor cell of the ith column of the dynamic misalignment calibration subarray.

8. The calibration method according to claim 4 or 5, wherein,

before on-chip training the first calibration memristor array to adjust weight values of the first calibration memristor array based on the first computational memristor array written with the first computational weight matrix and the first computational weight matrix, the calibration method further includes:

determining at least one row of memristor cells of the first computational memristor array at a critical weight location and setting an input of the at least one row of memristor cells of the dynamic misalignment calibration subarray to be the same as an input of the at least one row of memristor cells of the first computational memristor array at the critical weight location,

wherein determining the dynamic training calibration input data based on the first training computational input data comprises:

taking the first training computational input data of the at least one row of memristor cells of the first computational memristor array at the key weight location as dynamic training calibration input data of the at least one row of memristor cells of the dynamic misalignment calibration subarray.

9. The calibration method according to any one of claims 2 to 5,

on-chip training the first calibration memristor array based on the first computational memristor array written with the first computational weight matrix and the first computational weight matrix to adjust weight values of the first calibration memristor array, further comprising:

before inputting the first training computational input data to the first computational memristor array and inputting the first training calibration input data to the first calibration memristor array to obtain the first training calibration output data,

inputting the first training computational input data to the first computational memristor array to obtain first training output data;

according to the deviation of the first training output data and the first training target output data, columns in the first calculation memristor array needing to be calibrated are determined, and memristor units in the first calibration memristor array, corresponding to the columns in the first calculation memristor array needing to be calibrated, are connected in series with the columns in the first calculation memristor array needing to be calibrated.

10. A computing-integrated apparatus includes a first processing unit, wherein the first processing unit includes a first computing memristor array and a first calibration memristor array,

the first computational memristor array is configured to receive first computational input data and to compute the first computational input data to obtain first output data;

the first calibration memristor array configured to receive first calibration input data and calibrate the first output data according to the first calibration input data to obtain first calibration output data;

the first processing unit is configured to output the first calibration output data.

Technical Field

The embodiment of the disclosure relates to a storage and computation integrated device and a calibration method thereof.

Background

The memristor-based storage and calculation integrated device can directly perform operations such as in-situ multiplication and accumulation at a storage position, realizes component-level fusion of calculation and storage, breaks through the limitations of calculation power and energy efficiency of a traditional hardware platform, and is one of the most potential next-generation hardware chip technologies. Enterprises and scientific research units at home and abroad invest a large amount of manpower and material resources, and after the development of nearly ten years, the memristor-based storage and calculation integrated technology gradually enters a prototype demonstration stage of an actual chip and system from a theoretical simulation stage.

Disclosure of Invention

At least one embodiment of the present disclosure provides a calibration method of a passbook apparatus, the passbook apparatus including a first processing unit including a first computation memristor array and a first calibration memristor array, the first computation memristor array configured to receive first computation input data and to compute the first computation input data to obtain first output data; the first calibration memristor array configured to receive first calibration input data and calibrate the first output data according to the first calibration input data to obtain first calibration output data; the first processing unit is configured to output the first calibration output data, the calibration method comprising: determining a first calculation weight matrix corresponding to the first calculation memristor array through off-chip training, and writing the first calculation weight matrix into the first calculation memristor array; on-chip training the first calibration memristor array to adjust weight values of the first calibration memristor array based on the first computational memristor array to which the first computational weight matrix was written and the first computational weight matrix.

For example, in a calibration method provided in at least one embodiment of the present disclosure, the first computation memristor array includes M rows by N columns of memristor cells, the first calibration memristor array includes K rows by N columns of memristor cells, an ith column of the first calibration memristor array is connected in series with an ith column of the first computation memristor array, the memristor cells of the ith column of the first calibration memristor array are configured to calibrate first output data of the ith column of the first computation memristor array according to the first calibration input data to obtain first calibration output data of the ith column, M, N, K, i are positive integers, and 1 ≦ i ≦ N, the first calibration memristor array is trained on-chip based on the first computation memristor array written with the first computation weight array and the first computation weight matrix, to adjust weight values of the first calibration memristor array, including: determining first training target output data according to first training calculation input data and the first calculation weight matrix; inputting the first training computational input data to the first computational memristor array and inputting first training calibration input data to the first calibration memristor array to obtain first training calibration output data; adjusting weight values of memristor cells in the first calibration memristor array corresponding to a column in the first computational memristor array requiring calibration according to a deviation of the first training calibration output data and the first training target output data.

For example, in a calibration method provided in at least one embodiment of the present disclosure, the first calibration memristor array includes a fixed-offset calibration subarray, the first training calibration input data includes fixed-offset calibration input data, the fixed-offset calibration subarray includes 1 row by N columns of memristor cells, the inputting the first training calibration input data to the first calibration memristor array includes: inputting the fixed training calibration input data to the fixed offset calibration subarrays.

For example, in a calibration method provided in at least one embodiment of the present disclosure, the first calibration memristor array includes a dynamic bias calibration subarray, the first training calibration input data includes dynamic training calibration input data, the dynamic bias calibration subarray includes at least 1 row by N columns of memristor cells, the inputting the first training calibration input data to the first calibration memristor array includes: determining the dynamic training calibration input data according to the first training calculation input data; and inputting the dynamic training calibration input data to the dynamic bias calibration subarrays.

For example, in a calibration method provided in at least one embodiment of the present disclosure, the first calibration memristor array includes a fixed-bias calibration subarray and a dynamic-bias calibration subarray, the first training calibration input data includes fixed-training calibration input data and dynamic-training calibration input data, the fixed-bias calibration subarray includes 1 row × N columns of memristor cells, the dynamic-bias calibration subarray includes at least 1 row × N columns of memristor cells, the inputting the first training calibration input data to the first calibration memristor array includes: inputting the fixed training calibration input data to the fixed offset calibration subarrays; determining the dynamic training calibration input data according to the first training calculation input data; and inputting the dynamic training calibration input data to the dynamic bias calibration subarrays.

For example, in a calibration method provided in at least one embodiment of the present disclosure, inputting the fixed training calibration input data to the fixed offset calibration subarray includes: inputting 5% -20% of a maximum value of the first training computational input data to the fixed bias calibration subarray as the fixed training calibration input data.

For example, in a calibration method provided by at least one embodiment of the present disclosure, before on-chip training the first calibration memristor array based on the first computational memristor array and the first computational weight matrix written with the first computational weight matrix to adjust weight values of the first calibration memristor array, the calibration method further includes: determining at least one memristor cell in a critical weight location of an ith column of the first computational memristor array and setting an input of the at least one memristor cell in the ith column of the dynamic bias calibration subarray to be the same as an input of the at least one memristor cell in a critical weight location of the ith column of the first computational memristor array, the determining the dynamic training calibration input data from the first training computation input data comprising: taking the first training computational input data of the at least one memristor cell at a critical weight location of the ith column of the first computational memristor array as dynamic training calibration input data of the at least one memristor cell of the ith column of the dynamic misalignment calibration subarray.

For example, in a calibration method provided by at least one embodiment of the present disclosure, before on-chip training the first calibration memristor array based on the first computational memristor array and the first computational weight matrix written with the first computational weight matrix to adjust weight values of the first calibration memristor array, the calibration method further includes: determining at least one row of memristor cells of the first computational memristor array at a key weight location and setting inputs of the at least one row of memristor cells of the dynamic bias calibration subarray to be the same as inputs of the at least one row of memristor cells of the first computational memristor array at a key weight location, the determining the dynamic training calibration input data from the first training computational input data comprising: taking the first training computational input data of the at least one row of memristor cells of the first computational memristor array at the key weight location as dynamic training calibration input data of the at least one row of memristor cells of the dynamic misalignment calibration subarray.

For example, in a calibration method provided by at least one embodiment of the present disclosure, on-chip training is performed on the first calibration memristor array based on the first computation memristor array written with the first computation weight matrix and the first computation weight matrix to adjust weight values of the first calibration memristor array, further including: inputting the first training memristor array with the first training computational input data to obtain first training output data before inputting the first training computational input data to the first computational memristor array and inputting the first training calibration input data to the first calibration memristor array to obtain the first training calibration output data; according to the deviation of the first training output data and the first training target output data, columns in the first calculation memristor array needing to be calibrated are determined, and memristor units in the first calibration memristor array, corresponding to the columns in the first calculation memristor array needing to be calibrated, are connected in series with the columns in the first calculation memristor array needing to be calibrated.

For example, in a calibration method provided by at least one embodiment of the present disclosure, the integrated memory device further includes a second processing unit, the second processing unit includes a second computation memristor array and a second calibration memristor array, the second computation memristor array is configured to receive second computation input data determined according to the first calibration output data, and to perform computation on the second computation input data to obtain second output data; the second calibration memristor array configured to receive second calibration input data and calibrate the second output data according to the second calibration input data to obtain second calibration output data; the second processing unit is configured to output the second calibration output data, the calibration method further comprising: determining a second calculation weight matrix corresponding to the second calculation memristor array through off-chip training, and writing the second calculation weight matrix into the second calculation memristor array; on-chip training the second calibration memristor array to adjust weight values of the second calibration memristor array based on the second computational weight matrix and the computational outputs of the second computational memristor array written with the second computational weight matrix.

For example, in the calibration method provided by at least one embodiment of the present disclosure, the second processing unit is coupled to the first processing unit, and in the process of performing on-chip training on the second calibration memristor array based on the second calculated memristor array written with the second calculated weight matrix and the second calculated weight matrix to adjust the weight values of the second calibration memristor array, according to first training calculation input data and the first calculated weight matrix, first training target output data is determined and is taken as second training input data of the second calculated memristor array, or, in the case where the first calibration memristor array is trained, the first training calculation input data is input to the first calculation memristor array, first training calibration input data is input to the first calibration memristor array, to obtain first training calibration output data, and to use the first training calibration output data as second training input data for the second computational memristor array.

For example, in a calibration method provided by at least one embodiment of the present disclosure, each memristor cell in the first calibration memristor array is configured to be capable of implementing both positive and negative weights.

At least one embodiment of the present disclosure also provides a memory-computation integrated device, including a first processing unit including a first computation memristor array configured to receive first computation input data and compute the first computation input data to obtain first output data, and a first calibration memristor array; the first calibration memristor array configured to receive first calibration input data and calibrate the first output data according to the first calibration input data to obtain first calibration output data; the first processing unit is configured to output the first calibration output data.

For example, in the integrated memory device provided by at least one embodiment of the present disclosure, the first computation memristor array includes M rows by N columns of memristor cells, the first calibration memristor array includes K rows by N columns of memristor cells, an ith column of the first calibration memristor array is connected in series with an ith column of the first computation memristor array, the memristor cells of the ith column of the first calibration memristor array are configured to calibrate the first output data of the ith column of the first computation memristor array according to the first calibration input data to obtain the first calibration output data of the ith column, M, N, K, i are positive integers, and 1 ≦ i ≦ N.

For example, in the integrated memory device provided in at least one embodiment of the present disclosure, the first calibration memristor array includes a fixed-offset calibration subarray, the first calibration input data includes fixed calibration input data, the fixed-offset calibration subarray includes 1 row × N columns of memristor cells, an ith column of the fixed-offset calibration subarray is connected in series with an ith column of the first computation memristor array, and the memristor cells of the ith column of the fixed-offset calibration subarray are configured to calibrate the first output data of the ith column of the first computation memristor array according to the fixed calibration input data to obtain first calibration output data of the ith column.

For example, in the integrated memory device provided by at least one embodiment of the present disclosure, the first calibration memristor array includes a dynamic bias calibration subarray, the first calibration input data includes dynamic calibration input data, the dynamic bias calibration subarray includes at least 1 row by N columns of memristor cells, an ith column of the dynamic bias calibration subarray is connected in series with an ith column of the first computational memristor array, dynamic calibration input data corresponding to at least one memristor cell of the ith column of the dynamic bias calibration subarray is determined according to first computational input data corresponding to M memristor cells of the ith column of the first computational memristor array, the at least one memristor cell of the ith column of the dynamic bias calibration subarray is configured according to dynamic calibration input data corresponding to the at least one memristor cell of the ith column of the dynamic bias subarray, calibrating the first output data of the ith column of the first computing memristor array to obtain first calibrated output data of the ith column.

For example, in the integrated memory device provided by at least one embodiment of the present disclosure, the first calibration memristor array includes a fixed bias calibration subarray and a dynamic bias calibration subarray, the first calibration input data includes fixed calibration input data and dynamic calibration input data, the fixed bias calibration subarray includes 1 row by N columns of memristor cells, the dynamic bias calibration subarray includes at least 1 row by N columns of memristor cells, an ith column of the fixed bias calibration subarray and an ith column of the dynamic bias calibration subarray are connected in series with an ith column of the first computation memristor array, dynamic calibration input data corresponding to at least one memristor cell of the ith column of the dynamic bias calibration subarray is determined according to first computation input data corresponding to M memristor cells of the ith column of the first computation memristor array, the memristor cell of the ith column of the fixed offset calibration subarray and the at least one memristor cell of the ith column of the dynamic offset calibration subarray are configured to calibrate the first output data of the ith column of the first computation memristor array according to the fixed calibration input data and the dynamic calibration input data corresponding to the at least one memristor cell of the ith column of the dynamic offset calibration subarray, respectively, so as to obtain first calibration output data of the ith column.

For example, in at least one embodiment of the present disclosure, the fixed calibration input data is 5% to 20% of the maximum value of the first calculation input data.

For example, in the integrated memory device provided in at least one embodiment of the present disclosure, the dynamic calibration input data corresponding to at least one memristor cell in the ith column of the dynamic offset calibration subarray is the same as the first calculation input data corresponding to at least one memristor cell in the critical weight position in the ith column of the first calculation memristor array.

For example, in the integrated memory device provided in at least one embodiment of the present disclosure, the dynamic calibration input data corresponding to at least one row of memristor cells of the dynamic offset calibration subarray is the same as the first calculation input data corresponding to at least one row of memristor cells in the key weight position of the first calculation memristor array.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 illustrates a schematic diagram of a memristor crossbar array structure;

FIG. 2 illustrates a schematic diagram of a processing unit of a computing-integrated apparatus;

FIG. 3 illustrates a schematic diagram of a memristor-based storage integrated system;

FIG. 4A illustrates a schematic diagram of a low-level, fine-grained component-level calibration method;

FIG. 4B illustrates a schematic diagram of a high-level, coarse-grained system-level calibration method;

FIG. 4C is a diagram illustrating a mid-level, mid-granular calibration method for mid-level components according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a processing unit of a computing integrated device according to an embodiment of the disclosure;

FIG. 6 is a flowchart illustrating a calibration method for a computing integrated device according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of an example of a first processing unit provided in an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of one example of dynamically determining dynamic training calibration input data provided by an embodiment of the present disclosure;

fig. 9A is a flowchart of an example of a calibration method provided by at least one embodiment of the present disclosure;

fig. 9B is a flowchart of another example of a calibration method provided by at least one embodiment of the present disclosure;

fig. 10A is a schematic diagram of an independent parallel calibration manner provided by at least one embodiment of the present disclosure;

fig. 10B is a schematic diagram of a step-by-step calibration method according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The present disclosure is illustrated by the following specific examples. Detailed descriptions of known functions and known components may be omitted in order to keep the following description of the embodiments of the present invention clear and concise. When any element of an embodiment of the present invention appears in more than one drawing, that element is identified by the same reference numeral in each drawing.

The memristor cross array structure is an analog domain calculation core of the memristor memory calculation integrated device. For example, fig. 1 illustrates a schematic diagram of a memristor crossbar array structure 100. As shown in FIG. 1, the memristor crossbar array structure 100 may include a plurality of memristors arranged in a criss-cross manner in an array by arranging input data as an input vector X (e.g., including X as shown in FIG. 1)₁、x₂、……、x_nAnd the input vector may be a voltage of encoded amplitude, width, or number of pulses), encode the weight matrix as memristor conductance values G (e.g., including G as shown in fig. 1)₁₁、g₂₁、……、g_1nAnd g not shown in FIG. 1_m1、g_m1、……、g_mn) Obtaining output current by using high-parallelism and low-power consumption array reading operationI (e.g., including I shown in FIG. 1)₁、I₂、……、I_m) The method can realize the general multiplication and accumulation calculation in the deep learning, and further accelerate the matrix vector multiplication. For example, according to kirchhoff's law, the output current of a memristor crossbar array structure may be derived according to the following formula: i ═ gxv. The multiplication and accumulation calculation process is realized by utilizing a physical law in an analog domain, is different from a digital circuit realization mode of Boolean logic, does not need frequent access and movement of weight data, solves the von Neumann bottleneck of a classical calculation system, and can realize an intelligent calculation task with high calculation power and high energy efficiency.

Memristor crossbar arrays may be used to build basic Processing units (PEs) of a computing-integrated device. For example, FIG. 2 illustrates a schematic diagram of a processing unit 200 of a computing integrated device. As shown in fig. 2, the processing unit 200 may include an analog domain part and a digital domain part, wherein the analog domain part implements analog computation based on analog signals, and the input, control and output of the analog domain are digital signals; the digital domain part controls, cooperates with the function of the analog domain part and interacts with the outside. For example, as shown in fig. 2, the analog domain portion includes an input module 210, a memristor array 220, an output module 230, and a power supply module 240. The input module 210 is a related analog circuit for implementing the function of input vector; the memristor array 220 is a memristor crossbar array (e.g., the memristor crossbar array structure 100 shown in fig. 1), which may be written to a weight matrix and subjected to multiply-accumulate calculations; the output module 230 is a related analog circuit for implementing quantization of an output vector (e.g., the output current shown in fig. 1); the power supply module 240 is a basic analog power supply circuit. For example, the digital domain portion may include a controller, an input buffer, an output buffer, a digital post-processing module, an interface module, and the like (not shown in fig. 1). It should be noted that the memory processing unit 200 shown in fig. 1 is merely an example, and is not a limitation of the present disclosure, and the processing unit may add, decrease, and change modules according to actual situations.

FIG. 3 illustrates a schematic diagram of a memristor-based storage integrated system 300. For example, the banker system 300 may be a banker chip. As shown in fig. 3, the integrated storage system 300 includes a plurality of processing unit modules 310 and a plurality of functional units 320. As shown in fig. 3, each processing unit module 310 includes a plurality of processing units 311 and a plurality of functional modules 312, for example, the processing unit 311 may be the processing unit 200 shown in fig. 2, and the plurality of functional modules 312 are implemented by digital circuits and may include one or more of the following: the device comprises an interconnection module, an interface module, a control module and the like. For example, the plurality of functional units 320 are implemented by digital circuitry and may include one or more of the following: the device comprises an interconnection unit, a main control unit, an on-chip storage unit, a routing unit, an interface unit, a clock unit, a power supply unit and the like. It should be noted that the integrated storage system 300 shown in fig. 3 is only an example and is not a limitation of the present disclosure, and the integrated storage system may add, decrease, and change units or modules according to actual situations. In a memristor-based storage and calculation integrated system, signal processing and control realized by all digital domains are very stable, but analog calculation realized by an analog domain may be influenced by natural randomness, non-ideal characteristics and array parasitic parameters of a memristor or by environmental deviation and fluctuation of process, power supply, temperature and the like, so that ideal functions and outputs can be deviated when a device level (the memristor), a circuit level (an analog circuit module), an array level and a system level work, and precision loss and errors of calculation results can be caused by errors, noises and the like, so that a hardware system cannot work correctly. For example, in the case where each processing unit 311 shown in fig. 3 is the processing unit 200 shown in fig. 2, errors and perturbations may exist in the input module, the memristor array, the output module, and the power supply module in each processing unit 311, whereas in the case where the memristor-based integrated memory system shown in fig. 3 includes a plurality of processing units 311, errors and perturbations may be accumulated continuously, thereby seriously affecting the normal operation of the system, and this requires calibration.

For example, fig. 4A-4C illustrate a schematic of a calibration method. Conventional calibration methods can be divided into two categories. The first type of calibration method is low-level, fine-grained component-level calibration, which ensures reliable and accurate operation of each component by calibrating all potential sources of error and fluctuation, thereby ensuring that a system comprising multiple components can operate reliably and accurately. For example, a plurality of memristors are adopted to jointly represent a weight unit, and the influence of randomness is counteracted by using an averaging effect; a brand-new unit array structure is designed, and parasitic parameters of the array are relieved; the design size of the circuit is increased in equal proportion, and the process deviation is relieved; and a calibration circuit unit is introduced to compensate and calibrate the precision of the analog circuit. For example, FIG. 4A illustrates a schematic diagram of a low-level, fine-grained, component-level calibration method, where black circles represent calibration positions, and in FIG. 4A, each module within the analog domain of a processing unit is calibrated to ensure that the processing unit, and thus a system including multiple processing units, is operating reliably and accurately. The second type of calibration method is high-level and coarse-grained system-level calibration, and specific error and fluctuation sources are not concerned in the second type of calibration method, but correct work and output of the system function level are emphasized from the overall performance of the system. For example, the algorithm and the system are combined to perform joint optimization, on-chip training is performed on the key layer weight or all weights, an ensemble learning method is adopted, more hardware resources are adopted to realize the same algorithm, and the like. For example, fig. 4B illustrates a schematic diagram of a high-level, coarse-grained system-level calibration method, where black circles represent calibration locations, and in fig. 4B, calibration is achieved by algorithm optimization and flow refinement for a memristor-based memory-integrated system as a whole. However, the first type of calibration method has high overhead, high cost, and high complexity of design and implementation; the second calibration method generally has higher requirements on device characteristics, calibration reliability is difficult to guarantee, only functions in a limited network structure can be proved, and the method cannot be popularized to a wider and more complex network model.

In order to realize high-reliability and low-cost universal memory-computation integrated analog computation error calibration, the disclosure provides a middle-level and middle-granularity calibration method for middle-level components. In the middle-level and middle-granularity calibration method for the middle-level component, the redundant calibration unit is introduced to calibrate the calculation result of the analog domain of the middle-level component, so that the system can work reliably and accurately, and the introduced redundant calibration unit is only adjusted without changing the weight matrix realized by the existing memristor array, so that the hardware overhead can be flexibly configured according to the requirement of calibration precision, and the design as required is realized. For example, fig. 4C is a schematic diagram of a middle-level and middle-granularity calibration method for a middle-level component according to an embodiment of the present disclosure, where a black circle represents a calibration position, and in fig. 4C, a calculation result of a simulation domain of each processing unit is calibrated, and since errors of analog elements of various bottom layers are finally reflected on the simulation calculation result, calibrating the calculation result of the simulation domain is equivalent to calibrating the analog elements of each bottom layer at the same time, and it can be ensured that each calculation result is accurate at a processing unit level, thereby ensuring that a system normally operates.

The mid-level, mid-granularity calibration method for mid-level components proposed by the present disclosure, and embodiments and corresponding examples thereof, are described in detail below with reference to the accompanying drawings.

Fig. 5 is a schematic diagram of a processing unit of a storage and computation integrated device according to an embodiment of the present disclosure. Fig. 6 is a flowchart illustrating a calibration method of a storage and computation integrated device according to an embodiment of the disclosure. The calibration method shown in fig. 6 will be described in detail below, taking the integrated computing device shown in fig. 5 as an example.

For example, as shown in fig. 5, the integrated computing device includes a first processing unit 500, the first processing unit 500 including a first computation memristor array 510 and a first calibration memristor array 520, the first computation memristor array 510 configured to receive first computation input data and to compute the first computation input data to obtain first output data; the first calibration memristor array 520 is configured to receive first calibration input data and calibrate first output data according to the first calibration input data to obtain first calibration output data; the first processing unit 500 is configured to output first calibration output data.

For example, the first computational memristor array 510 may be the memristor array 220 shown in fig. 2. The first computation input data may be an encoded voltage, and the first computation memristor array 510 performs a multiply-accumulate computation to obtain first output data, which is a current value.

For example, the first calibration memristor array 520 may be a memristor crossbar array, the first calibration input data may be an encoded voltage, and the first calibration memristor array 520 may calibrate a fixed bias offset and a dynamic offset of the first output data.

It should be noted that, for the sake of clarity, fig. 5 only schematically shows the first processing unit 500 of the integrated device, and only shows a part of the components of the first processing unit 500, in fact, the integrated device may include a plurality of basic processing units similar to the first processing unit 500 and other possible components (for example, the functional unit 320 shown in fig. 3), and the first processing unit 500 may also include other possible components (for example, various analog circuits shown in fig. 2).

In this case, for example, as shown in fig. 6, the calibration method 600 includes step S610 and step S620.

Step S610: a first calculation weight matrix corresponding to the first calculation memristor array 510 is determined through off-chip training, and the first calculation weight matrix is written into the first calculation memristor array 510.

Step S620: based on the first computational memristor array 510 and the first computational weight matrix into which the first computational weight matrix is written, on-chip training is performed on the first calibration memristor array 520 to adjust the weight values of the first calibration memristor array 520.

For step S610, a first computational weight matrix may be encoded into conductance values of a first computational memristor array.

For step S620, the calculation output of the first calculation memristor array 510 written with the first calculation weight matrix may be regarded as actual first output data, an ideal target output data may be determined by using the first calculation weight matrix, a deviation exists between the actual first output data and the ideal target output data, the first calibration memristor array 520 is trained on chip, and the deviation may be reduced by adaptively adjusting the weight value of the first calibration memristor array 520 until the deviation reaches a proper interval, so as to achieve the purpose of calibration.

For example, the calibration method 600 described above may be integrated into a tool chain such as a compiler of a system, enabling full process automation. In this case, the only additional hardware overhead introduced is the first calibration memristor array 520 and the simple digital control circuitry (not shown in FIG. 5).

For example, the on-chip training may use a linear regression method, or may use other algorithms to adjust the weight values of the first calibration memristor array 520, so that the actual first output data approaches the ideal target output data, so as to achieve the calibration effect.

For example, the order of adjusting the weight values of the first calibration memristor array 520 may be in a parallel manner or a serial manner, or may be in other possible sequential manners, which is not limited by the embodiments of the present disclosure. For example, the operation of adjusting the weight values of the first calibration memristor array 520 may be an accurate quantitative update with read verification, or may be a qualitative symbolic update, or may adopt another operation manner capable of ensuring that the weights are increased or decreased as required, which is not limited by the embodiment of the present disclosure.

In the embodiment of the present disclosure, the first output data of the first computation memristor array is calibrated, and actually, the analog domain computation result in the first processing unit is calibrated, and the first output data already contains the deviation caused by the first computation memristor array in the first processing unit and other possible analog circuits (for example, various analog circuits shown in fig. 2), so that the calibration is a calibration at a processing unit level, and it can be ensured that the analog domain computation result of each processing unit is accurate, so that a system including a plurality of processing units can work normally, and has good reliability and universality. In addition, because each component of the bottom layer is not required to be calibrated, the introduced extra expense is low, and the method has the advantages of high efficiency and low cost; because only the weight value of the introduced first calibration memristor array is calibrated, the hardware overhead can be flexibly configured according to the requirement of calibration precision, and the design as required is realized. Therefore, the calibration method provided by the disclosure solves the key bottleneck of the development of the memory-computation integrated system, and is a core breakthrough of the memristor memory-computation integrated technology towards the practical application stage.

For example, in a calibration method provided by at least one embodiment of the present disclosure, the first memristor array 510 includes M rows by N columns of memristor cells, the first calibration memristor array 520 includes K rows by N columns of memristor cells, an ith column of the first calibration memristor array 520 is connected in series with the ith column of the first computation memristor array 510, the memristor cells of the ith column of the first calibration memristor array 520 are configured to calibrate first output data of the ith column of the first computation memristor array 510 according to first calibration input data to obtain first calibration output data of the ith column, M, N, K, i are positive integers, and 1 ≦ i ≦ N.

It should be noted that the size of the first calibration memristor array 520 is determined by the requirement of calibration accuracy, and the more accurate the simulation calculation result is expected, the larger the calibration range is, the more redundancy weight is required, that is, the larger the size of the first calibration memristor array 520 is required, and in an extreme case, the size of the first calibration memristor array 520 may be larger than the size of the first calculation memristor array 510.

It is further noted that the "rows" and "columns" used in describing the dimensions of the first compute memristor array 510 and the first calibration memristor array 520 are intended only to distinguish two dimensions of the memristor array, and are not limitations of the memristor array.

For example, in the calibration method provided in at least one embodiment of the present disclosure, step S620 includes steps S621 to S623.

Step S621: first training target output data is determined according to the first training calculation input data and the first calculation weight matrix.

Step S622: the first training memristor array 510 is input with first training computational input data, and the first training calibration input data is input with the first calibration memristor array 520 to obtain first training calibration output data.

Step S623: and adjusting the weight values of memristor units in the first calibration memristor array, which correspond to the columns in the first calculation memristor array needing to be calibrated, according to the deviation of the first training calibration output data and the first training target output data.

For step S621, first training input data is input to the first computation memristor array 510, and the first computation memristor array 510 may obtain first training target output data according to the first computation weight matrix.

For example, the first training input data may be randomly generated, or generated according to an input distribution sample of a predetermined training set of a tool chain such as a compiler, or directly be a part of the predetermined training set of the tool chain such as the compiler, which is not limited in this respect by the embodiments of the present disclosure.

For step S622, where the first memristor array 510 inputs the first training memristor input data and the first calibration memristor array 520 inputs the first training calibration input data, the entirety of both the first memristor array 510 and the first calibration memristor array 520 may be calculated to obtain the first training calibration output data.

For step S623, according to the deviation between the first training calibration output data and the first training target output data, only adjusting the weight values of the memristor cells in the first calibration memristor array 520 corresponding to the columns in the first computation memristor array 510 that need to be calibrated, but not adjusting the weight values of the memristor cells in the columns in the first computation memristor array 510 that need to be calibrated, so as to calibrate the deviation.

For example, each memristor cell in the first calibrated memristor array 510 is configured to be capable of implementing both positive and negative weights.

It should be noted that, the above embodiment schematically illustrates an iterative process of on-chip training of the first calibration memristor array, in an actual situation, multiple iterative processes are usually required to make the calibration result meet the requirement, and since each iterative process in the multiple iterative processes is the same as steps S621 to S623, details are not repeated here.

It should be noted that, in order to prevent the number of iterations from being too large, the maximum number of iterations may be set to save resources.

For example, fig. 7 is a schematic diagram of an example of a first processing unit provided in an embodiment of the present disclosure. As shown in fig. 7, the first processing unit 700 includes a first computational memristor array 710 and a first calibration memristor array 720. In fig. 7, the first calibration memristor array 720 includes a fixed-offset calibration subarray 720a and a dynamic-offset calibration subarray 720 b. The fixed offset calibration subarray 720a is configured to calibrate fixed offset and the dynamic offset calibration subarray 720b is configured to calibrate dynamic offset. It is noted that, in embodiments of the present disclosure, the first calibration memristor array 720 may include either or both of the fixed-offset calibration subarray 720a and the dynamic-offset calibration subarray 720b, and in the case where the first calibration memristor array 720 includes both of the fixed-offset calibration subarray 720a and the dynamic-offset calibration subarray 720b, either or both of the fixed-offset calibration subarray 720a and the dynamic-offset calibration subarray 720b may be used. For example, either or both of the fixed offset calibration subarray 720a and the dynamic offset calibration subarray 720b may be selected by a switching (not shown in fig. 7) control manner to flexibly control the first calibration memristor array as desired.

It should also be noted that the 1R (i.e., one resistance element) type of memristor in fig. 7 is merely exemplary and not limiting to the present disclosure, and the memristor may be of different types according to practical situations. For example, the memristor may also be of the 1T1R (i.e., one resistive element plus one transistor) type.

It is further noted that the dimensions of the first calibration memristor array 720 in FIG. 7 are merely exemplary, and not limiting of the present disclosure, and that the dimensions of the first calibration memristor array 720 may be determined according to the particular intelligent computing scenario and task being addressed and its accuracy requirements. Also, in fig. 7, the fixed offset calibration subarray 720a employs an array expansion mode and the dynamic offset calibration subarray 720b employs an independent multi-column mode, which is also exemplary and not limiting to the present disclosure, and the modes of the fixed offset calibration subarray 720a and the dynamic offset calibration subarray 720b may be more specific.

For example, in one example of an embodiment of the present disclosure, the first calibration memristor array includes a fixed-offset calibration subarray (e.g., fixed-offset calibration subarray 720a shown in fig. 7), the first training calibration input data includes fixed-training calibration input data, and the fixed-offset calibration subarray includes 1 row by N columns of memristor cells. In this case, inputting the first training calibration input data to the first calibration memristor array in step S622 includes: and inputting fixed training calibration input data to the fixed offset calibration subarrays.

For example, in another example of an embodiment of the present disclosure, the first calibration memristor array includes a dynamic misalignment calibration subarray (e.g., the dynamic misalignment calibration subarray 720b shown in fig. 7), the first training calibration input data includes dynamic training calibration input data, the dynamic misalignment calibration subarray including at least 1 row by N columns of memristor cells. In this case, inputting the first training calibration input data to the first calibration memristor array in step S622 includes: calculating input data according to the first training, and determining dynamic training calibration input data; and inputting dynamic training calibration input data to the dynamic bias calibration subarrays.

For example, in yet another example of an embodiment of the present disclosure, the first calibration memristor array includes a fixed bias calibration subarray and a dynamic bias calibration subarray (fixed bias calibration subarray 720a and dynamic bias calibration subarray 720b shown in fig. 7), the first training calibration input data includes fixed training calibration input data and dynamic training calibration input data, the fixed bias calibration subarray includes 1 row N columns of memristor cells, and the dynamic bias calibration subarray includes at least 1 row N columns of memristor cells. In this case, inputting the first training calibration input data to the first calibration memristor array in step S622 includes: inputting fixed training calibration input data to the fixed deviation calibration subarray; calculating input data according to the first training, and determining dynamic training calibration input data; and inputting dynamic training calibration input data to the dynamic bias calibration subarrays.

In an embodiment of the present disclosure, the fixed training calibration input data is the same for each of the N columns of the fixed offset calibration subarray.

For example, the fixed training calibration input data is a fixed-bias voltage pulse.

For example, where the first training computational input data for each row of the first computational memristor array is 0 or 1, the fixed training calibration input data may be fixedly set to 1 and unchanged as a function of the first training computational input data.

For example, the fixed training calibration input data may be set to 5% -20% of the maximum value of the first training calculation input data, taking into account that the deviation between the actual first output data and the ideal target output data tends to be relatively small. In this case, inputting fixed training calibration input data to the fixed offset calibration subarray includes: inputting 5% -20% of the maximum value of the first training calculation input data to the stuck-at-bias calibration subarray as stuck-at training calibration input data.

In embodiments of the present disclosure, the dynamic training calibration input data is dynamically determined and may be different for each of the N columns of the dynamic offset calibration subarray.

For example, in one example of an embodiment of the present disclosure, before on-chip training the first calibration memristor array based on the first calculated memristor array written with the first calculated weight matrix and the first calculated weight matrix to adjust the weight values of the first calibration memristor array, the calibration method further includes step S630 a: at least one memristor cell in a critical weight position of an ith column of the first computational memristor array is determined, and an input of the at least one memristor cell in the ith column of the dynamic misalignment calibration subarray is set to be the same as an input of the at least one memristor cell in the critical weight position of the ith column of the first computational memristor array. In this case, determining dynamic training calibration input data based on the first training calculation input data includes: the first training calculation input data of at least one memristor cell in a critical weight position of an ith column of the first computational memristor array is used as dynamic training calibration input data of at least one memristor cell of an ith column of the dynamic offset calibration subarray.

For example, the proportion of the key weight positions of the columns in the first calculation memristor array can be determined according to actual conditions, the key weight positions of the columns are defined in the first calculation memristor array according to the determined proportion, for example, the weights of the columns can be sorted according to the fluctuation degree and the fluctuation-effect degree, the corresponding positions of the memristors with the higher influence degrees are selected as the key weight positions of the columns according to the determined proportion, and the key weight positions of the columns in the first calculation memristor array may not be the same; meanwhile, the number of the key weight positions of each column of the first calculation memristor array is the same as the number of weight units accessed by each column of the dynamic deviation calibration subarray, if the ith column of the first calculation memristor array is in one-to-one correspondence with the ith column of the dynamic deviation calibration subarray, the input of the key weight of the ith column of the first calculation memristor array is shared with the input of each row of the ith column of the dynamic deviation calibration subarray, and therefore the dynamic input of the ith column of the dynamic deviation calibration subarray is determined, namely the first training calculation input data of the key weight position of the ith column of the first calculation memristor array is shared by the ith column of the dynamic deviation calibration subarray.

For example, fig. 8 is a schematic diagram of one example of dynamically determining dynamic training calibration input data provided by an embodiment of the present disclosure. In the example shown in fig. 8, the number of critical weight locations for each column of the first computational memristor array 810 is determined to be 2, and correspondingly, the size of the dynamic misalignment calibration subarray 820b is 2 rows. For example, in fig. 8, the memristor cells of row 1 and row j of column 1 of the first computational memristor array 810 are determined to be memristor cells at critical weight locations, and the inputs of row 1 and row 2 of column 1 of the dynamic misalignment calibration subarray 820b are set to be the same as the inputs of the memristor cells of row 1 and row j of column 1 of the first computational memristor array 810, respectively; determining memristor cells of row 1 and row 2 of column 2 of the first computational memristor array 810 as memristor cells at critical weight locations, and setting inputs of row 1 and row 2 of column 2 of the dynamic misalignment calibration subarray 820b to be the same as inputs of memristor cells of row 1 and row 2 of column 2 of the first computational memristor array 810, respectively; the memristor cells of the 2 nd row and the j th row of the 3 rd column of the first computational memristor array 810 are determined to be memristor cells at key weight positions, and the inputs of the 1 st row and the 2 nd row of the 3 rd column of the dynamic misalignment calibration subarray 820b are set to be the same as the inputs of the memristor cells of the 2 nd row and the j th row of the 3 rd column of the first computational memristor array 810, respectively, j being a positive integer greater than or equal to 2. In this way, the dynamic inputs for each column of the dynamic offset calibration subarray 820b may be determined, the inputs for each column of the dynamic offset calibration subarray 820b sharing the input of the critical weight location for the corresponding column of the first calculated memristor array 810.

In implementations of the present disclosure, the dynamic offset calibration subarrays may also employ an array expansion mode. For example, when the dynamic bias calibration subarray employs an array expansion mode, the critical weight locations of the first calibration memristor array may be determined in units of rows.

For example, in another example of an embodiment of the present disclosure, before on-chip training the first calibration memristor array to adjust weight values of the first calibration memristor array based on the first calculated memristor array written with the first calculated weight matrix and the first calculated weight matrix, the calibration method further includes step S630 b: the method further includes determining at least one row of memristor cells of the first computational memristor array at the critical weight location, and setting an input of the at least one row of memristor cells of the dynamic misalignment calibration subarray to be the same as an input of the at least one row of memristor cells of the first computational memristor array at the critical weight location. In this case, determining dynamic training calibration input data based on the first training calculation input data includes: the first training computational input data of at least one row of memristor cells of the first computational memristor array at the key weight location is taken as the dynamic training calibration input data of at least one row of memristor cells of the dynamic offset calibration subarray.

In the implementation of the present disclosure, all columns in the first computation memristor array may be calibrated, or a column in the first computation memristor array that needs to be calibrated may be determined, and only the column in the first computation memristor array that needs to be calibrated is calibrated to save the calculation amount of calibration.

For example, in an embodiment of the present disclosure, on-chip training is performed on the first calibration memristor array based on the first computation memristor array written with the first computation weight matrix and the first computation weight matrix to adjust weight values of the first calibration memristor array (step S620), further including step S624: inputting first training computational input data to the first computational memristor array to obtain first training output data, before inputting the first training computational input data to the first computational memristor array and inputting the first training calibration input data to the first calibration memristor array to obtain first training calibration output data (step S622); according to the deviation of the first training output data and the first training target output data, columns needing to be calibrated in the first calculation memristor array are determined, and memristor units, corresponding to the columns needing to be calibrated in the first calculation memristor array, in the first calibration memristor array are communicated with the columns needing to be calibrated in the first calculation memristor array in series.

For example, fig. 9A is a flowchart of an example of a calibration method provided in at least one embodiment of the present disclosure, and the calibration method 900a includes steps S910a to S950 a. As shown in fig. 9A, at step S910a, determining a structure and a size of a first calibration memristor array, the determining the structure of the first calibration memristor array referring to determining that the first calibration memristor array includes or selects one or both of a solid-state-bias calibration subarray and a dynamic-bias calibration subarray, the determining the size of the first calibration memristor array referring to determining a number of rows and columns of the first calibration memristor array according to a correction accuracy requirement; at step S920a, mapping a first weight computation matrix, e.g., deployed, mapped by a tool chain such as a compiler, to a first computation memristor array of each processing unit; at step S930a, determining key weight locations for the columns of the first computational memristor array, e.g., selecting, locating respective key weight locations for the columns according to the determined proportions; at step S940a, determining first training calibration input data, e.g., fixed training calibration input data being 5% -20% of a maximum value of the first training computational input data, inputs of different rows of columns of the dynamic deviation standard subarray being shared in real time with inputs of key weight positions of corresponding columns of the first computational memristor array; at step S950a, all columns of the first calibration memristor array are on-chip trained to achieve calibration, for example, using a linear regression method, on-chip training, adjusting the weight values of the fixed-bias calibration subarray and the dynamic-bias calibration subarray, until the deviation between the actual first output data and the ideal target output data reaches a suitable interval or the on-chip training reaches the maximum number of iterations. In this example, the columns in the first memristor array that require calibration are not predetermined, and all of the columns in the first memristor array are calibrated.

For example, fig. 9B is a flowchart of another example of a calibration method provided in at least one embodiment of the present disclosure, and the calibration method 900B includes steps S910B to S960B. As shown in fig. 9B, at step S910B, determining a structure and a size of the first calibration memristor array, the determining the structure of the first calibration memristor array referring to determining that the first calibration memristor array includes or selects one or both of a solid-state-bias calibration subarray and a dynamic-bias calibration subarray, the determining the size of the first calibration memristor array referring to determining a number of rows and columns of the first calibration memristor array according to the correction accuracy requirement; at step S920b, mapping a first weight computation matrix, e.g., deployed, mapped by a tool chain such as a compiler, to a first computation memristor array of each processing unit; at step S930b, determining key weight locations for the columns of the first computational memristor array, e.g., selecting, locating respective key weight locations for the columns according to the determined proportions; at step S940b, determining first training calibration input data, e.g., fixed training calibration input data being 5% -20% of a maximum value of the first training computational input data, inputs of different rows of columns of the dynamic deviation standard subarray being shared in real time with inputs of key weight positions of corresponding columns of the first computational memristor array; at step S950b, columns in the first computational memristor array requiring calibration are determined and turned on, e.g., determined and turned on as described in step S624; at step S960b, the columns of the first calibration memristor array that need to be calibrated are on-chip trained to achieve calibration, for example, by using a linear regression method, on-chip training, and adjusting the weight values of the fixed offset calibration subarray and the dynamic offset calibration subarray until the deviation between the actual first output data and the ideal target output data reaches a suitable interval or the on-chip training reaches the maximum number of iterations. In the present example, the columns in the first memristor array that require calibration are predetermined, and only the columns in the first memristor array that require calibration are calibrated.

In an embodiment of the present disclosure, a computationally integrated apparatus includes a plurality of processing units. For example, the integrative computing device further comprises a second processing unit comprising a second computing memristor array and a second calibration memristor array, the second computing memristor array configured to receive second computing input data determined from the first calibration output data and to compute the second computing input data to obtain second output data; the second calibration memristor array is configured to receive second calibration input data and calibrate second output data according to the second calibration input data to obtain second calibration output data; the second processing unit is configured to output second calibration output data; the calibration method further comprises: determining a second calculation weight matrix corresponding to the second calculation memristor array through off-chip training, and writing the second calculation weight matrix into the second calculation memristor array; on the basis of the computation output of the second computation memristor array written with the second computation weight matrix and the second computation weight matrix, on-chip training is performed on the second calibration memristor array to adjust the weight value of the second calibration memristor array.

It should be noted that, for the plurality of processing units included in the integrated computing device, a plurality of calibration sequences may be adopted, and the embodiment of the present disclosure is not limited thereto. For example, multiple processing units may be independently calibrated in parallel. For example, the plurality of processing units may also be calibrated stage by stage.

For example, in an embodiment of the present disclosure, a second processing unit is coupled with the first processing unit, the second processing unit, based on the second computational memristor array written with the second computational weight matrix and the second computational weight matrix, in on-chip training of the second calibration memristor array to adjust weight values of the second calibration memristor array, determining first training target output data based on the first training computational input data and the first computational weight matrix, and the first training target output data is used as second training input data of a second computing memristor array, or, inputting first training memristor input data to a first computing memristor array with a first training memristor array trained, inputting first training calibration input data to the first calibration memristor array, to obtain first training calibration output data, and using the first training calibration output data as second training input data of the second computational memristor array.

For example, fig. 10A is a schematic diagram of an independent parallel calibration method according to at least one embodiment of the present disclosure. As shown in fig. 10A, when the calculation weight matrix of each processing unit is divided and deployed in the compiling stage, ideal calculation input data of each processing unit is determined, training calculation input data of each processing unit is respectively constructed by using the ideal calculation input data of each processing unit, and each processing unit can be independently calibrated in parallel.

For example, fig. 10B is a schematic diagram of a progressive calibration method according to at least one embodiment of the present disclosure. As shown in fig. 10B, the levels of the respective processing units in the plurality of processing units are divided according to the layer to which the weight belongs during deep learning, the first-stage processing unit performs calibration first, and the corresponding input is training calculation input data constructed using ideal calculation input data of the first-stage processing unit; the output of the calibrated first stage processing unit under the training computational input data constructed using the ideal computational input data is used as the input to the next stage processing unit and the next stage processing unit is calibrated, and so on.

In the example shown in fig. 10A, the calibration input of each stage of processing units is based on ideal calculation input data confirmed at the compilation stage, whereas, in the example shown in fig. 10B, the calibration input of each stage of processing units (except for the first stage) is based on the actual output of the processing unit of the previous stage after calibration (which may deviate from the ideal calculation input data at the compilation stage). In contrast, the scheme shown in fig. 10B is more complex, but has better error adaptability and higher system calibration accuracy.

In summary, the present disclosure provides a middle-level and middle-granularity calibration method for a calculation result in a simulation domain, and designs a supporting architecture and an operation flow. According to the various embodiments and examples thereof, the calibration method provided by the present disclosure can implement unit-level calibration, and ensure accurate calculation results of the analog domain of each processing unit, thereby ensuring that a system including a plurality of processing units works normally, and having good reliability and universality. In addition, because each component of the bottom layer is not required to be calibrated, the introduced extra expense is low, and the method has the advantages of high efficiency and low cost; because only the weight value of the introduced first calibration memristor array is calibrated, the hardware overhead can be flexibly configured according to the requirement of calibration precision, and the design as required is realized. Therefore, the calibration method provided by the disclosure solves the key bottleneck of the development of the memory-computation integrated system, and is a core breakthrough of the memristor memory-computation integrated technology towards the practical application stage.

At least one embodiment of the present disclosure provides a memory-computation integrated device, including a first processing unit, where the first processing unit includes a first computation memristor array and a first calibration memristor array, and the first computation memristor array is configured to receive first computation input data and compute the first computation input data to obtain first output data; the first calibration memristor array is configured to receive first calibration input data and calibrate first output data according to the first calibration input data to obtain first calibration output data; the first processing unit is configured to output first calibration output data. For example, the first processing unit may refer to the related description of the first processing unit 500, which is not described herein again.

For example, in the integrated memory device provided by at least one embodiment of the present disclosure, the first computation memristor array includes M rows by N columns of memristor cells, the first calibration memristor array includes K rows by N columns of memristor cells, an ith column of the first calibration memristor array is connected in series with an ith column of the first computation memristor array, the memristor cells of the ith column of the first calibration memristor array are configured to calibrate first output data of the ith column of the first computation memristor array according to first calibration input data to obtain first calibration output data of the ith column, M, N, K, i are positive integers, and 1 ≦ i ≦ N. For example, the first processing unit may refer to the related description of the first processing unit 500, which is not described herein again.

For example, in the integrated memory device provided in at least one embodiment of the present disclosure, the first calibration memristor array includes a fixed offset calibration subarray, the first calibration input data includes fixed calibration input data, the fixed offset calibration subarray includes 1 row × N columns of memristor cells, an ith column of the fixed offset calibration subarray is connected in series with an ith column of the first computation memristor array, and the memristor cells of the ith column of the fixed offset calibration subarray are configured to calibrate the first output data of the ith column of the first computation memristor array according to the fixed calibration input data to obtain the first calibration output data of the ith column. For example, the misalignment calibration subarray may refer to the description of the misalignment calibration subarray 720a, which is not described herein.

For example, in the integrated memory device provided in at least one embodiment of the present disclosure, the first calibration memristor array includes a dynamic misalignment calibration subarray, the first calibration input data includes dynamic calibration input data, memristor cells of the dynamic misalignment calibration subarray include at least 1 row x N columns, an i-th column of the dynamic misalignment calibration subarray is connected in series with an i-th column of the first computation memristor array, dynamic calibration input data corresponding to at least one memristor cell of the i-th column of the dynamic misalignment calibration subarray is determined according to first computation input data corresponding to M memristor cells of the i-th column of the first computation memristor array, the at least one memristor cell of the i-th column of the dynamic misalignment calibration subarray is configured to perform dynamic calibration input data corresponding to the at least one memristor cell of the i-th column of the dynamic misalignment subarray, the first output data of the ith column of the first computing memristor array is calibrated to obtain first calibrated output data of the ith column. For example, the dynamic offset calibration subarray may refer to the description of the dynamic offset calibration subarray 720b, which is not described herein.

For example, in the integrated memory device provided in at least one embodiment of the present disclosure, the first calibration memristor array includes a fixed-deviation calibration subarray and a dynamic-deviation calibration subarray, the first calibration input data includes fixed-calibration input data and dynamic-calibration input data, the fixed-deviation calibration subarray includes 1 row × N columns of memristor cells, the dynamic-deviation calibration subarray includes at least 1 row × N columns of memristor cells, an ith column of the fixed-deviation calibration subarray and an ith column of the dynamic-deviation calibration subarray are connected in series with an ith column of the first computation memristor array, dynamic-calibration input data corresponding to at least one memristor cell of the ith column of the dynamic-deviation calibration subarray is determined according to first computation input data corresponding to M memristor cells of the ith column of the first computation memristor array, the memristor cell of the ith column of the fixed-deviation calibration subarray and at least one memristor cell of the ith column of the dynamic-deviation calibration memristor array The first output data of the ith column of the first computational memristor array is calibrated by the unit according to the fixed calibration input data and the dynamic calibration input data corresponding to at least one memristor unit of the ith column of the dynamic deviation calibration subarray, so as to obtain first calibration output data of the ith column. For example, the fixed offset calibration subarray may refer to the description related to the fixed offset calibration subarray 720a, and the dynamic offset calibration subarray may refer to the description related to the dynamic offset calibration subarray 720b, which is not described herein again.

For example, in at least one embodiment of the present disclosure, the fixed calibration input data is 5% -20% of the maximum value of the first calculation input data.

For example, in the integrated memory device provided by at least one embodiment of the present disclosure, the dynamic calibration input data corresponding to at least one memristor cell of the ith column of the dynamic offset calibration subarray is the same as the first calculation input data corresponding to at least one memristor cell in the critical weight position of the ith column of the first calculation memristor array. For example, the dynamic misalignment calibration subarray may refer to the description related to the dynamic misalignment calibration subarray 820b, and the configuration of the dynamic calibration input data may refer to the description related to step S630a, which is not described herein again.

For example, in the integrated memory device provided by at least one embodiment of the present disclosure, the dynamic calibration input data corresponding to at least one row of memristor cells of the dynamic offset calibration subarray is the same as the first calculation input data corresponding to at least one row of memristor cells of the first calculation memristor array at the critical weight location. For example, the configuration of the dynamic calibration input data may refer to the related description of step S630b, and will not be described herein again.

It should be noted that, for clarity and conciseness of representation, not all the components of the integrated storage device, nor all the components of the processing unit included in the integrated storage device, are given in the embodiments of the present disclosure. In order to realize the necessary functions of the integrated storage device and the processing unit included therein, those skilled in the art may provide and arrange other components not shown according to specific needs, and the embodiment of the present disclosure is not limited thereto.

Regarding technical effects of the integrated computing device and the processing unit included in the integrated computing device in different embodiments, reference may be made to the technical effects of the calibration method of the integrated computing device provided in the embodiments of the present disclosure, and details are not described herein again.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.