阅读说明：本技术 存储设备、包括所述存储设备的电子系统及其操作方法 (Memory device, electronic system including the same, and method of operating the same ) 是由 裴德镐 金东昱 柳炯宇 罗广贤 黄珠荣 崔侑罗 于 2019-05-31 设计创作，主要内容包括：一种电子系统包括主机设备和存储设备,所述存储设备包括易失型的第一存储器件和非易失型的第二存储器件。主机设备经由存储器映射的输入-输出接口来访问第一存储器件,且主机设备经由块可访问接口来访问第二存储器件。存储设备为主机设备提供虚拟存储器区域,使得包括在第一存储器件中的具有第一大小的主机专用存储器区域被映射到具有第二大小的虚拟存储器区域,其中第二大小大于第一大小。(An electronic system includes a host device and a storage device including a first storage device of a volatile type and a second storage device of a nonvolatile type. The host device accesses the first storage device via the memory-mapped input-output interface, and the host device accesses the second storage device via the block-accessible interface. The storage device provides the host device with a virtual memory region such that a host private memory region having a first size included in the first storage device is mapped to a virtual memory region having a second size, wherein the second size is larger than the first size.)

1. An electronic system, comprising:

a host device; and

a memory device including a first memory device of a volatile type and a second memory device of a non-volatile type,

wherein the first storage device is accessed by the host device via a memory-mapped input-output interface,

the second storage device is accessed by the host device via the block accessible interface, and

the storage device is configured to provide the host device with a virtual memory region such that a host private memory region having a first size included in the first storage device is mapped to a virtual memory region having a second size, wherein the second size is larger than the first size.

2. The electronic system of claim 1, wherein the storage device generates a dynamic mapping table comprising mappings between real addresses of the host-specific memory region and virtual addresses of the virtual memory region, and dynamically changes mappings of the dynamic mapping table according to a progress of an access operation of the host device for the virtual memory region.

3. The electronic system of claim 2, wherein the host device generates a static mapping table and provides the static mapping table to the storage device, wherein the static mapping table includes a mapping relationship between virtual addresses of the virtual memory regions and logical block addresses of flushed memory regions having a second size included in the second storage device.

4. The electronic system of claim 3, wherein the static mapping table further includes occupancy state information indicating whether data is stored at each logical block address mapped to a corresponding virtual address.

5. The electronic system of claim 4, wherein when accessing a first virtual address, the storage device determines whether to perform a load operation to store data mapped to a first logical block address of the first virtual address to a first real address mapped to the first virtual address based on the occupancy status information.

6. The electronic system of claim 2, wherein the storage device supports non-volatility of the virtual memory region such that all data stored in the virtual memory region remains even if power to the storage device is blocked.

7. The electronic system according to claim 2, wherein the storage device sets a persistent memory area including a plurality of flushing units with respect to the host-dedicated memory area, and performs a flushing operation to store data of one flushing unit of the plurality of flushing units in the second storage device when a write operation for the one flushing unit is completed.

8. The electronic system of claim 7, wherein the host device performs an append write operation to store data in the virtual memory region as virtual addresses increase, wherein the virtual addresses increase in sequence.

9. The electronic system of claim 8, wherein the storage device increases a flush location corresponding to a start location of the persistent memory region by a flush size of each flush unit in order from a start address of the host-specific memory region whenever a flush operation for each flush unit is completed, and returns the flush location to the start address of the host-specific memory region when the flush location reaches a last address of the host-specific memory region.

10. The electronic system of claim 8, wherein the storage device generates a flush status table comprising a mapping relationship between the plurality of flush units and real addresses where the append write operation has been performed, and performs a flush operation based on the flush status table.

11. The electronic system of claim 7, wherein the host device performs a random write operation to store data in the virtual memory region regardless of a sequential order of virtual addresses.

12. The electronic system of claim 11, wherein the dynamic mapping table further comprises write order information indicating an order of real addresses for which the random write operations have been performed.

13. The electronic system of claim 12, wherein the storage device generates a flush status table including the write order information and a mapping relationship between the plurality of flush units and real addresses at which the random write operation has been performed, and performs a flush operation based on the flush status table.

14. The electronic system of claim 7, further comprising an auxiliary power device configured to provide power to the storage device when an interruption occurs in input power provided to the storage device,

wherein the flush size of each of the plurality of flush units is determined within a power supply capacity of the auxiliary power supply apparatus.

15. The electronic system of claim 1, wherein the host-specific memory region comprises a plurality of sub-host-specific memory regions, the virtual memory region comprises a plurality of sub-virtual memory regions mapped to the plurality of sub-host-specific memory regions, respectively, and each of the plurality of sub-virtual memory regions is uniquely provided to one of a plurality of applications of the host device.

16. A storage device, comprising:

a first storage device configured to be accessed by a host device via a memory-mapped input-output interface;

a second storage device configured to be accessed by the host device via a block-accessible interface; and

a virtual memory controller configured to provide the host device with a virtual memory region such that a host private memory region having a first size included in the first storage device is mapped to a virtual memory region having a second size, wherein the second size is larger than the first size.

17. The storage device of claim 16, wherein the virtual memory controller comprises a mapping manager configured to: generating a dynamic mapping table including a mapping relationship between real addresses of the host dedicated memory area and virtual addresses of the virtual memory area, and dynamically changing the mapping relationship of the dynamic mapping table according to a progress of an access operation of the host device for the virtual memory area.

18. The storage device of claim 17, wherein the virtual memory controller further comprises an internal transfer manager configured to: controlling data transfer between the first storage device and the second storage device based on the dynamic mapping table, a static mapping table, and occupancy status information, wherein the static mapping table includes a mapping relationship between virtual addresses of the virtual memory regions and logical block addresses of a flush memory region of a second size included in the second storage device, the occupancy status information indicating whether data is stored at each logical block address mapped to a corresponding virtual address;

the virtual memory controller provides the static mapping table to the storage device.

19. The storage device of claim 18, wherein the internal transfer manager sets a persistent memory area including a plurality of flushing units for the host-dedicated memory area, and performs a flushing operation to store data of one flushing unit of the plurality of flushing units in the second storage device when a write operation for the one flushing unit is completed.

20. A method of operating an electronic system comprising a host device and a storage device, the method comprising:

accessing, by the host device, a first storage device included in the storage device via a memory-mapped input-output interface;

accessing, by the host device, a second storage device included in the storage device via a block-accessible interface; and

providing, by the storage device, a virtual memory region to the host device such that a host private memory region having a first size included in the first storage device is mapped to a virtual memory region having a second size, wherein the second size is larger than the first size.

Technical Field

Example embodiments of the inventive concepts relate generally to semiconductor integrated circuits, and more particularly, to a memory device providing a virtual memory area, an electronic system including the memory device, and an operating method of the electronic system.

Background

Generally, an embedded system may run software using, for example, a volatile memory such as a Dynamic Random Access Memory (DRAM) as a main memory and a non-volatile memory such as a NAND flash memory for storing user data. DRAM provides relatively fast read and write speeds and supports byte access. However, since the DRAM is a volatile memory, power consumption may be large because it requires a regular refresh process. Therefore, DRAMs are commonly used to store software read/write (R/W) data. NAND flash memory generally supports input/output (I/O) processing in units of pages (e.g., 2KB), and is therefore not typically used to execute code or store software R/W data. However, the NAND flash memory is generally used to store user data due to various characteristics including a fast R/W speed, low cost, and large capacity when transferring a large amount of data. Therefore, designing a system including these various memories increases design complexity and manufacturing costs, as the various memories are used in different ways and have different functions.

Disclosure of Invention

According to example embodiments of the inventive concepts, an electronic system includes a host device and a storage device including a first storage device of a volatile type and a second storage device of a non-volatile type. The host device accesses the first storage device via the memory-mapped input-output interface, and the host device accesses the second storage device via the block-accessible interface. The storage device provides the host device with a virtual memory region such that a host private memory region having a first size included in the first storage device is mapped to a virtual memory region having a second size, wherein the second size is larger than the first size.

According to an example embodiment of the inventive concepts, a storage device includes: a first storage device configured to be accessed by a host device through a memory-mapped input-output interface; a second storage device configured to be accessed by a host device via the block-accessible interface; and a virtual memory controller. The virtual memory controller provides a virtual memory region for the host device such that a host private memory region having a first size included in the first storage device is mapped to a virtual memory region having a second size, wherein the second size is larger than the first size.

According to an example embodiment of the inventive concepts, a method of operating an electronic system including a host device and a storage device includes: accessing, by a host device, a first storage device included in a storage device via a memory-mapped input-output interface, and a second storage device included in the storage device via a block-accessible interface; and providing, by the storage device, the virtual memory area for the host device such that a host private memory area having a first size included in the first storage device is mapped to a virtual memory area having a second size, the second size being larger than the first size.

Drawings

The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a flowchart illustrating a method of operating an electronic system according to an example embodiment of the inventive concepts.

Fig. 2 is a block diagram illustrating an electronic system according to an example embodiment of the inventive concepts.

Fig. 3 is a diagram illustrating address mapping in an electronic system according to an example embodiment of the inventive concepts.

Fig. 4 is a diagram illustrating a virtual memory area and a host dedicated memory area in an electronic system according to an example embodiment of the inventive concepts.

Fig. 5 is a diagram illustrating a dynamic mapping table in an electronic system according to an exemplary embodiment of the inventive concept.

Fig. 6 and 7 are diagrams illustrating a static mapping table in an electronic system according to an example embodiment of the inventive concepts.

Fig. 8 is a block diagram illustrating a virtual memory controller included in a storage device according to an example embodiment of the inventive concepts.

Fig. 9 is a diagram illustrating an additional write operation in an electronic system according to an example embodiment of the inventive concepts.

Fig. 10 is a diagram illustrating a mapping relationship of a dynamic mapping table according to an additional write operation of fig. 9 according to an example embodiment of the inventive concept.

Fig. 11 is a diagram illustrating a setting of a permanent memory area according to an append write operation of fig. 9 according to an example embodiment of the inventive concept.

Fig. 12 is a diagram illustrating a setting of a permanent memory area according to an append write operation of fig. 9 according to an example embodiment of the inventive concept.

Fig. 13 is a diagram illustrating a random write operation in an electronic system according to an example embodiment of the inventive concepts.

Fig. 14 is a diagram illustrating a mapping relationship of a dynamic mapping table according to the random write operation of fig. 13, according to an example embodiment of the inventive concept.

Fig. 15 is a diagram illustrating a setting of a permanent memory area according to the random write operation of fig. 13 according to an example embodiment of the inventive concepts.

Fig. 16 is a flowchart illustrating a method of operating an electronic system according to an example embodiment of the inventive concepts.

Fig. 17 is a diagram illustrating an example command of a block accessible interface according to an example embodiment of the inventive concepts.

Fig. 18 is a diagram illustrating address mapping in an electronic system according to an example embodiment of the inventive concepts.

Fig. 19 is a block diagram illustrating a storage device according to an example embodiment of the inventive concepts.

Fig. 20 is a block diagram illustrating a power down protection (PLP) circuit included in the electronic device of fig. 19 according to an example embodiment of the inventive concepts.

Fig. 21 is a diagram illustrating determining a flushing size in an electronic system according to an example embodiment of the inventive concept.

Fig. 22 is a block diagram illustrating an electronic system according to an example embodiment of the inventive concepts.

Fig. 23 is a block diagram illustrating a mobile device according to an example embodiment of the inventive concepts.

Detailed Description

Example embodiments of the inventive concepts may provide a storage device that efficiently provides storage space for a host device.

Example embodiments of the inventive concepts may also provide an electronic system including the storage device and the host device and a method of operating the electronic system.

Example embodiments of the inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the application.

Fig. 1 is a flowchart illustrating a method of operating an electronic system according to an exemplary embodiment of the inventive concept, and fig. 2 is a block diagram illustrating an electronic system according to an exemplary embodiment of the inventive concept.

Referring to fig. 1 and 2, the host device 100 accesses a first memory device MEM1210 included in the memory device 200 via a memory mapped input-output (MMIO) interface 30 (S100). Further, the host device 100 accesses the second memory device MEM2220 included in the memory device 200 via the block accessible interface 40 (S200). The storage apparatus 200 provides the host apparatus 100 with a virtual memory area such that a host private memory area having a first size included in the first storage device MEM1210 is mapped to a virtual memory area having a second size, wherein the second size is larger than the first size (S300).

As will be described below with reference to fig. 3, 4, and 5, the storage device 200 may generate the dynamic mapping table DMT including the mapping relationship between the real addresses RAl to RAm of the host dedicated memory area HDMR and the virtual addresses VAl to VAn of the virtual memory area VMR, and dynamically change the mapping relationship of the dynamic mapping table DMT according to the progress of the access operation of the host device 100 with respect to the virtual memory area VMR. In this way, it is possible to provide the virtual memory region VMR having a larger size than the host dedicated memory region HDMR corresponding to the real memory resource by dynamically changing the mapping relationship between the host dedicated memory region HDMR and the virtual memory region VMR, thereby reducing the size and enhancing the performance of the storage apparatus 200 and the electronic system 1000 including the storage apparatus 200.

As will be described below with reference to fig. 3, 6, and 7, the host device 100 may generate a static mapping table SMT including a mapping relationship between virtual addresses VA1 through VAn of a virtual memory region VMR and logical block addresses LBA1 through LBAn of a flush memory region FMR having a second size included in the second storage device MEM2220, and provide the static mapping table SMT to the storage device 200. In this way, the host device 100 and the storage device 200 may share the static mapping table SMT to efficiently support byte-wise access and block-wise access between the host device and the storage device.

As will be described below with reference to fig. 9 to 15, the memory device 200 may set a permanent memory region PMR including a plurality of flush units FU1 and FU2 with respect to the host-dedicated memory region HDMR, and perform a flush operation to store data of one flush unit among the plurality of flush units FU1 and FU2 in the second memory device MEM2220 when a write operation for the one flush unit is completed. In this way, the non-volatility of the virtual memory area VMR can be supported by the flushing operation, and the byte-wise access and block-wise access between the host device and the storage device can be effectively supported to enhance the performance of the storage device 200 and the electronic system 1000.

Referring to fig. 2, an electronic system 1000 includes a host device 100 and a storage device 200. The host device 100 may include at least one processor 110, such as a Central Processing Unit (CPU). The memory device 200 may include a first memory device MEMl210, a second memory device MEM2220, a virtual memory controller VMCON 230, and a block controller BLCON 240.

The processor 110 may generate the static mapping table SMT as described with reference to fig. 3, 6 and 7. The processor 110 may generate a byte access command BTCMD for accessing the first memory device MEM1210 and a block access command STCMD for accessing the second memory device MEM2220 based on mapping information of the static mapping table SMT.

The processor 110 may determine whether to store data at a logical block address LBA of the second memory device MEM2220, which is mapped to a virtual address VA of the virtual memory area VMR, based on the occupancy state information OCS of the static mapping table SMT; and the processor 110 may selectively perform an access in units of bytes with respect to the first memory device MEM1210 or an access in units of blocks with respect to the second memory device MEM2220 based on the determination.

The virtual memory controller 230 may receive a byte access command BTCMD via the MMIO interface 30. The virtual memory controller 230 may perform an access in units of bytes with respect to the first memory device MEM1210 based on the byte access command BTCMD.

The block controller 240 may receive a block access command STCMD via the block-accessible interface 40. The block controller 240 may perform access in units of blocks based on the block access command STCMD.

In addition, the virtual memory controller 230 and the block controller 240 may perform internal data transfer between the first memory device MEM1210 and the second memory device MEM 2220. The internal data transfer may include a flush operation corresponding to a data transfer from the first memory device MEMl210 to the second memory device MEM2220 and a load operation corresponding to a data transfer from the second memory device MEM2220 to the first memory device MEMl210, which will be described below.

Each of the MMIO interface 30 and the block-accessible interface 40 may be implemented as hardware, such as a bus system, software, such as a driver, or a combination of hardware and software.

In example embodiments of the inventive concepts, the first memory device MEM1210 of the memory device 200 may be connected to the processor 110 of the host device 100 via an MMIO interface 30, wherein said MMIO interface 30 may comprise, for example, a peripheral component interconnect express (PCIe) bus or the like. The virtual memory controller 230 of the storage device 200 can provide the MMIO interface 30 to the host device 100 using a byte-accessible address space larger than the host-specific memory region HDMR, thereby allowing access in bytes to the data stored in the host-specific memory region HDMR. In other words, the size of the virtual memory area VMR provided to the host device 100 may be larger than the host private memory area HDMR.

In example embodiments of the inventive concepts, the second storage device MEM2220 of the storage device 200 may be connected with the processor 110 of the host device 100 via a block-accessible interface 40, wherein the block-accessible interface 40 may comprise, for example, a Serial Advanced Technology Attachment (SATA) bus, a non-volatile memory express (NVMe) bus, a serial attached scsi (sas) bus, or the like. The memory device 200 may use a block-accessible address space corresponding to an access size of the second memory device MEM2220 to provide the host device 100 with a block-accessible interface 40 to allow access in units of blocks to data stored in the second memory device MEM 2220.

The first memory device MEM1210 may be any memory device that can be accessed by the host device 100 via the MMIO interface 30. For example, the first memory device MEM1210 may be a volatile memory device having a fast operation speed, such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like.

The second memory device MEM2220 may be any memory device that can be accessed by the host device 100 via the block-accessible interface 40. For example, the second memory device MEM2220 may be a non-volatile memory device such as an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a Nano Floating Gate Memory (NFGM), a polymer random access memory (popram), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), or the like.

Fig. 3 is a diagram illustrating address mapping in an electronic system according to an example embodiment of the inventive concepts.

Referring to fig. 3, the virtual address space VAS of the host device 100 may include a virtual memory region VMR and a flush memory region FMR.

The virtual memory area VMR is mapped to the host-specific memory area HDMR of the first memory device MEM 1210. The host-specific memory area HDMR may be part of the first memory device MEMl 210. In other words, the first size SZ1 of the host-dedicated memory area HDMR may be smaller than the size SZV of the first memory device MEMl 210. Here, the size refers to a data storage capacity or a memory capacity.

The host private memory area HDMR may have a first size SZl and the virtual memory area VMR may have a second size SZ2 that is larger than the first size SZl. In order to provide a virtual memory region VMR larger than the host private memory region HDMR corresponding to the real memory resource, the storage apparatus 200 may dynamically change the mapping relationship between the host private memory region HDMR and the virtual memory region VMR.

The second memory device MEM2220 may provide the host apparatus 100 with an address space having the same size SZN as the second memory device MEM 2220. The flush memory region FMR mapped to the virtual memory region VMR may be a part of the second memory device MEM 2220. In other words, the second size SZ2 of the flush memory region FMR may be smaller than the size SZN of the second memory device MEM 2220.

The virtual memory region VMR and the flush memory region FMR may have the same size, e.g., the second size SZ 2. Since the virtual memory region VMR and the flush memory region FMR have the same size, the host device 100 can statically set the mapping relationship between the virtual memory region VMR and the flush memory region FMR without change.

Fig. 4 is a diagram illustrating a virtual memory area and a host dedicated memory area in an electronic system according to an example embodiment of the inventive concepts.

Referring to fig. 4, the virtual memory area VMR and the host private memory area HDMR may be divided into a plurality of unit areas UR having the same size. The virtual addresses VA 1-VAn may be allocated to the cell region UR of the virtual memory region VMR and the real addresses RA 1-RAM may be allocated to the cell region UR of the host-dedicated memory region HDMR. For example, each of the virtual addresses VA 1-VAn and the real addresses RA 1-RAM may be the start address of the corresponding cell region UR.

The size of the cell area UR may be variously determined according to the characteristics and/or operation scenarios of the electronic system. In an example embodiment of the inventive concepts, as shown in fig. 6, one virtual address may correspond to one logical block address, and the size of the unit area UR may correspond to the size of a data block of the second memory device MEM 2220. In an example embodiment of the inventive concepts, as shown in fig. 7, two virtual addresses may correspond to one logical block address, and the size of the unit area UR may correspond to a half size of a data block of the second memory device MEM 2220.

Fig. 5 is a diagram illustrating a dynamic mapping table in an electronic system according to an exemplary embodiment of the inventive concept.

Referring to fig. 5, the dynamic mapping table DMT may include a mapping relationship between the real address RAD of the host-specific memory area HDMR and the virtual address VAD of the virtual memory area VMR.

For example, at time point T1, real addresses RA1, RA2, RA2, and RA4 may be mapped to virtual addresses VAa, VAb, VAc, and VAd, respectively. An "EMP" indicates that the corresponding real address is not mapped to a virtual address. For example, fig. 5 shows that the virtual address is not mapped to the real address RAm.

Such a mapping relationship between the real address RAD and the virtual address VAD may change according to the progress of the access operation of the host device 100 to the virtual memory region VMR. For example, at a time point T2 different from the time point T1, real addresses RA1, RA2, RA2, RA4, and RAm may be mapped to virtual addresses VAf, VAg, Vah, VAi, and VAj, respectively.

The dynamic mapping table DMT at the time point T1 indicates the mapping relationship between the virtual address most recently accessed from the time point T1 and the corresponding real address, and similarly, the dynamic mapping table DMT at the time point T2 indicates the mapping relationship between the virtual address most recently accessed from the time point T2 and the corresponding real address.

In this way, the storage apparatus 200 can provide the virtual memory region VMR having a larger size than the host dedicated memory region HDMR corresponding to the real memory resource by dynamically changing the mapping relationship between the host dedicated memory region HDMR and the virtual memory region VMR, thereby reducing the size and enhancing the performance of the storage apparatus 200 and the electronic system 1000 including the storage apparatus 200.

Fig. 6 and 7 are diagrams illustrating a static mapping table in an electronic system according to an example embodiment of the inventive concepts.

Referring to fig. 6 and 7, the static mapping table SMT may include a mapping relationship between a virtual address VAD of the virtual memory region VMR and a logical block address LBAD of the flush memory region FMR. In addition, the static mapping table SMT may further include occupancy status information OCS indicating whether data is stored at each logical block address LBAD mapped to the corresponding virtual address VAD. When data is stored at a logical block address LBA mapped to a virtual address VAD, the occupancy status information OCS may have a first value OC; and the occupancy status information OCS may have the second value UO when data is not stored at the logical block address LBA.

In an example embodiment of the inventive concept, one virtual address VAD may correspond to one logical block address LBAD, as shown in fig. 6. In other words, virtual addresses VA1, VA2, VA3, and VAn may be mapped to logical block addresses LBA1, LBA2, LBA3, and LBAn, respectively. In this case, the size of the cell area UR may correspond to the size of a data block of the second memory device MEM 2220. In the example of fig. 6, the occupancy status information OCS indicates: the data is stored at logical block addresses LBA1 and LBA2 mapped to virtual addresses VA1 and VA2, corresponding to a first value OC; while data is not stored at the logical block addresses LBA3 and LBA n mapped to the virtual addresses VA3 and VAn, corresponding to the second value UO.

In example embodiments of the inventive concepts, as shown in fig. 7, two virtual addresses may correspond to one logical block address. In other words, virtual addresses VA1 and VA2 may map to logical block address LBA1, virtual addresses VA3 and VA4 may map to logical block address LBA2, virtual addresses VA5 and VA6 may map to logical block address LBA3, and virtual addresses VA-1 and VAn may map to logical block address LBAq. In this case, n corresponds to 2q and the size of the cell area UR may correspond to half the size of the data block of the second memory device MEM 2220. In the example of fig. 7, the occupancy status information OCS indicates: the data is stored at logical block address LBA1, which maps to virtual addresses VA1 and VA2, corresponding to a first value OC; data is not stored at the logical block addresses LBA3 and LBAq mapped to the virtual addresses VA5, VA6, VAn-1, and VAn, corresponding to the second value UO; and the data is stored in a portion of the data block at logical block address LBA2 mapped to virtual addresses VA3 and VA4, corresponding to the first value OC and the second value UO.

The static mapping table SMT may be generated by the host device 100 and may be provided from the host device 100 to the storage device 200. In this way, the host device 100 and the storage device 200 may share the static mapping table SMT to efficiently support byte-wise access and block-wise access between the host device 100 and the storage device 200.

Fig. 8 is a block diagram illustrating a virtual memory controller included in a storage device according to an example embodiment of the inventive concepts.

Referring to FIG. 8, the virtual memory controller 230 may include a mapping manager 232, an internal transfer manager 234, and a recovery manager 236.

The mapping manager 232 may generate a dynamic mapping table DMT comprising a mapping between the real addresses RA 1-RAm of the host private memory area HDMR and the virtual addresses VA 1-VAn of the virtual memory area VMR. As described with reference to fig. 5, the mapping manager 232 may dynamically change the mapping relationship of the dynamic mapping table DMT according to the progress of the access operation of the host device 100 with respect to the virtual memory area VMR.

The internal transfer manager 234 may control data transfer between the first and second memory devices MEM1210 and 2220 based on a dynamic mapping table DMT and a static mapping table SMT including a mapping relationship between virtual addresses VA 1-VAn of the virtual memory region VMR and logical block addresses LBA 1-LBAn of the flush memory region FMR, and occupancy state information OCS indicating whether data is stored at each logical block address mapped to the corresponding virtual address.

The internal data transfer may include a flush operation corresponding to a data transfer from the first memory device MEM1210 to the second memory device MEM2220 and a load operation corresponding to a data transfer from the second memory device MEM2220 to the first memory device MEM1210, as will be described below.

The mapping manager 232 and the internal transfer manager 234 may be implemented as a combination of an Address Translation Unit (ATU), a Memory Management Unit (MMU), a data redirection multiplexer, and the like.

The recovery manager 236 may control operations for supporting non-volatile or persistent support of the persistent memory region PMT that is set for the host-specific memory region HDMR, as will be described with reference to fig. 11. The recovery manager 236 may be implemented as a combination of power down protection (PLP) circuitry and software to control the PLP circuitry as described below. The restore manager 236 may perform a backup operation to store data in the permanent memory area PMR into the flush memory area FMR of the second memory device MEM2220 of the nonvolatile type by using the auxiliary power when an interruption of the input power supplied to the storage apparatus 200 occurs. In addition, the restoration manager 236 may store the static mapping table SMT and the dynamic mapping table DMT in the meta area of the second memory device MEM2220 in the case of power interruption.

After the input power is restored, all data in the virtual memory area VMR may be restored based on the information and data stored in the second memory device MEM 2220.

Fig. 9 is a diagram illustrating an additional write operation (appending write operation) in an electronic system according to an exemplary embodiment of the inventive concept, and fig. 10 is a diagram illustrating a mapping relationship of a dynamic mapping table according to the additional write operation of fig. 9 according to an exemplary embodiment of the inventive concept.

Referring to fig. 9, the host device 100 may perform an additional write operation to store data in the virtual memory area VMR with the continuously increasing virtual address VAD. In fig. 9, "ACO" indicates a writing order.

Fig. 10 shows a change in the mapping relationship of the dynamic mapping table DMT corresponding to the additional write operation of fig. 9. For ease of illustration and description, FIG. 10 illustrates an example where the host-specific memory region HDMR corresponds to eight real addresses RA 1-RA 8, although the inventive concept is not so limited.

At a time point T11, the dynamic mapping table DMT indicates that the first virtual address VA1 and the second virtual address VA2 are mapped to the first real address RA1 and the second real address RA2 in turn, and that the virtual addresses are not yet mapped to the third to eighth real addresses RA3 to RA8 (EMPs).

At a time point T12 after the time point T11, the dynamic mapping table DMT indicates that the first to eighth virtual addresses VA1 to VA8 are sequentially mapped to all of the first to eighth real addresses RA1 to RA 8.

At time T13 after performing a write operation for the ninth virtual address VA9 and the tenth virtual address VA10, the ninth virtual address VA9 and the tenth virtual address VA10 are sequentially mapped to the first real address RA1 and the second real address RA 2.

Thus, the virtual addresses VA 1-VAn can be dynamically mapped to the real addresses RA 1-RAM (where n > m) by a rotating scheme or a polling scheme. With this dynamic mapping, it is possible to provide the host device 100 with the virtual memory area VMR having the second size SZ2 larger than the first size SZ1 by using the host dedicated memory area HDMR having the first size SZ 1.

Fig. 11 is a diagram illustrating a setting of a permanent memory area according to an append write operation of fig. 9 according to an example embodiment of the inventive concept.

Referring to fig. 11, the memory device 200 may set a permanent memory region PMR including a plurality of flush units FU1 and FU2 for a host dedicated memory region HDMR. For ease of illustration and description, FIG. 11 shows an example where the permanent memory region PMR includes two flush units FU1 and FU2, but the inventive concept is not so limited. For example, the persistent memory area PMR may comprise three or more flushing units.

The memory device 200 may perform a flush operation to store data of one flush unit of the plurality of flush units FU1 and FU2 in the second memory device MEM2220 when a write operation for the one flush unit is completed. For example, the internal transfer manager 234 included in the virtual memory controller 230 of fig. 8 may store the data in the one flushing unit in a corresponding portion of the flushing memory region FMR of the first memory device MEM1210 based on the static mapping table SMT and the dynamic mapping table DMT.

Whenever the flush operation for each flush unit is completed, the internal transfer manager 234 may increase the flush position corresponding to the start position of the permanent memory region PMR by the flush size SZF of each of the flush units FU1 and FU2 starting from the start address of the host-dedicated memory region HDMR. Fig. 11 shows the flush position FPOS1 at a time point T21 and the flush position FPOS2 at a time point T22 after the completion of the flush operation for the one flush unit FU 1.

The persistent memory region PMR may be dynamically changed such that the flush unit that completes the flush operation is excluded from the persistent memory region PMR and a new flush unit is included in the persistent memory region PMR.

When the flush location reaches the last address of the host private memory area HDMR, the internal transfer manager 234 may return the flush location to the start address of the host private memory area HDMR.

In this way, old data previously written to the host-specific memory area HDMR may have been stored in the non-volatile second memory device MEM2220 by a flush operation, and the latest data in the host-specific memory area HDMR may be included in the permanent memory area PMR. Even if the power supplied to the storage device 200 is suddenly interrupted or blocked, the restore manager 236, described with reference to fig. 8, may back up the data in the permanent memory region PMR to the flush memory region FMR of the second storage device MEM2220 using auxiliary power.

Thus, the storage device 200 can support non-volatility or permanence of the virtual memory area VMR, so that all data stored in the virtual memory area VMR can be maintained even if the power of the storage device 200 is blocked.

Fig. 12 is a diagram illustrating a setting of a permanent memory area according to an append write operation of fig. 9 according to an example embodiment of the inventive concept.

Referring to fig. 12, the internal transfer manager 234 in the storage device 200 may generate the flush state table FST including the mapping relationship between the plurality of flush units FU1 and FU2 and the real address at which the append write operation has been performed. The internal transfer manager 234 may perform the flush operation based on the flush state table FST.

In fig. 12, "FUX" indicates the index of the flush units FU1 and FU 2; "ACX" indicates a write order index; and "ACAD" indicates a real address corresponding to the writing order index ACX. An "EMP" indicates that the corresponding real address is not mapped to a virtual address.

At point in time T31, the flush state table FST indicates that the first real address RA1, the second real address RA2, and the third real address RA3 are mapped to the first flush unit FU 1. In other words, the flush status table FST at point in time T31 indicates that a write operation has been completed for the first and second real addresses RA1, RA2, and that a write operation is being performed for the third real address RA 3.

Thereafter, the write operation for the third real address RA3 is completed and the write operation for the fourth real address RA4 begins. The internal transfer manager 234 then performs a flush operation for the first real address RA1, the second real address RA2, and the third real address RA3 mapped to the first flush unit FU1, and deletes the mapping relationship of the flush unit FU 1.

As such, the flush state table FST at time point T32 indicates that a write operation is being performed for the fourth real address RA 4; the flush status table FST at point in time T33 indicates that a write operation has been completed for the fourth real address RA4 and the fifth real address RA5 and is being performed for the sixth real address RA 6; and the flush state table FST at point in time T34 indicates that a write operation is being performed for the seventh real address RA 7. Whenever a write operation is completed for each of the flush units FU1 and FU2, a flush operation may be alternately performed for the first flush unit FU1 and the second flush unit FU 2.

Fig. 13 is a diagram illustrating a random write operation in an electronic system according to an exemplary embodiment of the inventive concept, and fig. 14 is a diagram illustrating a mapping relationship of a dynamic mapping table according to the random write operation of fig. 13 according to an exemplary embodiment of the inventive concept.

Referring to fig. 13, the host device 100 may perform a random write operation to store data in the virtual memory area VMR regardless of the order of the virtual addresses VAD. In fig. 13, "ACO" indicates a writing order.

Fig. 14 shows a change in the mapping relationship of the dynamic mapping table DMT corresponding to the random write operation of fig. 13. As shown in fig. 14, the dynamic mapping table DMT may further include write order information ACO indicating the order of real addresses for which random write operations have been performed. For convenience of illustration and description, FIG. 14 shows an example in which the host-specific memory region HDMR corresponds to eight real addresses RA1 RA8, but the inventive concept is not limited thereto.

At a time point T41, the dynamic mapping table DMT indicates that the third virtual address VA3 and the seventh virtual address VA7 are mapped to the first real address RA1 and the second real address RA2 in turn, and that the virtual addresses are not yet mapped to the third to eighth real addresses RA3 to RA8 (EMPs).

At a point of time T42 after the point of time T41, the dynamic mapping table DMT indicates that the second virtual address VA2 and the ninth virtual address VA9 are mapped to the third real address RA3 and the fourth real address RA4 in order, an additional write operation is performed with respect to the third virtual address VA3, thus changing the write order of the first real address RA1 from 1 to 5.

At time T43 after time point T42, the dynamic mapping table DMT indicates that the sixth virtual address VA6 and the fifth virtual address VA5 are mapped to the fifth real address RA5 and the sixth real address RA6 in this order, and an additional write operation is performed for the second virtual address VA2, thus changing the write order of the third real address RA3 from 3 to 8.

At time T44 after time point T43, the dynamic mapping table DMT indicates that the first virtual address VA1 and the fourth virtual address VA4 are mapped to the seventh real address RA7 and the eighth real address RA8 in order.

If a write operation is performed for a new virtual address while mapping all of the real addresses RA 1-RA 8 to the corresponding virtual addresses, the new virtual address may be mapped to the real address corresponding to the oldest write order.

For example, at time T45 after time point T44, the dynamic mapping table DMT indicates that the fourth virtual address VA7 mapped to the second real address RA2 is deleted, and the eighth virtual address VA8 that is performing a write operation may be newly mapped to the second real address RA 2.

Thus, the virtual addresses VA 1-VAn can be dynamically mapped to the real addresses RA 1-RAM (where n > m) by using the write order information ACO. With this dynamic mapping, it is possible to provide the host device 100 with the virtual memory area VMR having the second size SZ2 larger than the first size SZ1 by using the host dedicated memory area HDMR having the first size SZ 1.

Fig. 15 is a diagram illustrating a setting of a permanent memory area according to the random write operation of fig. 13 according to an example embodiment of the inventive concepts.

Referring to FIG. 15, the internal transfer manager 234 in the storage device 200 may generate a flush status table FST including a mapping relationship between the plurality of flush units FUl and FUs 2 and real addresses where random write operations have been performed. The internal transfer manager 234 may perform the flush operation based on the flush state table FST.

In FIG. 15, "FUX" indicates the index of the flush units FU1 and FU 2; "ACX" indicates a write order index; and "ACAD" indicates a real address corresponding to the writing order index ACX. An "EMP" indicates that the corresponding real address is not mapped to a virtual address.

At point in time T51, the flush state table FST indicates that the first real address RA1, the second real address RA2, and the third real address RA3 are mapped to the first flush unit FU 1. In other words, the flush status table FST at point in time T51 indicates that a write operation has been completed for the first and second real addresses RA1, RA2, and that a write operation is being performed for the third real address RA 3.

Thereafter, the write operation for the third real address RA3 is completed and the write operation for the fourth real address RA4 begins. The internal transfer manager 234 then performs a flush operation for the first real address RA1, the second real address RA2, and the third real address RA3 mapped to the first flush unit FU1, and deletes the mapping relationship of the flush unit FUl.

As such, the flush status table FST at time point T52 indicates that a write operation has been completed for the fourth real address RA4 and the first real address RA1 and is being performed for the fifth real address RA 5; the flush status table FST at point in time T53 indicates that a write operation has been completed for the sixth real address RA6 and the third real address RA3 and that a write operation is being performed for the seventh real address RA 7; and the flush state table FST at point in time T54 indicates that the write operation has been completed for the eighth real address RA8 and is being performed for the second real address RA 2. Whenever a write operation is completed for each of the flush units FUl and FU2, a flush operation may be alternately performed for the first flush unit FUl and the second flush unit FU 2.

Fig. 16 is a flowchart illustrating a method of operating an electronic system according to an example embodiment of the inventive concepts.

Referring to fig. 16, the storage device 200 may receive a virtual address VAi as an access address from the host device 100 (S510). The virtual address VAi may be a write address for a write operation or a read address for a read operation.

The virtual memory controller 230 in the storage apparatus 200 may determine whether there is a real address RAj mapped to a virtual address VAi based on the state mapping table DMT (S520).

When there is a real address RAj mapped to a virtual address VAi in the dynamic mapping table DMT (S520: yes), the virtual memory controller 230 may perform an access operation with respect to the real address RAj (S560). When the real address RAj mapped to the virtual address VAi does not exist in the dynamic mapping table DMT (S520: no), the virtual memory controller 230 may assign the real address RAj to the virtual address VAi according to the above-described dynamically set mapping relationship (S530).

The internal transmission manager 234 in the storage device 200 may determine whether the value of the occupancy-state information OCS corresponding to the virtual address VAi is the first value OC or the second value UO based on the occupancy-state information OCS of the static mapping table SMT (S540).

When the corresponding value of the occupancy state information OCS is the first value OC (S540: yes), the internal transfer manager 234 may load data mapped to the logical block address of the virtual address VAi from the flush memory region FMR of the second memory device MEM2220 to the real address RAj of the host dedicated memory region HDMR (S550), and then the virtual memory controller 230 may perform an access operation with respect to the real address RAj (S560). Thus, read operations and/or overwrite operations may be performed while maintaining consistency of the stored data.

When the corresponding value of the occupancy status information OCS is not the first value OC (e.g., the corresponding value of the occupancy status information OCS is the second value UO) (S540: no), the virtual memory controller 230 may perform an access operation with respect to the real address RAj (S560) without performing a load operation.

In this way, when accessing the virtual address VAi, the storage device 200 may determine whether to perform a load operation to store data mapped to a logical block address of the virtual address VAi to the real address RAj mapped to the virtual address VAi based on the occupancy status information OCS.

After the access operation is completed, the storage device 200 may update the occupancy-state information OCS corresponding to the virtual address VAi (S570). When the corresponding value of the occupancy status information OCS is the first value OC, the first value OC may be maintained regardless of a write operation or a read operation. When a write operation has been performed for the virtual address VAi corresponding to the second value UO, the second value UO may be changed to the first value OC for the virtual address VAi after the write operation is completed.

Fig. 17 is a diagram illustrating an example command of a block accessible interface according to an example embodiment of the inventive concepts.

In fig. 17, "b" represents a binary value, and "h" represents a hexadecimal value. "O" means "optional" and "M" means "required". A value 00b of the OPCODE (01:00) may indicate that data transfer between the host apparatus 100 and the storage apparatus 200 does not occur, a value 01b of the OPCODE (01:00) may indicate that data is transferred from the host apparatus 100 to the storage apparatus 200, and a value 10b of the OPCODE (01:00) may indicate that data is transferred from the storage apparatus 200 to the host apparatus 100.

The value 0b of OPCODE (07) may represent the block access command STCMD as described above. The commands FL, WR, RD, WU, CP, WZ, and DM corresponding to the block access command STCMD may be standard commands formulated in the NVMe standard, for example.

Among the illustrated commands, the write zero command WZ may be a command for writing "0" to a write address, for example, a command for deleting data in the write address. By using the write zero command WZ, the host device 100 can delete data at a logical block address where the flush memory region FMR corresponds to a virtual address of the virtual memory region VMR in the second memory device MEM 2220. In this case, the host device 100 may change the value of the occupancy status information OCS corresponding to the virtual address from the first value OC to the second value UO and notify the storage device 200 of the change of the occupancy status information OCS.

Fig. 18 is a diagram illustrating address mapping in an electronic system according to an example embodiment of the inventive concepts.

Referring to fig. 18, the host private memory area HDMR may include a plurality of sub-host private memory areas HDMR1 and HDMR2, and the virtual memory area VMR may include a plurality of sub-virtual memory areas VMR1 and VMR2 mapped to the plurality of sub-host private memory areas HDMR1 and HDMR2, respectively. For convenience of illustration and description, fig. 18 shows an example in which each of the host private memory region HDMR and the virtual memory region VMR is divided into two sub-regions, but the inventive concept is not limited thereto.

The storage apparatus 200 can uniquely provide each of the plurality of sub virtual memory regions VMR1 and VMR2 to each of the plurality of applications APP1 and APP2 of the host apparatus 100. The static mapping table SMT, the dynamic mapping table DMT and the flush state table FST as described above may be generated and managed separately for each of the applications APP1 and APP 2. The host device 100 may manage information, or the storage device 200 may manage information by using a function such as Namespace of NVMe standard. Further, the storage apparatus 200 may protect a sub virtual memory area of each application using a Memory Protection Unit (MPU) so that one application cannot invade a sub virtual memory area of another application.

Fig. 19 is a block diagram illustrating a storage device according to an example embodiment of the inventive concepts.

Referring to fig. 19, a memory device 500 may include a power down protection circuit PLP 510, an auxiliary power device APWM 520, an internal circuit INT 530, and a power rail 400.

The power down protection circuit 510 may receive input power Pin via a first node N1. The power down protection circuit 510 may supply the charging power Pch to the auxiliary power supply apparatus 520 via the second node N2, or receive the auxiliary power Pcap from the auxiliary power supply apparatus 520. Power fail protection circuit 510 may provide at least one of input power Pin and auxiliary power Pcap or a combination of input power Pin and auxiliary power Pcap as internal power Pint to internal circuitry 530 via third node N3. Third node N3 is a node on power rail 400 for supplying power to internal circuitry 530.

The auxiliary power supply device 520 may include a capacitor module or an auxiliary battery. The internal circuit 530 may have various configurations according to the type of the memory device 500. For example, the storage device 500 may be a Solid State Drive (SSD), an embedded multimedia card (eMMC), a Universal Flash (UFS) device, or the like, and the internal circuit 530 may include a first storage device of a volatile type, a second storage device of a non-volatile type, and circuits such as a virtual memory controller and a block controller for controlling the first storage device and the second storage device.

The power down protection circuit 510 may generate a status signal STA indicating the power capacity of the auxiliary power device 520 and provide the status signal STA to the internal circuitry 530 of the storage device 500. The status signal STA may be a multi-bit signal indicating the power supply capacity. The internal circuit 530 may control the operation of the memory device 500 based on the state signal STA. For example, the internal circuitry 530 may adjust the flush size SZF based on the status signal STA.

Fig. 20 is a block diagram illustrating a power down protection (PLP) circuit included in the electronic device of fig. 19 according to an example embodiment of the inventive concepts.

Referring to fig. 20, the power down protection circuit 510 may include a controller 511, a first monitor 512, a second monitor 513, a charger 514, and a power switch 515.

Controller 511 may control the overall operation of power down protection circuit 510. For example, the controller 511 may generate the status signal STA as described above.

The first monitor 512 may monitor the input power Pin provided through the first node N1 to generate the first detection signal DET 1. For example, the first monitor 512 may monitor the input power Pin based on the voltage at the first node N1. If the voltage at the first node N1 becomes lower than the reference level, the first monitor 120 may determine that an interrupt has occurred in the input power Pin and activate the first detection signal DET1 to notify the controller 511 of the interrupt.

The second monitor 513 may monitor the state of the secondary power supply device 520 to generate the second detection signal DET2, and the controller 511 may generate the state signal STA based on the second detection signal DET2 of the second monitor 513. For example, the second monitor 130 may monitor the state of the auxiliary power supply device 520 based on the voltage and/or current at the second node N2.

The charger 514 may provide charging power Pch for charging the auxiliary power supply device 520 based on the input power Pin. The timing of the charging operation may be controlled by a control signal from the controller 511. The charging operation may be performed periodically or non-periodically.

The power switch 515 may electrically connect the first node N1 and/or the second node N2 to the third node N3 in response to a control signal from the controller 511. When the first node N1 is electrically connected to the third node N3, the input power Pin may be provided to the internal circuitry 530 as internal power Pint via the power rail 400. When the second node N2 is electrically connected to the third node N3, auxiliary power Pcap may be provided to the internal circuitry 530 as internal power Pint via power rail 400.

In some cases, the first node N1 and the second node N2 may be electrically connected to the third node N3 at the same time, and thus, the sum of the input power Pin and the auxiliary power Pcap may be supplied as the internal power Pint to the internal circuit 530.

Fig. 21 is a diagram illustrating determining a flush size in an electronic system according to an example embodiment of the inventive concept.

The upper part of fig. 21 represents the flushing operation FOP when the state signal STA indicates that the power capacity of the auxiliary power device 520 is relatively low, and the lower part of fig. 21 represents the flushing operation FOP when the state signal STA indicates that the power capacity of the auxiliary power device 520 is relatively high. As shown in fig. 21, the above-described flushing size SZF (e.g., the data amount per flushing operation) may be controlled based on the auxiliary power Pcap.

When the auxiliary power Pcap is relatively small, the flush size SZF1 of the flush unit FU in the host-dedicated memory area HDMR may be set to be relatively small. In contrast, when the auxiliary power Pcap is relatively high, the flush size SZF2 of the flush unit FU in the host-dedicated memory area HDMR may be set to be relatively large.

In this way, as the auxiliary power Pcap or the power supply capacity of the auxiliary power supply apparatus 520 decreases, the flushing operation can be performed more frequently. Although the performance of the storage apparatus 200 may deteriorate in the case where the flush operation is frequently performed, the flush operation may be completed with a lower auxiliary power Pcap to ensure non-volatility or permanence of the virtual memory region VMR.

Fig. 22 is a block diagram illustrating an electronic system according to an example embodiment of the inventive concepts.

Referring to fig. 22, a system 1001 includes a host device 2000 and a storage device 3000. For example, the storage device 3000 may be an embedded multimedia card (eMMC), a Solid State Drive (SSD), or the like.

The host device 2000 may be configured to control data processing operations, such as data read operations and data write operations of the storage device 3000. The host device 2000 may be a data processing device such as a Central Processing Unit (CPU), a processor, a microprocessor, or an application processor that may process data. The host device 2000 and the storage device 3000 may be embedded or implemented in an electronic device. The host device 2000 and the storage device 3000 may be connected to each other via a bus 10.

The host device 2000 may include a processor (CPU)2100, a memory (MEM)2200, and a Host Controller Interface (HCI)2300, which are connected to each other via a bus 20. An Operating System (OS) and/or host Firmware (FW)2110 may be executed by the processor 2100. The processor 2100 may include hardware and/or software for controlling: generation of commands, analysis of responses to commands, storage of data in storage device 3000, and/or data processing. Processor 2100 may execute the OS and host firmware 2110 to perform these operations.

Host controller interface 2300 may interact with storage device 3000. For example, the host controller interface 2300 is configured to issue commands to the storage device 3000, receive responses to the commands from the storage device 3000, transmit write data to the storage device 3000, and receive read data from the storage device 3000.

The memory device 3000 may include a plurality of nonvolatile memory devices (NVMs) 3100, a memory controller 3200, and an auxiliary power device APWM 3300.

The non-volatile memory device 3100 may optionally be supplied with an external high voltage VPP. The non-volatile memory device 3100 may be implemented as a flash memory, a Ferroelectric Random Access Memory (FRAM), a phase change random access memory (PRAM), a Magnetic Random Access Memory (MRAM), or the like.

The memory controller 3200 may be connected to the nonvolatile memory device 3100 through a plurality of channels CH1 to CHi. The memory controller 3200 may include one or more processors 3210, power down protection circuitry 3220, host interface circuitry 3230, a non-volatile memory device MEM 3240, a non-volatile memory interface circuitry 3250, a virtual memory controller VMCON 3260, and a block controller BLCON 3270.

The power down protection circuit 3220 may monitor the state of the auxiliary power supply device 3300 and generate a state signal STA based on the monitoring result to control the operation of the storage device 3000.

The processor 3210 is configured to control the overall operation of the storage controller 3200. For example, the processor 3210 may operate firmware 3212 including a Flash Translation Layer (FTL) or the like.

The host interface circuit 3230 may provide an interface with external devices, such as the host device 2000. The non-volatile memory interface circuit 3250 may provide an interface with the non-volatile memory device 3100.

The volatile memory device 3240 may correspond to the first memory device MEM1210 described above and the nonvolatile memory device 3100 may correspond to the second memory device MEM2220 described above.

The virtual memory controller 3260 and the block controller 3270 may be substantially the same as described above, and thus, a repetitive description will be omitted.

Fig. 23 is a block diagram illustrating a mobile device according to an example embodiment of the inventive concepts.

Referring to fig. 23, a mobile device 4000 may include at least one application processor 4100, a communication module 4200, a display/touch module 4300, a storage device 4400, and a buffer RAM 4500.

The application processor 4100 controls the operation of the mobile device 4000. The application processor 4100 may execute at least one application to provide internet browsing, games, video, and the like. The communication module 4200 is implemented to perform wireless or wired communication with an external device. The display/touch module 4300 is implemented to display data processed by the application processor 4100 and/or receive data through the touch panel. The storage device 4400 is implemented to store user data.

The storage device 4400 may be an embedded multimedia card (eMMC), a Solid State Drive (SSD), a universal flash memory (UFS) device, or the like. The storage device 4400 may provide the virtual memory region VMR to the application processor 4100 as described above according to example embodiments of the inventive concepts.

Buffer RAM4500 temporarily stores data used to process operations of mobile device 4000. For example, buffer RAM4500 can be double data Rate synchronous dynamic random Access memory (DDR SDRAM), Low Power DDR SDRAM (LPDDRSDRAM), graphics DDR SDRAM (GDDR SDRAM), Rambus DRAM (RDRAM), and so forth.

As described above, the storage device, the electronic system, and the method according to example embodiments of the inventive concepts may provide a virtual memory region larger than a host-dedicated memory region corresponding to real memory resources by dynamically changing a mapping relationship between the host-dedicated memory region and the virtual memory region to reduce the size of the storage device and the electronic system and enhance the performance thereof. Further, the storage device, the electronic system, and the method according to example embodiments of the inventive concept may support non-volatility of a virtual memory area through a flush operation and effectively support byte-wise access and block-wise access between a host device and the storage device, thereby enhancing performance of the storage device and the electronic system.

The inventive concept can be applied to any electronic device and system. For example, the inventive concept may be applied to various systems such as memory cards, Solid State Drives (SSDs), embedded multimedia cards (emmcs), mobile phones, smart phones, Personal Digital Assistants (PDAs), Portable Multimedia Players (PMPs), digital cameras, video recorders, Personal Computers (PCs), servo computers, workstations, laptop computers, digital TVs, set top boxes, portable game machines, navigation systems, wearable devices, internet of things (IoT) devices, internet of everything (IoE) devices, electronic books, Virtual Reality (VR) devices, Augmented Reality (AR) devices, and the like.

While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.