Data storage device and operation method of data storage device
阅读说明:本技术 数据存储装置及数据存储装置的操作方法 (Data storage device and operation method of data storage device ) 是由 金真洙 姜玟求 于 2019-07-31 设计创作,主要内容包括:本发明提供了一种数据存储装置。该数据存储装置可包括:非易失性存储器装置;以及控制器,控制非易失性存储器装置的读取操作,其中控制器包括:存储器,存储工作负载模式信息;以及处理器,基于工作负载模式信息检查第一时段中的工作负载模式,并且根据第一时段中的工作负载模式来判定在第一时段之后的第二时段中待执行的读取模式。(The invention provides a data storage device. The data storage device may include: a non-volatile memory device; and a controller controlling a read operation of the nonvolatile memory device, wherein the controller includes: a memory to store workload pattern information; and a processor checking a workload pattern in the first period based on the workload pattern information, and determining a read mode to be performed in a second period subsequent to the first period according to the workload pattern in the first period.)
1. A data storage device comprising:
a non-volatile memory device; and
a controller to control a read operation of the non-volatile memory device,
wherein the controller comprises:
a memory to store workload pattern information; and
a processor that checks a workload pattern in a first period based on the workload pattern information, and determines a read pattern to be performed in a second period subsequent to the first period according to the workload pattern in the first period.
2. The data storage device of claim 1, wherein the workload pattern in the first period of time includes information indicating whether commands provided to the non-volatile memory device in the first period of time are of the same type or different types, information indicating whether the size of a block of data provided to the non-volatile memory device in the first period of time is the same or different, and information about the number of commands queued in a command queue.
3. The data storage device of claim 1, wherein the read mode comprises a cache read mode and a normal read mode.
4. The data storage device of claim 3, wherein the workload pattern information comprises:
a first value indicating whether all commands provided to the non-volatile memory device in the first period of time are read commands;
a second value indicating whether a block of data provided to the non-volatile memory device in the first period of time is one size; and
a third value indicating whether a number of commands queued in the command queue in the first period of time is greater than or equal to a threshold.
5. The data storage device of claim 4, wherein the processor determines that the cache read mode is to be performed in the second period of time when all of the first value, the second value, and the third value of the workload pattern information are in a set state.
6. The data storage device of claim 4, wherein the processor determines that the normal read mode is to be performed in the second period of time when one or more of the first value, the second value, and the third value of the workload pattern information is in a reset state.
7. The data storage device of claim 1,
wherein a flash translation layer, FTL, is loaded into the memory, an
Wherein the FTL includes a workload detection module.
8. The data storage device of claim 7, wherein at the end of the first period, the processor drives the workload detection module to detect a workload pattern in the first period and update the workload pattern information based on the detected workload pattern.
9. A method of operating a data storage device, the data storage device comprising a non-volatile memory device and a controller that controls read operations of the non-volatile memory device and that includes a memory for storing workload pattern information, the method of operation comprising:
checking a workload pattern in a first period based on the workload pattern information, an
Determining a read mode to be performed in a second period after the first period according to a workload pattern in the first period.
10. The operating method of claim 9, wherein the workload pattern in the first period of time includes information indicating whether commands provided to the non-volatile memory device in the first period of time are of the same type or different types, information indicating whether the size of a block of data provided to the non-volatile memory device in the first period of time is the same or different, and information about the number of commands queued in a command queue.
11. The method of operation of claim 9, wherein the workload pattern information comprises:
a first value indicating whether all commands provided to the non-volatile memory device in the first period of time are read commands;
a second value indicating whether a block of data provided to the non-volatile memory device in the first period of time is one size; and
a third value indicating whether a number of commands queued in the command queue in the first period of time is greater than or equal to a threshold.
12. The operation method according to claim 11, wherein determining the read mode to be performed in the second period of time includes:
determining whether the first value, the second value, and the third value of the workload pattern information are all in a set state; and
determining to execute a cache read mode as the read mode when it is determined that the first value, the second value, and the third value of the workload pattern information are all in the set state.
13. The operation method according to claim 11, wherein determining the read mode to be performed in the second period of time includes: determining to execute a normal read mode as the read mode when one or more of the first value, the second value, and the third value of the workload pattern information are in a reset state.
14. The method of operation of claim 9, further comprising:
detecting a workload pattern in the first period at a first point in time at which the first period ends; and
updating the workload pattern information based on the detected workload pattern.
15. The method of operation of claim 14, further comprising:
detecting a workload pattern in the second period at a second point in time at which the second period ends; and
updating the workload pattern information based on the detected workload pattern.
16. A data storage device comprising:
a non-volatile memory device; and
a controller that controls the non-volatile memory device to perform a cache read operation during a current period when the non-volatile memory device performs a set number of read operations on only a single size block of data during a previous period.
Technical Field
Various embodiments of the present disclosure relate generally to a semiconductor device, and more particularly, to a data storage device and an operating method of the data storage device.
Background
More recently, computing environment paradigms have turned into pervasive computing where computer systems can be used anytime and anywhere. Therefore, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has been rapidly increasing. Such portable electronic devices typically use data storage devices that utilize memory devices. The data storage device is used for storing data used in the portable electronic device.
Since the data storage device using the memory device has no mechanical driver, the data storage device has excellent stability and durability, high information access speed, and low power consumption. Data storage devices having these advantages include Universal Serial Bus (USB) memory devices, memory cards having various interfaces, universal flash memory (UFS) devices, and Solid State Drives (SSDs).
Disclosure of Invention
Various embodiments relate to a data storage device and an operating method of the data storage device capable of selectively performing a cache read operation and a normal read operation according to a workload.
In an embodiment, a data storage device may include: a non-volatile memory device; and a controller configured to control a read operation of the nonvolatile memory device, wherein the controller includes: a memory configured to store workload pattern information; and a processor configured to check a workload pattern in a first period based on the workload pattern information, and determine a read mode to be performed in a second period subsequent to the first period according to the workload pattern in the first period.
In an embodiment, a method of operating a data storage device may include: the method includes checking a workload pattern in a first period based on the workload pattern information, and determining a read pattern to be performed in a second period subsequent to the first period according to the workload pattern in the first period.
In an embodiment, a data storage device may include a non-volatile memory device; and a controller configured to control the non-volatile memory device to perform a cache read operation during a current period when the non-volatile memory device performs a set number of read operations on only a single-sized data block during a previous period.
Drawings
Fig. 1 illustrates a configuration of a data storage device according to an embodiment.
Fig. 2 shows a configuration of a memory such as that of fig. 1.
Fig. 3 illustrates a Flash Translation Layer (FTL).
Fig. 4 shows a period set to detect a workload pattern.
Fig. 5 illustrates workload pattern information.
Fig. 6A shows a process of determining which read operation is performed in a subsequent period according to the workload pattern.
Fig. 6B and 6C illustrate a normal read operation and a cache read operation, respectively.
FIG. 7 illustrates a method of operation of a data storage device according to an embodiment.
FIG. 8 illustrates a data processing system including a Solid State Drive (SSD) according to an embodiment.
Fig. 9 shows a controller such as that shown in fig. 8.
FIG. 10 illustrates a data processing system including a data storage device, according to an embodiment.
FIG. 11 illustrates a data processing system including a data storage device, according to an embodiment.
FIG. 12 illustrates a network system including a data storage device, according to an embodiment.
Fig. 13 is a diagram illustrating a nonvolatile memory device included in a data storage apparatus according to an embodiment.
Detailed Description
A data storage device and an operation method of the data storage device according to the present disclosure are described below by various embodiments with reference to the accompanying drawings. Throughout the specification, references to "an embodiment" or the like are not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Therefore, a first element described below may also be referred to as a second element or a third element without departing from the spirit and scope of the present invention.
It will be further understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Communication between two elements, whether directly or indirectly connected/coupled, may be wired or wireless unless stated otherwise or the context dictates otherwise.
As used herein, the singular form may also include the plural form and vice versa, unless the context clearly dictates otherwise. The articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or the context clearly dictates otherwise.
It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements, and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1 shows a configuration of a data storage device 10 according to an embodiment.
Referring to fig. 1, a data storage device 10 may store data accessed by a host device 20 such as: a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV or a car infotainment system. The data storage device 10 may also be referred to as a memory system.
The data storage device 10 may be configured as any of various storage devices according to an interface protocol coupled to the host device 20. For example, the data storage device 10 may be configured as any one of the following: a Solid State Drive (SSD), a multimedia card (MMC) such as eMMC, RS-MMC or micro-MMC, a Secure Digital (SD) card such as mini SD or micro SD, a Universal Serial Bus (USB) memory device, a universal flash memory (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type memory device, a Peripheral Component Interconnect (PCI) card type memory device, a PCI express (PCI-E) card type memory device, a Compact Flash (CF) card, a smart media card, and a memory stick.
Data storage device 10 may be manufactured as any of a variety of types of packages, such as: package On Package (POP), System In Package (SIP), System On Chip (SOC), multi-chip package (MCP), Chip On Board (COB), wafer-level manufacturing package (WFP), and wafer-level package on package (WSP).
The data storage device 10 may include a
The
Fig. 1 shows that the data storage device 10 includes one
The
For example, each of the memory cells of the memory cell array may be configured as a single-layer cell (SLC) storing 1-bit data or a multi-layer cell (MLC) storing 2-bit or more data. MLCs may store 2-bit data, 3-bit data, 4-bit data, or more. In general, a memory cell storing 2-bit data may be referred to as an MLC, a memory cell storing 3-bit data may be referred to as a Triple Layer Cell (TLC), and a memory cell storing 4-bit data may be referred to as a Quadruple Layer Cell (QLC). However, in this specification, memory cells storing 2-bit data to 4-bit data may be collectively referred to as MLCs for convenience.
The
The
The host interface 210 may interface the host device 20 and the data storage device 10 in response to a protocol of the host device 20. For example, the host interface 210 may communicate with the host device 20 via any one of the following protocols: USB (universal serial bus), UFS (universal flash), MMC (multimedia card), PATA (parallel advanced technology attachment), SATA (serial advanced technology attachment), SCSI (small computer system interface), SAS (serial SCSI), PCI (peripheral component interconnect), and PCI-e (PCI express).
Processor 220 may include a Micro Control Unit (MCU) and/or a Central Processing Unit (CPU). The processor 220 may process a request transmitted from the host device 20. To process requests transmitted from the host device 20, the processor 220 may drive code-based instructions or algorithms, i.e., firmware, loaded to the
The processor 220 may generate a control signal for controlling the operation of the
The
The memory interface 240 may control the
Fig. 2 illustrates the
Referring to fig. 2, the
The
When the
The FTL stored in the first region R1 of the
Fig. 3 illustrates an FTL according to an embodiment.
Referring to fig. 3, the FTL may include a workload detection module (WLDM)310, etc., but is not particularly limited thereto. Although fig. 3 only shows the workload pattern information WLPI, it is apparent to those skilled in the art that the FTL further may include various functional modules such as a garbage collection module, a wear leveling module, a bad block management module, an address mapping module, a write module, a read module, and a mapping module.
The WLDM310 may detect the workload pattern over a set period of time. The WLDM310 may update the workload pattern information WLPI stored in the
Fig. 4 shows a period set to detect a workload pattern, and fig. 5 shows workload pattern information WLPI.
By way of example, fig. 4 shows only the first to third periods. However, the number of periods is not particularly limited to three, but may increase as time elapses. In fig. 4, "t" may indicate a current time point, and "t-1" may indicate a time point before the current time point. Further, "t + 1" may indicate a time point after the current time point, and "t + 2" may indicate a time point after "t + 1". The time between adjacent time points may be fixed. For example, adjacent time points may be separated by a set time. However, the present invention is not limited to this configuration. In another embodiment, the time intervals between adjacent time points may be different.
At time point "t", the processor 220 may drive the WLDM310 to detect a workload pattern for a first period of time from time point "t-1" to time point "t". For example, the workload patterns may include various pieces of information such as: the type of command provided to the
For example, the WLDM310 may detect whether the commands provided to the
When all the commands provided to the
The workload pattern information WLPI may be used as reference information for determining whether it is more efficient to perform a cache read operation or to perform a normal read operation in a subsequent period.
Fig. 6A shows a process of deciding which read operation is performed in a subsequent period according to a workload pattern in an existing period, fig. 6B shows a normal read operation and fig. 6C shows a cache read operation.
As shown in fig. 6A, when the first field (read-only CMD), the second field (one type of block size), and the third field (queue depth above the threshold) of the workload pattern information WLPI are all set to the "set (1)" state, the WLDM310 may determine that it is efficient to perform the cache read operation in the subsequent period. When all fields of the workload pattern information WLPI are set to the "set (1)" state, it may indicate that a read operation is performed only on a data block of the same size during a previous period (i.e., a first period). In this case, the WLDM310 may determine that it is highly likely that only read operations for data blocks of the same size will be performed in subsequent periods.
When a read operation for a data block of the same size is performed in the current period, it is more efficient to perform a cache read operation in a subsequent period than to perform an ordinary read operation. Accordingly, the WLDM310 may decide to perform a cache read operation on a read request received from the host device 20 in a subsequent period. Further, the WLDM310 may provide a read control signal corresponding to the determination result, i.e., a cache read control signal, to the processor 220, and the processor 220 may control the
When one or more of the first field (read-only CMD), the second field (one type of block size), and the third field (queue depth above a threshold) of the workload mode information WLPI are set to a "reset (0)" state, the WLDM310 may determine that it is efficient to perform a normal read operation in a subsequent period. When the "read only CMD" of the workload mode information WLPI is set to the "reset (0)" state, it may indicate that both the read operation and the write operation are performed during the previous period, i.e., the second period; when "one type of block size" is set to the "reset (0)" state, it may indicate that an operation is performed on a data block of a different size, and when "queue depth above threshold" is set to the "reset (0)" state, it may indicate that a smaller number of requests are received from the host device 20. Depending on which field(s) is/are set to the "reset (0)" state, the WLDM310 may determine that read and write operations will be performed, that operations will be performed on different sized blocks of data, or that a smaller number of requests will be received from the host device 20 in a subsequent period.
In this case, since it is more efficient to perform the normal read operation than to perform the cache read operation, the WLDM310 may decide to perform the normal read operation on the read request received from the host device 20 in a subsequent period. The WLDM310 may provide the processor 220 with a read control signal corresponding to the determination result, i.e., a normal read control signal, and the processor 220 may control the
Referring to fig. 6B, a normal read operation will be described as follows when the
Referring to fig. 6C, a cache read operation will be described as follows when the
Then, when the
Fig. 6C illustrates that when the processing of the first cache read command CMD _ CR1 is completed, the
That is, the cache read operation may include a series of processes of reading data from the memory cell array in response to one read command, and simultaneously outputting data corresponding to a previous read command to the controller. Thus, a cache read operation may exhibit higher read performance than a normal read operation.
However, since the cache read operation stores the currently read data in the cache buffer while outputting the previous data cached in the cache buffer to the controller, when the next command provided from the controller is not a read command, it is necessary to first provide a separate command for outputting the data stored in the cache buffer to the nonvolatile memory device and then provide the next command to the nonvolatile memory device. Thus, cache read operations may be more efficient when read commands are provided continuously, and may be less efficient than normal read operations when read and write commands are mixed and provided.
In an embodiment, which of a plurality of types of read operations is performed may be decided according to a workload pattern in a subsequent period, which is estimated based on the workload pattern in a previous period, which may improve read performance.
FIG. 7 illustrates a method of operation of a data storage device according to an embodiment. In describing this method, reference may be made to one or more of fig. 1-6 in addition to fig. 7.
In step S701, the processor 220 of the
Although not shown in fig. 7, the processor 220 may drive the WLDM310 at a time point "t" at which the first period ends, so as to detect a workload pattern in the first period from the time point "t-1" to the time point "t". Since the workload patterns and the detection methods have been described above, further description thereof is omitted here. The WLDM310 may update the values set for the various fields of the workload pattern information WLPI based on the detected workload patterns in the previous period.
In step S703, the WLDM310 may determine whether the cache read condition is satisfied based on the values set for the respective fields of the workload pattern information WLPI. For example, WLDM310 may determine that the cache read condition is satisfied when the first field (read-only CMD), the second field (one type of block size), and the third field (queue depth above a threshold) of workload mode information WLPI are all set to a "set (1)" state. When the cache read condition is satisfied (i.e., yes in step S703), the process may proceed to step S705. On the other hand, when the cache read condition is not satisfied (i.e., no in step S703), the process may proceed to step S707.
In step S705, the WLDM310 may provide a read control signal to the processor 220 indicating that the cache read condition is satisfied, and the processor 220 may transmit a cache read command to the
In step S707, the WLDM310 may provide the processor 220 with a read control signal indicating that the cache read condition is not satisfied, and the processor 220 may check whether the last read command transmitted in the previous period is a cache read command. If so (i.e., YES in step S707), the process may proceed to step S709. On the other hand, when the last read command transmitted in the previous period is not a cache read command (i.e., no in step S707), the process may proceed to step S711.
In step S709, the processor 220 may control the
In step S711, the processor 220 may transmit a normal read command to the
After steps S705 and S711, step S701 may be performed again.
According to an embodiment of the present invention, the data storage device is configured to detect a workload pattern during a set period, and selectively perform one of a cache read operation and a normal read operation based on the detected workload pattern.
That is, the data storage device may perform a cache read operation when the cache read operation has an advantage, and perform a normal read operation when the normal read operation has an advantage. Accordingly, the performance of the data storage device can be maximized.
FIG. 8 illustrates a data processing system including a Solid State Drive (SSD) according to an embodiment. Referring to fig. 8, a
SSD2200 may include
The
The
The
Fig. 9 illustrates the
The host interface 2211 may perform interfacing between the
The control component 2212 may analyze and process the signal SGL input from the
The ECC component 2214 may generate parity data for data to be transferred to the
The memory interface 2215 may provide control signals such as commands and addresses to the
FIG. 10 illustrates a data processing system including a data storage device, according to an embodiment. Referring to fig. 10,
The
The
The
The
The
FIG. 11 illustrates a data processing system including a data storage device, according to an embodiment. Referring to FIG. 11, data processing system 4000 may include a host device 4100 and a data storage device 4200.
The host device 4100 may be configured in a board form such as a PCB. Although not shown in fig. 11, the host device 4100 may include internal functional blocks configured to perform the functions of the host device 4100.
The data storage device 4200 may be configured in the form of a surface mount package. The data storage device 4200 may be mounted on the host device 4100 by solder balls 4250. Data storage device 4200 may include a controller 4210, a cache memory device 4220, and a non-volatile memory device 4230.
The controller 4210 may control the overall operation of the data storage device 4200. The controller 4210 may be configured to have the same configuration as the
Buffer memory device 4220 may temporarily store data to be stored in non-volatile memory device 4230. Buffer memory device 4220 may temporarily store data read from non-volatile memory device 4230. The data temporarily stored in the buffer memory device 4220 may be transferred to the host apparatus 4100 or the nonvolatile memory device 4230 by the control of the controller 4210.
The nonvolatile memory device 4230 may be used as a storage medium of the data storage apparatus 4200.
Fig. 12 illustrates a
The
The
Fig. 13 is a diagram illustrating a nonvolatile memory device included in a data storage apparatus according to an embodiment. Referring to fig. 13, the
The
The data read/
The
The
The
While various embodiments have been illustrated and described, it will be appreciated by those skilled in the art in light of the present disclosure that various modifications may be made to any of the disclosed embodiments. Accordingly, it is intended that the invention cover all such modifications as fall within the scope of the claims and their equivalents.
- 上一篇:一种医用注射器针头装配设备
- 下一篇:一种存储访问控制方法和装置