阅读说明：本技术 电子器件
(Electronic device
) 是由 阿布舍克·班纳吉
P·范米尔贝克
皮特·莫昂 于 2019-07-17 设计创作，主要内容包括：本发明公开了一种电子器件。该电子器件可以包括沟道层,该沟道层包含Al<Sub>z</Sub>Ga<Sub>(1-z)</Sub>N,其中0≤z≤0.1；栅极介电层；以及高电子迁移率晶体管(HEMT)的栅极电极。栅极介电层可以设置在沟道层与栅极电极之间。所述栅极电极包括接触所述栅极介电层的栅极电极膜,其中所述栅极电极膜可以包含某种材料,其中所述材料具有的电子亲和能与带隙能量的总和为至少6eV。在一些实施方案中,该材料可以包括p型半导体材料。用于所述栅极电极膜的所述特定材料可以被选择来实现增强型HEMT的所期望的阈值电压。在另一个实施方案中,阻挡层的一部分可以在栅极结构下方保持完整。这样的配置可以改善载流子迁移率并减少Rdson。(The invention discloses an electronic device. The electronic device may include a channel layer including Al z Ga (1‑z) N, wherein z is more than or equal to 0 and less than or equal to 0.1; a gate dielectric layer; and a gate electrode of a High Electron Mobility Transistor (HEMT). A gate dielectric layer may be disposed between the channel layer and the gate electrode. The gate electrode comprises a gate electrode film contacting the gate dielectric layer, wherein the gate electrode film may comprise a material having an electron affinity withThe sum of the band gap energies is at least 6 eV. In some embodiments, the material may include a p-type semiconductor material. The particular material used for the gate electrode film can be selected to achieve a desired threshold voltage for an enhancement mode HEMT. In another embodiment, a portion of the barrier layer may remain intact under the gate structure. Such a configuration may improve carrier mobility and reduce Rdson.)
1. An electronic device, comprising:
a channel layer comprising AlzGa(1-z)N, wherein z is more than or equal to 0 and less than or equal to 0.1;
a gate dielectric layer; and
a gate electrode of a high electron mobility transistor, wherein the gate dielectric layer is disposed between the channel layer and the gate electrode, and the gate electrode comprises a first gate electrode film contacting the gate dielectric layer, wherein the first gate electrode film comprises a material, wherein the material has a sum of an electron affinity and a band gap energy of at least 6 eV.
2. The electronic device of claim 1, wherein the gate dielectric layer comprises:
a first dielectric film comprising a first dielectric material; and
a second dielectric film covering the first dielectric film and including a second dielectric material,
wherein the content of the first and second substances,
the second dielectric material has a higher energy conduction band and valence band than the semiconductor material of the channel layer and the first dielectric material, and
the second dielectric material has a larger bandgap energy than the semiconductor material and the first dielectric material of the channel layer.
3. The electronic device of claim 1, wherein the material of the first gate electrode film comprises a polycrystalline p-type semiconductor material having at least 1 x 1017Dopant concentration of one atom per cubic centimeter.
4. The electronic device according to claim 3, wherein the gate electrode further comprises a second gate electrode film covering the first gate electrode film, wherein an ohmic contact is formed at an interface between the first gate electrode film and the second gate electrode film.
5. The electronic device according to claim 3, wherein the gate electrode further comprises a second gate electrode film covering the first gate electrode film, wherein the second gate electrode film is a p-type metal-containing film.
6. The electronic device of claim 3, wherein the gate electrode further comprises a second gate electrode film overlying the first gate electrode film, wherein the second gate electrode film comprises a metal having a work function in a range of 4.6eV to 6.0 eV.
7. An electronic device, comprising:
a channel layer comprising AlzGa(1-z)N, wherein z is more than or equal to 0 and less than or equal to 0.1; and
a gate electrode of the high electron mobility transistor, wherein,
a gate electrode layer overlies the channel layer,
the gate electrode includes a first gate electrode film and a second gate electrode film,
within the gate electrode, the first gate electrode film is closer to the channel layer than any other of the gate electrodes, and the second gate electrode film is farther from the channel layer than any other of the gate electrodes, and
the first gate electrode film comprises a first material, wherein the first material has a sum of an electron affinity and a band gap energy of at least 6 eV.
8. The electronic device of claim 7, wherein the gate electrode further comprises a third gate electrode film disposed between the first gate electrode film and the second gate electrode film, the third gate electrode film having a work function that is the same as or less than the work function of the first gate electrode film and the same as or greater than the work function of the second gate electrode film.
9. The electronic device of claim 8, further comprising a barrier layer overlying the channel layer, wherein,
the first gate electrode film contacts the barrier layer and comprises single crystal p-type GaN,
the third gate electrode film comprises polycrystalline p-type GaN, and
the second gate electrode film includes a metal-containing film, wherein,
an ohmic contact is formed at an interface between the second gate electrode film and the third gate electrode film.
10. An electronic device comprising a high electron mobility transistor, the electronic device comprising:
a channel layer comprising GaN;
a barrier layer overlying the channel layer and comprising AlxInyGa(1-x-y)N, wherein, 0<x is less than or equal to 1, and y is more than or equal to 0 and less than or equal to 0.3;
a gate dielectric layer extending partially but not completely through the barrier layer, wherein,
the gate dielectric layer includes a first dielectric film and a second dielectric film overlying the first dielectric film,
the first dielectric film comprises a first dielectric material,
the second dielectric film comprises a second dielectric material different from the first dielectric material,
the second dielectric material has a higher energy conduction band and valence band than GaN and the first dielectric material, and
the second dielectric material has a larger band gap energy than the semiconductor material of the channel layer and the first dielectric material,
a gate electrode, wherein the gate dielectric layer is disposed between the channel layer and the gate electrode, and the gate electrode comprises:
a polycrystalline p-type semiconductor film in contact with the gate dielectric layer; and
a metal-containing film covering and in contact with the polycrystalline p-type semiconductor film, wherein,
an ohmic contact is formed at an interface between the polycrystalline p-type semiconductor film and the metal-containing film, and
the metal-containing film comprises a metal having a work function greater than that of aluminum;
a gate interconnect contacting the gate electrode;
a source electrode; and
and a drain electrode.
Technical Field
The present disclosure relates to electronic devices, and more particularly, to electronic devices including high electron mobility transistors including gate dielectric layers and gate electrodes.
Background
The high electron mobility transistor may be an enhancement mode transistor. In some enhancement mode high electron mobility transistors, a p-type GaN layer is used as a gate electrode and contacts a channel layer. Such a configuration may help improve pinch-off voltage; however, the carrier mobility under the gate electrode is reduced, and leads to higher on-state resistance between the source electrode and the drain electrode. Some designs, such as multi-finger configurations, may have a relatively high pinch-off voltage to ensure that all fingers are turned off. It would be desirable to further improve enhancement mode high electron mobility transistors without the aforementioned disadvantageous complications.
Disclosure of Invention
The problem to be solved by the invention is to provide an electronic device which may comprise an enhancement transistor with a sufficiently high threshold voltage.
In one aspect, an electronic device is provided. The electronic device may include a channel layer including AlzGa(1-z)N, wherein z is more than or equal to 0 and less than or equal to 0.1; a gate dielectric layer; and a gate electrode of the high electron mobility transistor, wherein the gate dielectric layer is disposed between the channel layer and the gate electrode, and the gate electrode comprises a first gate electrode film contacting the gate dielectric layer, wherein the first gate electrode film comprises a material having a sum of an electron affinity and a band gap energy of at least 6 eV.
In one embodiment, the gate dielectric layer may include: a first dielectric film comprising a first dielectric material; and a second dielectric film covering the first dielectric film and including a second dielectric material, wherein the second dielectric material has a conduction band and a valence band of higher energy than the semiconductor material of the channel layer and the first dielectric material, and has a band gap energy larger than the semiconductor material of the channel layer and the first dielectric material.
In another embodiment, the material of the first gate electrode film may include a material having at least 1 × 1017Polycrystalline p-type semiconductor material with a dopant concentration of one atom per cubic centimeter.
In a particular embodiment, the gate electrode may further include a second gate electrode film overlying the first gate electrode film, wherein the ohmic contact is formed at an interface between the first gate electrode film and the second gate electrode film.
In another particular embodiment, the gate electrode can further include a second gate electrode film overlying the first gate electrode film, wherein the second gate electrode film is a p-type metal-containing film.
In further particular embodiments, the gate electrode can further include a second gate electrode film overlying the first gate electrode film, wherein the second gate electrode film includes a metal having a work function in a range of 4.6eV to 6.0 eV.
In another aspect, an electronic device is provided. The electronic device may include a channel layer including AlzGa(1-z)N, wherein z is more than or equal to 0 and less than or equal to 0.1; and a gate electrode of the high electron mobility transistor. The gate electrode layer may cover the channel layer, and the gate electrode may include a first gate electrode film and a second gate electrode film. Within the gate electrode, a first gate electrode film may be closer to the channel layer than any other of the gate electrodes, and a second gate electrode film may be farther from the channel layer than any other of the gate electrodes. The first gate electrode film can comprise a first material, wherein the first material has a sum of an electron affinity and a band gap energy of at least 6 eV.
In one embodiment, the gate electrode may further include a third gate electrode film disposed between the first gate electrode film and the second gate electrode film, and the third gate electrode film may have a work function that is the same as or less than a work function of the first gate electrode film and the same as or greater than a work function of the second gate electrode film.
In a particular embodiment, the electronic device can further include a barrier layer overlying the channel layer, wherein the first gate electrode film contacts the barrier layer and comprises single crystal p-type GaN, the third gate electrode film comprises polycrystalline p-type GaN, and the second gate electrode film comprises a metal-containing film, wherein an ohmic contact is formed at an interface between the second gate electrode film and the third gate electrode film.
In a further aspect, an electronic device is provided. The electronic device may include a high electron mobility transistor including:
a channel layer comprising GaN;
a barrier layer overlying the channel layer and comprising AlxInyGa(1-x-y)N, wherein 0<x is less than or equal to 1, and y is more than or equal to 0 and less than or equal to 0.3;
a gate dielectric layer extending partially but not completely through the barrier layer, wherein:
the gate dielectric layer includes a first dielectric film and a second dielectric film overlying the first dielectric film,
the first dielectric film comprises a first dielectric material,
the second dielectric film comprises a second dielectric material different from the first dielectric material,
the second dielectric material has a higher energy conduction band and valence band than the GaN and the first dielectric material, and
the second dielectric material has a larger bandgap energy than the semiconductor material of the channel layer and the first dielectric material,
a gate electrode, wherein the gate dielectric layer is disposed between the channel layer and the gate electrode, and the gate electrode comprises:
a polycrystalline p-type semiconductor film in contact with the gate dielectric layer; and
a metal-containing film overlying and in contact with the polycrystalline p-type semiconductor film, wherein:
an ohmic contact is formed at an interface between the polycrystalline p-type semiconductor film and the metal-containing film, and
the metal-containing film comprises a metal having a work function greater than that of aluminum;
a gate interconnect contacting the gate electrode;
a source electrode; and
and a drain electrode.
A technical effect of the present invention is achieved by making a gate electrode have a work function high enough to increase the threshold voltage of a transistor. Such a gate electrode is particularly suitable for transistors in which the gate electrode has a multi-finger configuration.
Drawings
Embodiments are shown by way of example in the drawings and the embodiments are not limited thereto.
Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece including a substrate, a buffer layer, a channel layer, a buffer layer, and a passivation layer.
Fig. 2 includes an illustration of a cross-sectional view of the workpiece of fig. 1 after patterning a portion of the buffer layer and forming a gate dielectric layer.
Fig. 3 includes an illustration of a cross-sectional view of the workpiece of fig. 2 after forming a lower gate electrode film.
Fig. 4 includes an illustration of a cross-sectional view of the workpiece of fig. 3 after forming an upper gate electrode film.
FIG. 5 includes an illustration of a cross-sectional view of the workpiece of FIG. 4 after forming source and drain electrodes and a gate interconnect.
Fig. 6 includes an illustration of a top view of a layout of a multi-finger transistor design in accordance with an embodiment.
Fig. 7 includes an illustration of a top view of a layout of a multi-finger transistor design in accordance with another embodiment.
Figure 8 includes an illustration of a cross-sectional view of a portion of a workpiece including an enhanced high electron mobility transistor according to another embodiment.
Fig. 9 includes a graph of drain current as a function of gate voltage for lower gate electrode films having different work functions.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
Detailed Description
The following description, in conjunction with the drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to help describe the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other embodiments may be employed based on the teachings as disclosed in this application.
The terms "comprises," "comprising," "includes," "including," "has," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. In addition, unless expressly stated to the contrary, "or" means an inclusive or, rather than an exclusive or. For example, condition a or B is satisfied by either: a is true (or present) and B is false (or not present), a is false (or not present) and B is true (or present), and both a and B are true (or present).
In addition, "a" or "an" is used to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. The description is to be construed as including one, at least one, or the singular also includes the plural and vice versa unless it is explicitly stated that the contrary is intended. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, where more than one item is described herein, a single item may be substituted for the more than one item.
The use of the words "about", "about" or "substantially" is intended to mean that the value of a parameter is close to a specified value or location. However, a slight difference may prevent the value or position from being exactly as specified. Thus, from an ideal target as described at all, a difference of at most ten percent (10%) is a reasonable difference for values.
The group numbers corresponding to the columns in the periodic table are based on the IUPAC periodic table, 2016, 11, 28, edition.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. Many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronics arts, without being described herein.
The electronic device may include: a channel layer comprising AlzGa(1-z)N, wherein z is more than or equal to 0 and less than or equal to 0.1; a gate dielectric layer; and a gate electrode of a High Electron Mobility Transistor (HEMT). A gate dielectric layer may be disposed between the channel layer and the gate electrode. The gate electrode comprises a first gate electrode film contacting the gate dielectric layer, wherein the first gate electrode film may comprise a material having a sum of an electron affinity and a band gap energy of at least 6 eV. In some embodiments, the material may include a p-type semiconductor material.
Embodiments of such a device may have an enhancement mode HEMT with a higher threshold voltage than each of the HEMTs having (1) a p-type GaN gate electrode without a gate dielectric layer and (2) a gate dielectric layer and a metal gate electrode. In a non-limiting embodiment, a relatively high threshold voltage may be obtained in which the gate electrode comprises a polycrystalline p-type semiconductor material having a work function of about 7 eV. In another embodiment, a p-type Si material may be used, and the p-type Si material has a work function of about 5.1 eV. A relatively high work function (compared to chemical vapor deposited TiN) provides an increase in threshold voltage. For every 1eV increase in work function, the threshold voltage increases by about 1V. In a particular embodiment, the increment can be at least 0.2V, at least 0.5V, at least 1.1V, or higher. Thus, after reading this specification, skilled artisans will appreciate that the threshold voltage may be varied by selecting materials for the gate electrode.
In one embodiment, a portion of the barrier layer may remain intact under the gate structure. Such a configuration may improve carrier mobility and reduce on-state resistance (Rdson). The process may allow for the formation of a relatively thick barrier layer and removal of a portion of the barrier layer, or may be combined with the process of forming a relatively thin barrier layer, and the access region is grown from the exposed portion of the barrier layer outside the gate region. Thus, different process flows may be used to achieve the benefits described herein.
Fig. 1 includes a cross-sectional view of a portion of a workpiece 100 in which a HEMT is being formed. The workpiece 100 may include a substrate 102, a buffer layer 104, a channel layer 106, a barrier layer 108, and a passivation layer 110. The substrate 102 may comprise silicon, sapphire (single crystal Al)2O3) Silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga)2O3) Spinel (MgAl)2O4) Another suitable substantially single crystal material, etc. The selection of the particular material and crystal orientation along the major surface may be selected based on the composition of the overlying semiconductor layer.
The buffer layer 104 may comprise a III-N material, and in one particular embodiment, comprises AlaGa(1-a)N, wherein a is more than or equal to 0 and less than or equal to 1. The composition of the buffer layer 104 may depend on the composition of the channel layer 106 and the design operating voltage of the HEMT. The composition of the buffer layer 104 may vary with thickness such that the buffer layer 104 has a relatively higher aluminum content closer to the substrate 102 and a relatively higher gallium content closer to the channel layer 106. In a particular embodiment, the cation (metal atom) content in the buffer layer 104 near the substrate 102 may be 10 atomic% to 100 atomic% Al, the remainder being Ga, and the cation content in the buffer layer 104 near the channel layer 106 may be 0 atomic%To 50 atomic% of Al, the remainder being Ga. In another embodiment, the buffer layer 104 may include a plurality of films. The buffer layer 104 may have a thickness in a range of about 1 to 5 microns.
The channel layer 106 may include AlzGa(1-z)N, wherein 0 ≦ z ≦ 0.1, and has a thickness in a range of about 10nm to 4000 nm. In one particular embodiment, the channel layer 106 is a GaN layer (z ═ 0). The channel layer 106 may be inadvertently doped or doped with an electron donor (n-type) dopant or an electron acceptor (p-type) dopant. A high density two-dimensional electron gas (2DEG) may be formed near a portion of the interface of the channel layer 106 and the barrier layer 108 and is responsible for high mobility and low resistivity of the transistor structure when in an on state. In an enhancement mode HEMT, the 2DEG may not be present under the gate structure when the HEMT is in an off state. Any reduction in the 2DEG electrons will increase the on-resistance of the transistor. In one embodiment, the concentration of acceptor (when the carrier is an electron) or donor (when the carrier is a hole) may be kept as low as reasonably possible.
In a particular embodiment, when Metal Organic Chemical Vapor Deposition (MOCVD) is used to form the channel layer 106, the acceptor may include a source gas (e.g., Ga (CH))3)3) Carbon (c) of (a). In a particular embodiment, the lowest trap concentration is desired, but may be limited by growth or deposition conditions and precursor purity. Thus, as the channel layer 106 grows, some carbon may become incorporated, and such carbon may lead to unintentional doping. The carbon content can be controlled by controlling deposition conditions such as deposition temperature and flow rate. In one embodiment, the channel layer 106 has a carrier impurity concentration greater than 0 and less than 1 × 1014Less than 1 × 10 atoms/cubic centimeter15One atom per cubic centimeter or less than 1 x 1016One atom per cubic centimeter, and in another embodiment up to 1X 1016One atom per cubic centimeter. In yet another embodiment, the carrier impurity concentration is at 1 × 1013One atom/cubic centimeter to 1 x 1016In the range of one atom per cubic centimeter.
In one embodiment, the channel layer 106 has a thickness of at least 50 nm. When the thickness is less than 50nm, 2DEG may be more difficult to generate, maintain, or both. In another embodiment, the channel layer 106 has a thickness of at most 5000 nm. In one particular embodiment, a thickness in the range of 50nm to 300nm may provide a sufficiently thick channel layer 106 to allow proper generation and maintenance of the 2DEG, and still obtain a reasonable Rdson. Although not shown, a spacer layer may be used between the channel layer 106 and the barrier layer 108 if desired.
The barrier layer 108 may comprise a III-V semiconductor material, such as a III-N semiconductor material. In a particular embodiment, the barrier layer may comprise AlxInyGa(1-x-y)N, wherein 0<x is less than or equal to 1, and y is more than or equal to 0 and less than or equal to 0.3. The barrier layer 108 may comprise a single film or multiple films. When the barrier layer 108 includes multiple films, the aluminum content may remain substantially the same, or increase with increasing distance from the channel layer 106. As the aluminum content in the barrier layer 108 increases, the thickness of the barrier layer 108 may be relatively thin. In one embodiment, the barrier layer 108 has a thickness of at least 10nm, and in another embodiment, the barrier layer 108 has a thickness of at most 150 nm. In a particular embodiment, the barrier layer 108 has a thickness in the range of 20nm to 90 nm.
The buffer layer 104, the channel layer 106, and the barrier layer 108 are formed using epitaxial growth techniques, and thus at least a portion of the barrier layer 108, the channel layer 106, and the buffer layer 104 may be monocrystalline. In one particular embodiment, the metal-containing film can be formed using metal organic chemical vapor deposition.
The passivation layer 110 may include one or more films. In one embodiment, the passivation layer 110 may include a single silicon nitride film. In another embodiment, the passivation layer 110 may include a lower silicon nitride film closer to the barrier layer 108, an aluminum nitride film disposed between the two silicon nitride films, and an upper silicon nitride film further from the barrier layer 108. The passivation layer 110 may be deposited by Metal Organic Chemical Vapor Deposition (MOCVD) to maintain the crystalline quality of the underlying layers. The passivation layer 110 has a thickness in a range of 2nm to 150 nm.
The passivation layer 110 is patterned to remove the barrier layer 108 and portions of the passivation layer 110 in the gate region where the gate structure will be subsequently formed. The silicon nitride film may be removed using a dry etch using a fluorine chemistry such as SF6、CHF3、NF3And the like. The use of fluorine chemistry does not significantly etch aluminum-containing films or layers because AlF3An aluminum-containing film or layer is formed and further etching is stopped. Therefore, the barrier layer 108 is not significantly etched after removing the silicon nitride film in contact with the barrier layer 108. When the passivation layer 110 includes an aluminum nitride film, the aluminum nitride film may use a chlorine chemistry such as BCl3、HCl、Cl2Etc., or using a base such as tetramethylammonium hydroxide ((CH)3)4) NOH or TMAH), KOH, NaOH, etc. Dry etching of a single film or a combination of films of the passivation layer 110 may be performed using timed etching, end point detection, or a combination of end point detection and timed over-etching.
When etching the barrier layer 108, care may be taken to help maintain the crystalline quality of the barrier layer 108 and the channel layer 106. For example, when the barrier layer 108 is etched by the plasma, exposed portions of the barrier layer 108, the channel layer 106, or both may be damaged by the plasma, thereby reducing the crystal quality at the location where the gate structure is subsequently formed. In a non-limiting embodiment, a portion of barrier layer 108 may be removed using an atomic layer etch. For atomic layer etching, an oxide monolayer is formed from the barrier layer 108 and the oxide is removed using a wet etchant. About 1.0nm to 1.9nm of the thickness of the barrier layer 108 is removed for each oxidation-wet etch cycle. The oxidation and wet etch are repeated until the desired thickness of the barrier layer 108 is removed. In one embodiment, some of the barrier layer 108 remains along the bottom of the opening and has a thickness greater than 0nm and up to 5 nm. The remaining portion of the barrier layer 108 helps to improve carrier mobility under the gate structure and keeps Rdson lower than if a subsequently formed gate dielectric layer contacted the channel layer 106. In another embodiment, the barrier layer 108 may be etched until the channel layer 106 is exposed.
A gate dielectric layer 240 is formed over the channel layer 106 and the barrier layer 108 as shown in figure 2. The gate dielectric layer may include a lower dielectric film 242 and may include one or more other films. In the embodiment shown, the gate dielectric layer 240 further includes an upper dielectric film 244. The lower dielectric film 242 may be formed in contact with an underlying semiconductor layer (such as the barrier layer 108 or the channel layer 106) using a technique to achieve a desired interface between the underlying semiconductor layer and the lower dielectric film 242. The lower dielectric film 242 may have various compositions, which may depend on the composition of the underlying semiconductor layer. In one embodiment, the lower dielectric film 242 may comprise a nitride, an oxide, or an oxynitride. Exemplary materials may include Si3N4、Al2O3、ZrO2、HfO2、SiO2、TiO2、Ta2O5、Nb2O5Another suitable metal oxide or the corresponding oxynitride.
The deposition technique may depend on the particular material formed for the lower dielectric film 242. For Si3N4The lower dielectric film 242 may be formed using a silicon halide and a nitrogen-containing source gas. In one embodiment, the silicon halide may comprise SiH3Cl、SiH2Cl2、SiHCl3Etc., and the nitrogen-containing gas may include NH3、N2、N2O、N2H4And the like. In a particular embodiment, SiH2Cl2And NH3May be used as a source gas and the deposition may be performed at a temperature of at least 1000 ℃ to form Si3N4. In a particular embodiment, the deposition may be performed at a temperature of up to 1150 ℃. The interface between the lower dielectric film 242 and the underlying semiconductor layer has at most 1 × 1013eV-1cm-2The interface trap density of (1).
The lower dielectric film 242 may include metal oxide or metal oxynitride. The metal oxide and metal oxynitride may be formed using MOCVD, Atomic Layer Deposition (ALD), or inorganic CVD (to distinguish from MOCVD). The metal precursor may be a metal hydrideMetal halides, metal alkanes, metal alkoxides or metal amines or amides. The metal halide may or may not be in the form of a hydrate. The aluminum source gas may comprise trimethylaluminum (Al (CH)3)3) Aluminum chloride hexahydrate (AlCl)3·6H20) Aluminum bromide (AlBr)3) And the like. The oxygen source gas may include O2、O3、H2O、N2O, and the like.
The hafnium source gas may include hafnium butoxide (Hf (OC)4H9)4) 2-methoxymethyl-2-propanol hafnium (Hf (OC)4H9OCH3)4) Hafnium dimethylamide (Hf (N (CH))3)2)4) Hafnium diethylamide (Hf (N (C)2H5)2)4) Hafnium tetrachloride (HfCl)4) And the like. Zirconium and titanium have similar compounds as hafnium, with Zr or Ti replacing Hf. The niobium, tantalum and vanadium may be dimethylamides (e.g., Nb (N (CH)3)2)5) Diethyl amide (e.g., Nb (CH)2CH3)2)5) Ethoxides (e.g., Nb (OC)2H5)5) And the like. As previously described, the deposition may be performed as decomposition of a metal source gas, or may include an oxygen source gas or a nitrogen source gas.
The deposition may be carried out at a temperature of at least 1000 c, if possible. If the deposition does not allow such high temperatures, some or all of the lower dielectric film 242 may be deposited and then annealed at a temperature of at least 600 ℃. For example, for ALD, the deposition may be at a temperature in the range of 300 ℃ to 600 ℃. The lower dielectric film 242 may be formed in an iterative process of deposition of a metal precursor monolayer and subsequent annealing at least 600 ℃. This process may be repeated for at least two monolayers and as many monolayers as necessary to achieve the desired thickness.
The upper dielectric film 244 may contain a material having a conduction band and a valence band with higher energy than the semiconductor material of the channel layer 106 and the material of the lower dielectric film 242. The material of the upper dielectric film 244 may be compared to the semiconductor material of the channel layer 106 and the material of the lower dielectric film 242To have a larger bandgap energy. When the lower dielectric film 242 includes Si3N4When the upper dielectric film 244 may include Al2O3、ZrO2、HfO2、SiO2、TiO2、Ta2O5、Nb2O5Another suitable metal oxide or the corresponding oxynitride.
The continuous process description with respect to gate dielectric layer 240 is based on the embodiment as shown. After reading this specification, skilled artisans will appreciate that other embodiments may be used without departing from the concepts described herein. In one embodiment, the lower dielectric film 242 may include a silicon nitride film. The thickness of the interfacial film may be in the range of 10nm to 40 nm. The upper dielectric film 244 may include an aluminum oxide film. Although deposition using MOCVD is not required, MOCVD can be used to deposit the upper dielectric film 244. The oxide film 244 has a thickness in a range of 5nm to 120 nm.
A lower gate electrode film 344 overlies the gate dielectric layer 240 as shown in fig. 3. The lower gate electrode film 344 may include a material having a sum of an electron affinity and a band gap energy of at least 6 eV. Examples of such materials may include polycrystalline p-type semiconductor materials. In one embodiment, the polycrystalline p-type semiconductor material may comprise polycrystalline p-type AlcGa(1-c)N, wherein c is more than or equal to 0 and less than or equal to 1. The unintentionally doped polycrystalline GaN has n-type conductivity, and therefore, the lower gate electrode film 344 includes p-type dopants such as Mg, Zn, Cd, and the like. In another embodiment, p-type SiC or p-type Si may be used for the lower gate electrode film 344. The p-type dopant for p-type SiC may include a p-type dopant used in Si. The lower gate electrode film 344 may have at least 1 × 1017Dopant concentration of one atom per cubic centimeter. In another embodiment, the dopant concentration is at most 1X 1022One atom per cubic centimeter. The lower gate electrode film 344 may be formed using any of the techniques available for forming the channel layer 106 or the barrier layer 108. The p-type dopant may be incorporated in situ or introduced into the film after deposition. In a particular embodiment, molecular beam epitaxy may be used at 625The lower gate electrode film 344 is formed at a temperature in the range of deg.c to 675 deg.c.
When the lower gate electrode film 344 contains p-type GaN, the work function is about 6 to 7eV, and the threshold voltage can be increased by more than 2V compared to chemical vapor deposited TiN. In another embodiment, p-type Si with a work function of about 5.1eV may be used. Therefore, p-type Si can increase the threshold voltage by about 0.5V. The lower gate electrode film 344 may have a thickness in a range of 10nm to 300 nm. In another embodiment, the lower gate electrode film 344 may be thicker if needed or desired.
The lower gate electrode film 344 may be patterned to achieve a shape for forming a gate electrode of an enhancement mode HEMT. A portion of the lower gate electrode film 344 located outside the gate region may be removed using a technique that does not significantly etch the gate dielectric layer 240. When the lower gate electrode film 344 contains p-type GaN and the upper gate dielectric film 244 contains Al2O3In this case, the lower gate electrode film 344 may be dry-etched using a fluorine chemical as described above. In another embodiment, the lower gate electrode film 344 may be etched using molten KOH. After reading this specification, a skilled artisan will be able to determine the etchant used during patterning based at least in part on the particular materials of the upper gate dielectric film 244 and the lower gate electrode film 344.
An upper gate electrode film 444 of the gate electrode 440 may be formed over the lower gate electrode layer 344, as shown in fig. 4. The upper gate electrode film 444 includes a material that can form an ohmic contact with the lower gate electrode film 344. The material of the upper gate electrode film 444 may be a metal-containing material having p-type conductivity. The upper gate electrode film 444 can include NiO, a Ti-Al alloy, Co, Pt, Rb, or another suitable p-type metal-containing material. Accordingly, an ohmic contact may be formed at the interface between the lower gate electrode film 344 and the upper gate electrode film 444. If the upper gate electrode film 444 has n-type conductivity, the interface between the lower gate electrode film 344 and the upper gate electrode film 444 will form a schottky contact. Unintentionally doped polycrystalline GaN formed by MOCVD, Ni annealed in nitrogen, and ZnO are examples of n-type metal-containing materials and may not be used when the lower gate electrode film 344 includes a material having p-type conductivity.
The upper gate electrode film 444 has a thickness in the range of 10nm to 500 nm. The upper gate electrode film 444 can be formed using various formation techniques, such as chemical vapor deposition, ALD, molecular beam epitaxy, and the like. When the upper gate electrode film 444 contains NiO, the upper gate electrode film 444 may be formed by depositing a Ni film using rapid thermal annealing in an oxygen-containing atmosphere and oxidizing the Ni film to form NiO having p-type conductivity. A portion of the upper gate electrode film 444 located outside the gate region is removed. The gate electrode 440 includes portions of the lower gate electrode film 344 and the upper gate electrode film 344 within the gate region.
In another embodiment, the access region may be formed to avoid the need for an etch stop layer 108. In one embodiment, the barrier layer 108 may be formed having a thickness corresponding to the thickness of the barrier layer 108 under the gate structure. A sacrificial structure may be formed in the gate region and an access region may be grown on the exposed portion of the relatively thin barrier layer 108. After removal of the sacrificial structures, a gate dielectric layer 240 and a gate electrode 440 may be formed in the gate region. Thus, different process flows may be used without departing from the concepts described herein.
Fig. 5 shows the workpiece 100 after forming an insulating layer 500, source 522 and drain 526 electrodes, and a gate interconnect 524. An insulating layer 500 may be formed over the gate electrode 440 and the upper dielectric layer 244. The insulating layer 500 may include an oxide, a nitride, or an oxynitride. The insulating layer 500 may have a thickness in a range of 50nm to 500 nm. The insulating layer 500 may be patterned to define contact openings for the source and drain electrodes 522, 526 and the gate interconnect 524.
A contact opening for the gate interconnect 524 can extend through the insulating layer 500 and fall on the gate electrode 440. Contact openings for the source electrode 522 and the drain electrode 526 may extend through the insulating layer 500, the gate dielectric layer 240, and the passivation layer 110. In one embodiment, contact openings for source electrode 522 and drain electrode 526 fall on barrier layer 108. In another embodiment, the contact openings for the source electrode 522 and the drain electrode 526 may extend through a portion, but not all, of the barrier layer 108, or through the entire thickness of the barrier layer 108 and contact the channel layer 106. In one particular embodiment, contact openings for source electrode 522 and drain electrode 526 are formed such that a portion of barrier layer 108 is disposed between channel layer 106 and source electrode 522 and drain electrode 526. The thickness of barrier layer 108 under source electrode 522 and drain electrode 526 may be different than the thickness of barrier layer 108 under the bottom of the gate structure. In a particular implementation, a thickness of barrier layer 108 under the gate structure is less than a thickness of barrier layer 108 under source electrode 522 and drain electrode 526.
A conductive layer is formed over the gate dielectric layer 240 and within the contact opening. The conductive layer may comprise a single film or multiple films. For gate interconnect 524, the work function of the predominant material within the conductive layer may have a different work function than lower gate electrode film 344, upper gate electrode film 444, or both. In a particular embodiment, the work function of the primary material within the conductive layer may have a work function that is less than the work function of the lower gate electrode film 344.
The conductive layer may include one or more films. In one embodiment, the conductive layer may be in contact with the upper gate electrode film 444. In another embodiment (not shown), the upper gate electrode film 444 may not be used when a portion of the conductive layer in contact with the gate electrode 440 has p-type conductivity.
In one embodiment, the conductive layer may include an adhesive film and a barrier film. Such films may comprise Ta, TaSi, Ti, TiW, TiSi, TiN, etc. The conductive layer may further include a conductive film. The body film may comprise Al, Cu, or another material that is more conductive than other films within the conductive layer. In one embodiment, the body film can comprise at least 90 wt.% Al or Cu. The body film can have a thickness at least as thick as the other films within the conductive layer. In one embodiment, the thickness of the body film is in the range of 20nm to 900nm, and in a more particular embodiment, in the range of 50nm to 500 nm. More or fewer films may be used in the conductive layer. The number and composition of the films within the conductive layer may depend on the needs or desires of a particular application. After reading this specification, skilled artisans will be able to determine the composition of conductive layers appropriate for their devices.
The conductive layer is patterned to form a source electrode 522, a gate interconnect 524, and a drain electrode 526. In another implementation, the gate interconnect 524 can be formed at a different interconnect level than the source electrode 522 and the drain electrode 526.
One or more additional interconnect levels and passivation layers may be formed over the workpiece. Each interconnect level may include an interlayer dielectric layer and an interconnect. A conductive layer may be used at each interconnect level. The conductive layer may be the same as or different from other conductive layers previously described in this specification. A substantially finished electronic device has been formed.
Fig. 6 and 7 include illustrations of top views of exemplary layouts of electronic devices. This layout shows a multi-finger design for source electrode 522, gate electrode 440, and drain electrode 526. For simplicity, the portion of the gate interconnect 524 overlying the gate electrode 440 is not shown to better illustrate the positional relationship between the gate electrode 440, the gate runner 642, and the gate bond pad 644 within the multi-finger design. In implementation, the gate interconnect 524 may overlie the gate electrode 440 and the portion including the gate runner 642 and the gate bond pad 644. Gate electrode 440 is not under gate bond pad 644 and portions of gate runner 642. In fig. 6 and 7, the source electrode 522, the gate electrode 440, and the drain electrode 526 are shown in the center of the drawings.
Referring to fig. 6, a drain bonding pad 666 is electrically connected to the drain electrode 526, a gate bonding pad 644 is electrically connected to the gate electrode 440 via a gate runner 642, and a source bonding pad 662 is electrically connected to the source electrode 522. The bond pads may be formed using any of the materials and techniques described with respect to the conductive layers used for source electrode 522 and drain electrode 526. In another embodiment, bond pads 662 and 666 may be replaced with conductive plates. Referring to fig. 7, the drain plate 766 is electrically connected to the drain electrode 526 via a contact 736, and the source plate 762 is electrically connected to the source electrode 522 via a contact 732. Drain plate 762 and source plate 766 may be plated onto the workpiece or may be attached as conductive foils. Conductive materials for the drain plate 762 and the source plate 766 may include Cu, Ni, Au, etc. If needed or desired, an intermediate metallization layer, such as Ti, TiN, TiW, W, etc., may be formed prior to plating.
In another embodiment, the gate electrode of the enhancement mode HEMT may have one or more additional gate electrode films and may not require a gate dielectric layer. In fig. 8, gate electrode 840 includes a lowermost gate electrode film 842, an intermediate gate electrode film 844, and an uppermost gate electrode film 846. Within gate electrodes such as gate electrode 840 and gate electrode 440 (fig. 4), a gate electrode film such as lowermost gate electrode film 842 or lower gate electrode film 344 (fig. 4) closest to channel layer 106 has the same or higher work function than any other of the gate electrodes that overlies such lowermost gate electrode film 842 or lower gate electrode film 344, and a gate electrode film such as uppermost gate electrode film 846 or upper gate electrode film 444 (fig. 4) furthest from channel layer 106 has the same or lower work function than any other of the gate electrodes that overlies such uppermost gate electrode film 846 or upper gate electrode film 444.
In fig. 8, the lowermost gate electrode film 842 of the gate electrodes 840 may be any of the compositions described with respect to the lower gate electrode film 344 or may comprise a single crystalline p-type semiconductor material. In one embodiment, the single crystalline p-type semiconductor material may comprise single crystalline p-type single crystalline AldGa(1-d)N, wherein d is more than or equal to 0 and less than or equal to 1. Unlike unintentionally doped polycrystalline GaN, single crystal GaN formed by MOCVD has p-type conductivity. For single crystal GaN, when the p-type dopant is C, the dopant concentration can be controlled by the deposition conditions. Alternatively, or in addition to doping during deposition, the lowermost gate electrode film 842 can include different p-type dopants, such as Mg, Zn, Cd, and the like. The lowermost gate electrode film 842 may have at least 1 × 1017Is based on atomDopant concentration in cubic centimeters. In another embodiment, the dopant concentration is at most 1X 1022One atom per cubic centimeter. When the lowermost gate electrode film 842 comprises single crystal p-type GaN, the work function is about 6eV to 7 eV. In a particular embodiment, a lowermost gate electrode film 842 can be epitaxially grown from barrier layer 108. The lowermost gate electrode film 842 may have a thickness in the range of 10nm to 300 nm. In another embodiment, the lowermost gate electrode film 842 can be thicker, if needed or desired.
Dielectric layer 852 is formed over barrier layer 108 and lowermost gate electrode film 842. Dielectric layer 852 may comprise any material, may be formed using any technique, and has any thickness described with respect to upper gate dielectric film 244. In one particular implementation, dielectric layer 852 can comprise Al formed by ALD2O3. Dielectric layer 852 is patterned to expose the lowermost gate electrode film 842. Intermediate gate electrode film 844 and uppermost gate electrode film 846 may be formed and patterned as shown in fig. 8. Intermediate gate electrode film 844 can comprise any material, can be formed using any technique, and has any thickness described with respect to lower gate electrode film 344. The middle gate electrode film 844 has a different composition or characteristic than the lowermost gate electrode film 842. In a non-limiting example, lowermost gate electrode film 842 may comprise single crystal p-type GaN, and intermediate gate electrode film 844 may comprise polycrystalline p-type GaN. Uppermost gate electrode film 846 may comprise any material, may be formed using any technique, and has any thickness described with respect to upper gate electrode film 444. Processing continues as previously described to complete the formation of the enhancement mode HEMT.
The embodiments described herein can help to increase the threshold voltage of an enhancement mode HEMT. The composition of the lower gate electrode film 344 may allow for a significantly higher work function than if the gate interconnect, which is comprised primarily of aluminum, contacts the gate dielectric layer 240. Fig. 9 includes plots of drain current (Ids) versus gate voltage (Vgs) for lower gate electrode films having different work functions (W). The graph is a simulated graph in which the gate dielectric composition and thickness are held constant and the drain voltage (Vds) is 0.1V. As shown in fig. 9, the threshold voltage increases by about 1V for every 1eV increase in work function. The work function of aluminum is about 4.1eV, and that of polycrystalline p-type GaN is in the range of 6eV to 7 eV. Thus, when a TiN/Al gate electrode (e.g., chemical vapor deposited TiN would be in contact with the gate dielectric layer 240) is replaced with a p-type GaN gate electrode, the increase in threshold voltage may exceed 2 eV. After reading this specification, the skilled artisan will be able to select a material for the lower gate electrode film 344 that increases the threshold voltage of the enhancement mode HEMT by at least 0.2V, at least 0.5V, at least 1.1V, or another voltage for a particular application. HEMTs may have better pinch-off characteristics, especially when the threshold voltage is at least 2V. The improved pinch-off characteristics are particularly useful in multi-finger transistor designs, such as those shown in fig. 6 and 7. As shown and described with respect to fig. 8, an enhancement mode HEMT is expected to have a similar effect.
Materials that may be used for upper gate electrode film 344, uppermost gate electrode film 846, and gate interconnect 524 include metals commonly used for processing Si-based Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Thus, at least part of the processing may be performed in the fabrication area for forming the MOSFET.
In addition, a relatively high quality interface is formed between the gate dielectric layer 240 and an underlying semiconductor layer (such as the barrier layer 108 or the channel layer 106). This process does not require dry etching of the barrier layer 108 and, therefore, the surface of the barrier layer 108 or the channel layer 106 may have less plasma damage because the barrier layer 108 is not etched by the plasma. The gate dielectric layer 240 may be formed using processing conditions that help maintain the crystalline quality of the barrier layer 108 and the channel layer 106. The gate dielectric layer 240 may be formed using processing conditions that facilitate producing an enhancement mode HEMT with a reduced interface state density and reduced carrier trap density at the interface between the gate dielectric layer 240 and an underlying semiconductor layer, such as the barrier layer 108 or the channel layer 106.
In one embodiment, a portion of the barrier layer 108 keeps the gate structure spaced apart from the channel layer 106. Such a configuration may improve carrier mobility and reduce Rdson. The increased work function of the lower gate electrode film 344 allows the threshold voltage of the HEMT to be high enough to properly pinch off the transistors under the gate structure when the HEMT is in the off state.
Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Upon reading this specification, skilled artisans will appreciate that those aspects and embodiments are exemplary only, and do not limit the scope of the invention. Implementations may be in accordance with any one or more of the items listed below.
