阅读说明：本技术 一种rc-igbt半导体器件 (RC-IGBT semiconductor device ) 是由 不公告发明人 于 2019-10-18 设计创作，主要内容包括：本发明公开了一种RC-IGBT半导体器件,在1个半导体衬底形成有IGBT和FWD,IGBT具有p型基极层和n型漂移层和多个沟槽栅极结构,栅电极穿过p型基极层,p型基极层由栅电极分成多个间隔区域；在间隔区域中,p型基极层上表面设置有p+发射极区和n+发射极区,n+发射极及p型基极层的侧壁均与沟槽侧壁外表面相接触；FWD从上到下设置有多个虚拟沟道、p型基极层,虚拟沟道间隔穿过p型基层,并且虚拟沟道的底部到达衬底,在FWD的虚拟沟道与IGBT的栅电极之间的p型基极层上表面设置有p+阳极层；在FWD部分的n型漂移层的背面形成的多个间隔的深n+阴极区以及设置在深n+阴极区域间隔之间的浅p+阴极区。本发明实现了无振荡的内置FWD的RC-IGBT半导体器件。(The invention discloses an RC-IGBT semiconductor device, wherein an IGBT and an FWD are formed on 1 semiconductor substrate, the IGBT is provided with a p-type base layer, an n-type drift layer and a plurality of trench gate structures, a gate electrode penetrates through the p-type base layer, and the p-type base layer is divided into a plurality of interval regions by the gate electrode; in the spacing region, a p + emitter region and an n + emitter region are arranged on the upper surface of the p-type base layer, and the side walls of the n + emitter and the p-type base layer are both contacted with the outer surface of the side wall of the groove; the FWD is provided with a plurality of virtual channels and a p-type base layer from top to bottom, the virtual channels penetrate through the p-type base layer at intervals, the bottoms of the virtual channels reach the substrate, and a p + anode layer is arranged on the upper surface of the p-type base layer between the virtual channels of the FWD and a gate electrode of the IGBT; a plurality of spaced deep n + cathode regions formed on a back surface of the n-type drift layer of the FWD portion and shallow p + cathode regions disposed between the deep n + cathode region spaces. The invention realizes the RC-IGBT semiconductor device with built-in FWD and no oscillation.)

1. An RC-IGBT semiconductor device, wherein an IGBT and an FWD are formed on 1 semiconductor substrate, the IGBT having:

the p-type base layer is formed on the surface of the n-type drift layer;

a plurality of trench gate structures each including a trench on the substrate and a conductive film in the trench via an insulating film and a polysilicon gate electrode and a gate oxide layer of an IGBT element; a SiO2 gate oxide layer is arranged in the groove on the substrate, and polycrystalline silicon is deposited on the SiO2 gate oxide layer;

the gate electrode penetrates through the p-type base layer, and the p-type base layer is divided into a plurality of spacing areas by the gate electrode;

in the spacing area, the upper surface of the p-type base layer is provided with a p + emitter area and an N + emitter area, the p + emitter area is arranged side by side with the N + emitter area, and the N + emitter area is arranged on two sides of the p + emitter area; an n + emitter region disposed in a surface portion of the spacer region, sidewalls of the n + emitter and the p-type base layer each contacting an outer surface of a sidewall of the trench, the n + emitter region and the p + emitter region each being electrically coupled with the emitter electrode;

the bottom of the n-type drift layer is provided with an n-type electric field stopping layer; the back surface of the n-type electric field stop layer is in contact with a p + collector region, and the p + collector region is electrically coupled with a collector electrode;

the FWD has: a plurality of dummy channels and p-type base layers are arranged from top to bottom and are formed on the surface of the n-type drift layer; the dummy channels are connected to the emitter electrodes by being coupled together with each other as signal lines;

the dummy channel interval passes through the p-type base layer, the bottom of the dummy channel reaches the substrate, and a p + anode layer is also arranged on the upper surface of the p-type base layer between the dummy channel of the FWD and the gate electrode of the IGBT;

a plurality of spaced n + cathode regions formed on a back surface of the n-type drift layer of the FWD portion, the n + cathode regions having a depth greater than that of the p + cathode regions, and p + cathode regions disposed between the n + cathode region spacings, the n + cathode regions and the p + cathode regions being electrically connected to the collector electrode.

2. An RC-IGBT semiconductor device according to claim 1, characterized in that the n + emitter region has the higher impurity concentration than the substrate.

3. An RC-IGBT semiconductor device as claimed in claim 1, characterized in that an N-type semiconductor blocking layer is provided under the p-type base layer of the emitter region and between the gate electrode of the IGBT and the dummy channel of the FWD.

4. An RC-IGBT semiconductor device according to any one of claims 1 to 3, wherein a lifetime control region is provided right under the anode part of the FWD part, above the deep n + cathode region and the shallow p + cathode region.

5. An RC-IGBT semiconductor device according to claim 4, wherein said lifetime control region is formed by helium ion implantation.

6. An RC-IGBT semiconductor device according to claim 5, wherein the starting material of the semiconductor device is stainless steel material with helium ion shielding capability, and is subjected to photoresist lamination process, exposure and development; thereafter, the material is chemically etched; finally, the two etched stainless steel masks are connected using diffusion bonding techniques.

7. An RC-IGBT semiconductor device according to claim 6, wherein the thickness of the stainless steel material is 100-200 μm.

Technical Field

The invention belongs to the technical field of power semiconductors, and particularly relates to an RC-IGBT semiconductor device.

Background

An igbt (insulated Gate Bipolar transistor), an insulated Gate Bipolar transistor, may be regarded as a composite of a Bipolar high-power transistor and a power field effect transistor. The IGBT is a composite full-control voltage-driven power semiconductor device consisting of a BJT (bipolar junction transistor) and an MOS (insulated gate field effect transistor), and has the advantages of both high input impedance of the MOSFET and low conduction voltage drop of the GTR. Turning on the IGBT by providing a transistor base current; conversely, if a reverse gate voltage is applied, the channel is eliminated and the IGBT is turned off by the reverse gate current.

The IGBT integrates the advantages of small GTR on-state voltage drop, large current-carrying density, high withstand voltage, small power MOSFET driving power, high switching speed, high input impedance and good thermal stability, and is popular among people. The development success of the inverter provides favorable conditions for improving the performance of power electronic devices, particularly for miniaturization, high efficiency and low noise of the inverter, so that the inverter can be used for locomotives and trains, electric automobile trains and hybrid electric automobiles. The growth in the area of renewable energy sources such as solar and wind power has led to a demand for high power IGBTs.

However, the fast switching speeds of converter/inverter technology may cause electromagnetic interference due to high di/dt, dv/dt. All power electronic equipment generates and emits harmful electrical signals (EMI noise), resulting in degradation of the performance of other electrical/electronic equipment. They generate high frequency conducted and radiated EMI noise and distorted line currents due to the shaped edges of the switching waveform with high dv/dt. Undesirable electromagnetic interference effects include interference with wireless systems (radio, television, mobile, data transmission), failure of biomedical equipment, ABS braking systems and electronic control systems in electric vehicles and electric cars.

The high dv/dt and di/dt of IGBT modules are prone to conductive and radiative emissions, since IGBT modules switch hundreds of voltages and currents on and off in hundreds of nanoseconds. These high dv/dt and di/dt are caused by the turn-off waveform of the IGBT and the reverse recovery waveform of the built-in FWD.

As shown in fig. 1, which shows the half-bridge current voltage and reverse recovery waveform of the conventional RC-IGBT device, it can be seen from the figure that when the switching speed of the IGBT is high, high di/dt is generated when the IGBT is turned off and when the FWD is recovered in the reverse direction, and a turn-off surge voltage is generated due to the inductance of the wiring around the module. The figure shows an operation waveform when the IGBT is turned off, and a high voltage is generated in the main circuit distributed inductance due to a sudden change in the main circuit current when the IGBT is turned off in the turn-off surge voltage. The built-in FWD produces a high spike voltage when the IGBT turns off and an oscillation in voltage when the FWD recovers in the reverse direction. Fig. 1(c) shows the waveform form of FWD fast reverse recovery, whereas the fast waveform causes current oscillation due to high di/dt at the end of the recovery phase.

Therefore, how to avoid the voltage and current oscillation caused by high di/dt and dv/dt in the turn-off stage of the IGBT is a technical problem to be solved in the art without sacrificing the performance of any IGBT module.

Disclosure of Invention

The invention aims to solve the technical problem of how to avoid voltage and current oscillation caused by high di/dt and dv/dt in the turn-off stage of an IGBT on the premise of not sacrificing the performance of any IGBT module, and provides an RC-IGBT semiconductor device.

In order to solve the technical problems, the invention adopts the following technical scheme:

provided is an RC-IGBT semiconductor device, wherein an IGBT and an FWD are formed on 1 semiconductor substrate, the IGBT is characterized in that:

the p-type base layer is formed on the surface of the n-type drift layer;

a plurality of trench gate structures each including a trench on the substrate and a conductive film in the trench via an insulating film and a polysilicon gate electrode and a gate oxide layer of an IGBT element; a SiO2 gate oxide layer is arranged in the groove on the substrate, and polycrystalline silicon is deposited on the SiO2 gate oxide layer; the gate electrode penetrates through the p-type base layer, and the p-type base layer is divided into a plurality of spacing areas by the gate electrode;

in the spacing area, the upper surface of the p-type base layer is provided with a p + emitter area and an N + emitter area, the p + emitter area is arranged side by side with the N + emitter area, and the N + emitter area is arranged on two sides of the p + emitter area; an n + emitter region disposed in a surface portion of the spacer region, sidewalls of the n + emitter and the p-type base layer each contacting an outer surface of a sidewall of the trench, the n + emitter region and the p + emitter region each being electrically coupled with the emitter electrode;

the bottom of the n-type drift layer is provided with an n-type electric field stopping layer; the back surface of the n-type electric field stop layer is in contact with a p + collector region, and the p + collector region is electrically coupled with a collector electrode;

the FWD has: a plurality of dummy channels and p-type base layers are arranged from top to bottom and are formed on the surface of the n-type drift layer; the dummy channels are connected to the emitter electrodes by being coupled together with each other as signal lines;

the dummy channel interval passes through the p-type base layer, and the bottom of the dummy channel reaches the substrate; a p + anode layer is also arranged on the upper surface of the p-type base layer between the virtual channel of the FWD and the gate electrode of the IGBT;

a plurality of spaced deep n + cathode regions formed on a back surface of the n-type drift layer of the FWD portion, and shallow p + cathode regions disposed between the deep n + cathode region spaces, the n + cathode regions and the p + cathode regions being electrically connected to the collector electrode. The invention realizes low parasitic capacitance by the design, and obtains low collector emitter saturation voltage drop VCE (sat) and a large short-circuit current safe working area.

Preferably, the n + emitter region has the impurity concentration higher than the substrate.

Further, an N-type semiconductor blocking layer is disposed below the p-type base layer of the emitter region and between the gate electrode of the IGBT and the dummy channel of the FWD.

An N-type semiconductor blocking layer as an N-well is provided below the emitter region and the p-type base layer as a p-well and between the gate electrode of the IGBT and the dummy channel of the FWD, preventing the release of holes when the IGBT is on. Thus, the on-state voltage Von and the forward voltage are reduced, and the influence of the potential in the gate electrode is avoided. In addition, since the n-type semiconductor layer does not contact the sidewall of the trench, an increase in the near field of the trench is suppressed, thereby improving the breakdown voltage.

Further, a lifetime control region is provided directly below the anode portion of the FWD portion, the lifetime control region being above the deep n + cathode region and the shallow p + cathode region.

Furthermore, the lifetime control region is formed by implanting helium ions.

Still further, the starting material of the semiconductor device is stainless steel, which has the shielding capability to helium ions, the thickness of the material is 100-200 μm, and then a photoresist lamination process is carried out, and exposure and development are carried out; thereafter, the material is chemically etched; finally, the two etched stainless steel masks are connected using diffusion bonding techniques.

The invention has the following beneficial effects:

the invention realizes low parasitic capacitance, and obtains low collector emitter saturation voltage drop VCE (sat) and a large short-circuit current safe working area;

the invention reduces the voltage Von and the forward voltage in the on state, and avoids the influence of the potential in the gate electrode. In addition, since the n-type semiconductor layer does not contact the sidewall of the trench, an increase in the near field of the trench is suppressed, thereby improving the breakdown voltage.

The invention adopts a service life control technology and a new cathode structure to realize built-in FW without oscillation.

Drawings

FIG. 1 is a graph of half-bridge current-voltage and reverse recovery waveforms for a conventional RC-IGBT device, where 1(a) is the half-bridge, 1(b) is the current and voltage of the IGBT, and 1(c) is the fast reverse recovery;

FIG. 2 is a schematic diagram of voltage and current oscillations at FWD reverse recovery;

fig. 3(a) is a typical reverse recovery wave form at FWD reverse recovery; fig. 3(b) is a hole carrier density with time at the time of FWD reverse recovery;

fig. 4 is a schematic diagram of carrier distribution at the time of IGBT turn-off transient;

FIG. 5 is a schematic cross-sectional view of an RC-IGBT according to an embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view of an RC-IGBT according to an embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view of an RC-IGBT according to an embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view of an RC-IGBT according to an embodiment of the present invention;

the labels in the figure are: 1: FWD; 2: an IGBT; 3: an n + cathode region; 4: an n-type electric field stop layer; 5: an n-type drift layer; 6: a lifetime control region; 7: a gate electrode; 8: a p + collector region; 9: a collector electrode; 10: a p + cathode region; 11: an n-type semiconductor barrier layer; 12: an emitter electrode; 13: a virtual channel; 14: an insulating film; 15: a p + anode region; 16: a p-type base layer; 17: an n + emitter region; 18: a p + emitter region.

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.