阅读说明：本技术 一种异质结电池制备方法 (Preparation method of heterojunction battery ) 是由 不公告发明人 于 2019-10-18 设计创作，主要内容包括：本发明公开了一种异质结电池制备方法,异质结电池包括依次顺序设置的栅电极、透明导电层、n型非晶硅层、本征非晶硅层、单晶硅基底、本征非晶硅层、p型非晶硅层、透明导电层及栅电极,制备方法包括：在单晶硅基底的一端面上进行本征非晶硅层的镀膜工艺,翻片,在和单晶硅基底的一端面相对设置的另一端面上进行本征非晶硅层的镀膜工艺,进行n型非晶硅层的镀膜工艺,翻片,进行p型非晶硅层的镀膜工艺。该制备方法可降低掺杂的n或者p型材料污染另外一面没有镀本征非晶硅层的硅片的表面；而且,可更好地匹配各薄膜层镀膜时的工艺温度,从而提升异质结电池的性能。(The invention discloses a preparation method of a heterojunction battery, wherein the heterojunction battery comprises a gate electrode, a transparent conducting layer, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, a monocrystalline silicon substrate, an intrinsic amorphous silicon layer, a p-type amorphous silicon layer, a transparent conducting layer and a gate electrode which are sequentially arranged, and the preparation method comprises the following steps: the method comprises the steps of performing a film coating process of an intrinsic amorphous silicon layer on one end face of a monocrystalline silicon substrate, turning a wafer, performing a film coating process of an intrinsic amorphous silicon layer on the other end face opposite to one end face of the monocrystalline silicon substrate, performing a film coating process of an n-type amorphous silicon layer, turning a wafer, and performing a film coating process of a p-type amorphous silicon layer. The preparation method can reduce the pollution of the doped n-type or p-type material on the surface of the silicon chip of which the other surface is not plated with the intrinsic amorphous silicon layer; moreover, the process temperature of each thin film layer during film coating can be better matched, so that the performance of the heterojunction battery is improved.)

1. A preparation method of a heterojunction battery comprises a monocrystalline silicon substrate, intrinsic amorphous silicon layers respectively arranged on two opposite end faces of the monocrystalline silicon substrate, p-type amorphous silicon layers and n-type amorphous silicon layers respectively arranged on the intrinsic amorphous silicon layers on two faces, transparent conducting layers respectively arranged on the p-type amorphous silicon layers and the n-type amorphous silicon layers, and gate electrodes respectively arranged on the transparent conducting layers on two faces, and is characterized in that: the preparation method comprises the following steps: and performing the film coating process of the intrinsic amorphous silicon layer on one end face of the monocrystalline silicon substrate, turning the wafer, performing the film coating process of the intrinsic amorphous silicon layer on the other end face opposite to one end face of the monocrystalline silicon substrate, performing the film coating process of the n-type amorphous silicon layer, turning the wafer, and performing the film coating process of the p-type amorphous silicon layer.

2. The method of manufacturing a heterojunction cell according to claim 1, wherein: and the heterojunction cell is subjected to a film coating process of each thin film layer in a die cavity, and the process temperature in the die cavity is not higher than 190 ℃ when the film coating process of the p-type amorphous silicon layer is carried out.

3. The method of claim 2, wherein the process temperature in the cavity is 150 ~ 170 degrees to form the p-type amorphous silicon layer.

4. The method of manufacturing a heterojunction cell according to claim 1, wherein: the intrinsic amorphous silicon layers on the two opposite end faces of the monocrystalline silicon substrate are formed by performing layer-by-layer film coating from the monocrystalline silicon substrate.

5. The heterojunction cell preparation method of claim 4, wherein: the intrinsic amorphous silicon layer is provided with n layers, wherein the first layer is in contact with the monocrystalline silicon substrate, the n layer is in contact with the p-type amorphous silicon layer and the n-type amorphous silicon layer, the ratio of hydrogen to silane in the intrinsic amorphous silicon layer of the first layer is 0:1 to 1:1, and the ratio of hydrogen to silane in the intrinsic amorphous silicon layer of the n layer is 10:1 to 500: 1.

6. The method of claim 5, wherein the intrinsic amorphous silicon layer further comprises one or more intermediate intrinsic amorphous silicon layers between the first intrinsic amorphous silicon layer and the n-th intrinsic amorphous silicon layer, and hydrogen and silane in each of the intermediate intrinsic amorphous silicon layers gradually transition from the first intrinsic amorphous silicon layer to the n-th intrinsic amorphous silicon layer in a ratio of 1:1 ~ 10: 1.

7. The heterojunction cell preparation method of claim 5, wherein: the plating rate of the first intrinsic amorphous silicon layer is more than 5 angstroms per second.

8. The heterojunction cell preparation method of claim 5, wherein: and the coating rate of the n-th intrinsic amorphous silicon layer is less than 3 angstroms per second.

9. The heterojunction cell preparation method of claim 4, wherein: when the intrinsic amorphous silicon layer is coated layer by layer, pure hydrogen plasma treatment is carried out after the coating process of each layer is finished.

10. The method of manufacturing a heterojunction cell according to claim 1, wherein: the thickness of the intrinsic amorphous silicon layer on the front side of the heterojunction cell is smaller than that of the intrinsic amorphous silicon layer on the back side of the heterojunction cell.

11. The method of manufacturing a heterojunction cell according to claim 1, wherein: and oxygen is doped in the intrinsic amorphous silicon layer positioned on the front side of the heterojunction cell.

12. The method of manufacturing a heterojunction cell according to claim 1, wherein: and increasing oxygen doping and/or carbon doping in the process of coating the p-type amorphous silicon layer and the n-type amorphous silicon layer, wherein the ratio of the oxygen doping and/or the carbon doping to silane is increased from 0:1 to 1:1.4 from the beginning of coating the p-type amorphous silicon layer and the n-type amorphous silicon layer to the end of coating.

13. The method of manufacturing a heterojunction cell according to claim 1, wherein: the heterojunction battery is subjected to the film coating process of each thin film layer in the die cavity, and different thin film layers are subjected to the film coating process in different die cavities respectively.

Technical Field

The invention relates to the technical field of battery manufacturing, in particular to a heterojunction battery preparation method.

Background

The heterojunction cell comprises a monocrystalline silicon substrate, intrinsic amorphous silicon layers respectively arranged on two opposite end faces of the monocrystalline silicon substrate, a p-type amorphous silicon layer and an n-type amorphous silicon layer respectively arranged on the intrinsic amorphous silicon layers on the two faces, transparent conductive layers respectively arranged on the p-type amorphous silicon layer and the n-type amorphous silicon layer, and gate electrodes respectively arranged on the transparent conductive layers on the two faces.

Disclosure of Invention

It is an object of the present invention to address the problems of the prior art by providing an improved method of fabricating a heterojunction cell.

In order to achieve the purpose, the invention adopts the technical scheme that:

a preparation method of a heterojunction battery comprises a monocrystalline silicon substrate, intrinsic amorphous silicon layers respectively arranged on two opposite end faces of the monocrystalline silicon substrate, p-type amorphous silicon layers and n-type amorphous silicon layers respectively arranged on the intrinsic amorphous silicon layers on the two faces, transparent conducting layers respectively arranged on the p-type amorphous silicon layers and the n-type amorphous silicon layers, and gate electrodes respectively arranged on the transparent conducting layers on the two faces, wherein the preparation method comprises the following steps: and performing the film coating process of the intrinsic amorphous silicon layer on one end face of the monocrystalline silicon substrate, turning the wafer, performing the film coating process of the intrinsic amorphous silicon layer on the other end face opposite to one end face of the monocrystalline silicon substrate, performing the film coating process of the n-type amorphous silicon layer, turning the wafer, and performing the film coating process of the p-type amorphous silicon layer.

Preferably, the heterojunction cell is subjected to a film coating process of each thin film layer in a mold cavity, and the process temperature in the mold cavity is not higher than 190 ℃ when the film coating process of the p-type amorphous silicon layer is carried out.

Further, when the coating process of the p-type amorphous silicon layer is carried out, the process temperature in the mold cavity is 150 ~ 170 degrees.

Preferably, the intrinsic amorphous silicon layers on the opposite end surfaces of the single-crystal silicon substrate are formed by performing layer-by-layer film plating from the single-crystal silicon substrate.

Further, the intrinsic amorphous silicon layer has n layers, wherein a first layer is in contact with the monocrystalline silicon substrate, an nth layer is in contact with the p-type amorphous silicon layer and the n-type amorphous silicon layer, the ratio of hydrogen to silane in the first intrinsic amorphous silicon layer is 0:1 to 1:1, and the ratio of hydrogen to silane in the nth intrinsic amorphous silicon layer is 10:1 to 500: 1.

Further, the intrinsic amorphous silicon layer further includes one or more intermediate intrinsic amorphous silicon layers between the first intrinsic amorphous silicon layer and the nth intrinsic amorphous silicon layer, and hydrogen and silane in each of the intermediate intrinsic amorphous silicon layers are gradually transited from the first intrinsic amorphous silicon layer to the nth intrinsic amorphous silicon layer in a ratio of 1:1 ~ 10: 1.

Furthermore, the first intrinsic amorphous silicon layer is coated at a coating rate of more than 5 angstroms per second.

Furthermore, the coating rate of the n-th intrinsic amorphous silicon layer is less than 3 angstroms per second.

Further, when the intrinsic amorphous silicon layer is coated layer by layer, pure hydrogen plasma treatment is performed after the coating process is completed on each layer.

Preferably, the thickness of the intrinsic amorphous silicon layer located at the front side of the heterojunction cell is smaller than the thickness of the intrinsic amorphous silicon layer located at the back side of the heterojunction cell.

Preferably, the intrinsic amorphous silicon layer on the front side of the heterojunction cell is doped with oxygen.

Preferably, oxygen doping and/or carbon doping are/is added in the process of coating the p-type amorphous silicon layer and the n-type amorphous silicon layer, and the ratio of the oxygen doping and/or the carbon doping to silane is increased from 0:1 to 1:1.4 from the beginning of coating the p-type amorphous silicon layer and the n-type amorphous silicon layer to the end of coating.

Preferably, the heterojunction battery is subjected to a film coating process of each thin film layer in a mold cavity, and different thin film layers are subjected to film coating processes in different mold cavities respectively.

Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages: the heterojunction cell preparation method of the invention firstly carries out the film coating process of the intrinsic amorphous silicon layer contacted with the two sides of the silicon chip, and then respectively carries out the film coating process of the doped amorphous silicon layer on the intrinsic amorphous silicon layer, thereby reducing the pollution of the doped n or p type material on the surface of the silicon chip of which the other side is not coated with the intrinsic amorphous silicon layer; in addition, the p-type amorphous silicon layer is finally deposited in the preparation method, so that the process temperature of each layer of film can be better matched, and the performance of the heterojunction battery is improved.

Detailed Description

The technical solution of the present invention is further explained below.

The heterojunction cell comprises a monocrystalline silicon substrate, intrinsic amorphous silicon layers respectively arranged on two opposite end faces of the monocrystalline silicon substrate, a p-type amorphous silicon layer and an n-type amorphous silicon layer respectively arranged on the intrinsic amorphous silicon layers on the two faces, transparent conductive layers respectively arranged on the p-type amorphous silicon layer and the n-type amorphous silicon layer, and gate electrodes respectively arranged on the transparent conductive layers on the two faces.

The preparation method of the heterojunction battery comprises the following steps:

(1) preparing a monocrystalline silicon substrate, and performing texturing, cleaning and other treatment on the monocrystalline silicon substrate;

(2) performing a film coating process of an intrinsic amorphous silicon layer on one end surface of a monocrystalline silicon substrate;

(3) turning the sheet: turning the monocrystalline silicon substrate by 180 degrees;

(4) performing a film coating process of an intrinsic amorphous silicon layer on the other end surface opposite to one end surface of the monocrystalline silicon substrate;

(5) performing a film coating process on the n-type amorphous silicon layer;

(6) turning the sheet again: turning the monocrystalline silicon substrate by 180 degrees again;

(7) performing a film coating process on the p-type amorphous silicon layer;

(8) respectively carrying out a film coating process of the transparent conducting layer on the p-type amorphous silicon layer and the n-type amorphous silicon layer;

(9) and respectively printing gate electrodes on the transparent conductive layers on the two sides.

In the above process steps, the intrinsic amorphous silicon layer contacting both end surfaces of the single crystal silicon substrate is coated, and then the doped amorphous silicon layer on the intrinsic amorphous silicon layer is coated, so that the doped n-type material or p-type material can be reduced to pollute the surface of the other surface of the single crystal silicon substrate which is not coated with the intrinsic amorphous silicon layer. In addition, in the film coating process of each thin film layer, n-type materials or p-type materials are inevitably deposited on the carrier plate for loading the monocrystalline silicon substrate, so that the new monocrystalline silicon substrate can be polluted when a new monocrystalline silicon substrate enters next time, particularly, the pollution loss of the p-type materials to the new monocrystalline silicon substrate is relatively large, and after the process steps are adopted, the p-type materials can not contact the monocrystalline silicon substrate body completely, so that the pollution loss is further reduced.

In the above process, when the intrinsic amorphous silicon layer is coated on the opposite end surfaces of the single crystal silicon substrate, the intrinsic amorphous silicon layer may be formed by performing a coating process layer by layer from the end surfaces of the single crystal silicon substrate.

Specifically, the intrinsic amorphous silicon layer is provided with n layers, the n layers comprise a thin layer which is in contact with a monocrystalline silicon substrate, namely a first intrinsic amorphous silicon layer, and a thin layer which is in contact with a p-type amorphous silicon layer and an n-type amorphous silicon layer, namely an n-th intrinsic amorphous silicon layer, the first intrinsic amorphous silicon layer mainly plays a role in forming good contact with monocrystalline silicon and storing hydrogen elements as much as possible, so that a hydrogen-rich thin film layer which is prepared by adopting pure silane or a process with low hydrogen content is formed, the ratio of hydrogen to silane is 0:1 to 1:1, the n-th intrinsic amorphous silicon layer plays a role in forming good contact with an upper doped amorphous silicon film and the thin film needs to be compact enough to ensure that impurities in the doped amorphous silicon thin film cannot diffuse into the intrinsic amorphous silicon layer, so that a large amount of hydrogen is needed for film coating formation, the dense thin film layer is ensured, the ratio of hydrogen to silane is 10:1 to 500:1, the intrinsic amorphous silicon layer can also comprise one or more intrinsic thin film layers which are between the first intrinsic amorphous silicon layer and the n-th intrinsic amorphous silicon layer, namely the intrinsic amorphous silicon layer is formed by adopting a gradient mode of hydrogen, the intrinsic amorphous silicon layer and the intrinsic amorphous silicon layer is 351, and the intrinsic amorphous silicon layer is gradually changed from the intrinsic amorphous silicon layer in the intrinsic amorphous silicon layer.

After the coating process is completed on different film layers, the treatment of pure hydrogen plasma can be carried out to improve the surface quality of the film.

In one embodiment, the number n of intrinsic amorphous silicon layers is 2, the 1 st intrinsic amorphous silicon layer is prepared according to the ratio of hydrogen to silane being 0:1, then pure hydrogen plasma treatment is performed, and the 2 nd intrinsic amorphous silicon layer is prepared according to the ratio of hydrogen to silane being 10: 1.

In another embodiment, the number n of intrinsic amorphous silicon layers is 30, the ratio of hydrogen to silane is 0:1 when the 1 st layer is plated, the ratio of hydrogen to silane is 100:1 when the 30 th layer is plated, and the ratio of hydrogen to silane is continuously changed as the number of plated layers increases when the 2 nd 2 ~ 29 th layer is plated.

In the process of coating each thin film layer of the intrinsic amorphous silicon layer, the coating rate of the first intrinsic amorphous silicon layer needs to be very high, and the film prepared in this way is rich in hydrogen elements; the coating rate of the n-th intrinsic amorphous silicon layer needs to be low, and the thin film layer is compact and has low hydrogen content. In the two embodiments of the invention, the coating rate of the first intrinsic amorphous silicon layer is greater than 5 angstroms per second, and the coating rate of the n-th intrinsic amorphous silicon layer is less than 3 angstroms per second.

Preferably, the thickness of the intrinsic amorphous silicon layer on the front side of the heterojunction cell is smaller than that of the intrinsic amorphous silicon layer on the back side of the heterojunction cell, and the intrinsic amorphous silicon layer on the front side of the heterojunction cell is doped with oxygen element or other elements so as to improve the light transmission capability of the heterojunction cell.

The heterojunction cell carries out the coating process of each thin film layer in the die cavity, when carrying out the coating process of p type amorphous silicon layer, the process temperature in the die cavity is not higher than 190 degrees, the process temperature in the preferred die cavity is 150 ~ 170 degrees.

In the process of coating the p-type amorphous silicon layer and the n-type amorphous silicon layerDifferent doping concentrations or increased oxygen doping, e.g. with N, may be used₂O or CO₂Gas and or carbon doping, e.g. with CH₄And impurities such as gas and the like, wherein the ratio of oxygen doping and/or carbon doping to silane is increased from 0:1 to 1:1.4 from the beginning of film coating to the end of film coating of the p-type amorphous silicon layer and the n-type amorphous silicon layer, so that the problem that the doped gas cannot exert the due effect when the doping concentration is too high is solved.

In the film coating process of each film layer of the heterojunction battery, different film layers are subjected to film coating processes in different die cavities respectively. Therefore, the capacity of the coating equipment can be greatly improved, the cross contamination among the thin film layers can be avoided, the performance of the heterojunction battery is improved, and the cost is reduced.

The above-mentioned embodiments are merely illustrative of the technical idea and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the scope of the present invention, and all equivalent changes or modifications made according to the spirit of the present invention should be covered in the scope of the present invention.