阅读说明：本技术 动态触发器和动态触发器的与数据无关的p堆叠反馈电路 (Dynamic flip-flop and data-independent P-stack feedback circuit for dynamic flip-flop ) 是由 马修·贝尔津什 苏曼斯·苏瑞尼 于 2019-07-05 设计创作，主要内容包括：公开动态触发器和动态触发器的与数据无关的P堆叠反馈电路。本发明的方面包括包含与数据无关的P堆叠反馈电路的动态触发器。与数据无关的P堆叠反馈电路可包括：第一P型晶体管,由第一反相信号选通；以及第二P型晶体管,由反相时钟信号选通。第二P型晶体管的漏极可结合到第一P型晶体管的源极。第二P型晶体管的源极可结合到被配置为接收第二反相信号的节点。第二P型晶体管的源极可直接结合到被配置为接收第二反相信号的节点而不是恒定电源。与数据无关的P堆叠反馈电路可包括一个或多个延迟级以消除竞争条件。(Dynamic flip-flops and data-independent P-stack feedback circuits for dynamic flip-flops are disclosed. Aspects of the invention include a dynamic flip-flop including a data-independent P-stack feedback circuit. The data independent P-stack feedback circuit may include: a first P-type transistor gated by a first inversion signal; and a second P-type transistor gated by the inverted clock signal. The drain of the second P-type transistor may be coupled to the source of the first P-type transistor. The source of the second P-type transistor may be coupled to a node configured to receive the second inverted signal. The source of the second P-type transistor may be directly coupled to a node configured to receive the second inverted signal instead of the constant power supply. The data independent P-stack feedback circuit may include one or more delay stages to eliminate race conditions.)

1. A dynamic trigger, comprising:

a data independent P-stack feedback circuit comprising:

a first P-type transistor gated by a first inversion signal; and

a second P-type transistor gated by an inverted clock signal, wherein:

the drain electrode of the second P type transistor is combined to the source electrode of the first P type transistor; and is

The source of the second P-type transistor is coupled to a node configured to receive a second inverted signal.

2. The dynamic flip-flop of claim 1, wherein a source of the second P-type transistor is directly coupled to a node configured to receive the second inverted signal instead of the constant power supply.

3. The dynamic flip-flop of claim 1, wherein a drain of the second P-type transistor is directly coupled to a source of the first P-type transistor.

4. The dynamic flip-flop of claim 3, wherein the data-independent P-stack feedback circuit does not include a transistor gated by the data input signal.

5. The dynamic flip-flop of claim 1, further comprising an N-stack portion comprising an N-type transistor gated by a data input signal.

6. The dynamic flip-flop of claim 5, wherein the N-type transistor is referred to as a first N-type transistor, wherein the N-stack portion further comprises:

a second N-type transistor gated by a feedback signal;

a third N-type transistor gated by a clock signal; and

and a fourth N-type transistor gated by the first inversion signal.

7. The dynamic flip-flop of claim 6, wherein the data-independent P-stack feedback circuit further comprises:

a third P-type transistor gated by a feedback signal; and

and a fourth P-type transistor gated by the inverted clock signal.

8. The dynamic trigger of claim 7, wherein:

the node is referred to as a first node;

a drain of the first P-type transistor is coupled to a second node;

the dynamic trigger further comprises:

a fifth N-type transistor gated by the inverted clock signal and coupled to the second node; and

and a sixth N-type transistor gated by the first inversion signal and coupled to the second node.

9. The dynamic trigger of claim 8, further comprising:

a middle portion comprising:

a fifth P-type transistor gated by the feedback signal and coupled to a third node associated with the first signal; and

and a sixth P-type transistor gated by the clock signal and coupled to a third node associated with the first signal.

10. The dynamic trigger of claim 9, further comprising:

an output section including:

a seventh P-type transistor gated by the first signal;

an eighth P-type transistor gated by a clock signal;

a ninth P-type transistor gated by the second inversion signal;

a seventh N-type transistor gated by a clock signal;

an eighth N-type transistor gated by the first signal; and

and a ninth N-type transistor gated by the second inversion signal.

11. The dynamic flip-flop of claim 1, wherein the data-independent P-stack feedback circuit further comprises:

one or more delay stages disposed anywhere within the data-independent P-stack feedback circuit.

12. The dynamic flip-flop of claim 11, wherein the one or more delay stages comprise two or more inverters.

13. The dynamic flip-flop of claim 11, wherein the one or more delay stages comprises three delay stages.

14. The dynamic flip-flop of claim 11, further comprising an N-stack portion comprising a plurality of N-type transistors each gated by a respective data input signal.

15. The dynamic trigger of claim 14, wherein the N-stack portion further comprises:

a second N-type transistor gated by a feedback signal;

a third N-type transistor gated by a clock signal; and

and a fourth N-type transistor gated by the first inversion signal.

16. The dynamic flip-flop of claim 1, wherein the data-independent P-stack feedback circuit further comprises:

one or more delay stages disposed between the first and second P-type transistors.

17. A data-independent P-stack feedback circuit of a dynamic flip-flop, the data-independent P-stack feedback circuit comprising:

a first P-type transistor gated by a first inversion signal; and

a second P-type transistor gated by an inverted clock signal, wherein:

the drain electrode of the second P type transistor is combined to the source electrode of the first P type transistor; and is

The source of the second P-type transistor is coupled to a node configured to receive a second inverted signal.

18. The data-independent P-stack feedback circuit of claim 17, wherein the source of the second P-type transistor is directly coupled to a node configured to receive the second inverted signal rather than a constant power supply.

19. The data independent P-stack feedback circuit of claim 17, further comprising: one or more delay stages disposed between the first and second P-type transistors.

20. The data-independent P-stack feedback circuit of claim 19, wherein the one or more delay stages comprises three delay stages.

Technical Field

Embodiments of the present invention relate to semiconductor circuits, and more particularly, to dynamic flip-flops with data-independent P-stack feedback mechanisms that may be integrated into a single-stage combinational circuit.

Background

Conventional flip-flops are common components in many integrated circuits. In increasingly complex architectures, the scenario where multiple signals converge onto a single trigger is growing at an exponential rate. With higher frequency targets, the negative setup margin (i.e., data arriving later than the clock arrival) of the path is becoming a bottleneck in many designs. To deal with these and other growing problems, flip-flops must be fast and have setup benefits.

For example, when N: 1 Multiplexer (MUX) output to join (sticch) to flip-flop data input pin, N: the evaluation of the 1MUX is a major contributor to the setup requirements of the circuit. In one approach to improving the setup requirements, N: the 1MUX is integrated into the flip-flop. However, as the number N of inputs of the MUX becomes larger, a larger number of signals may converge into the flip-flop, and the height of the P-stack in the feedback circuit will become N + 2. In other words, P-stacks are higher and N-stacks are wider. This increases the total capacitance on the internal nodes within the circuit.

What is needed is an improved dynamic trigger with a data independent P-stack feedback mechanism.

Disclosure of Invention

Aspects of the invention include a dynamic flip-flop including a data-independent P-stack feedback circuit. The data independent P-stack feedback circuit may include: a first P-type transistor gated by a first inversion signal; and a second P-type transistor gated by the inverted clock signal. The drain of the second P-type transistor may be coupled to the source of the first P-type transistor. The source of the second P-type transistor may be coupled to a node configured to receive the second inverted signal. The source of the second P-type transistor may be directly coupled to a node configured to receive the second inverted signal instead of the constant power supply. The data independent P-stack feedback circuit may include one or more delay stages to eliminate race conditions.

Certain inventive features may best be implemented by implementing them in a processor, such as an ARM processor core. Other types of processors or Application Specific Integrated Circuits (ASICs) may implement the inventive principles disclosed herein. The inventive concepts may be implemented within the processor and/or memory modules of various mobile devices, such as smart phones, tablets, notebook computers, etc., or in various stationary devices, such as desktop computers, routers, etc.

Drawings

The foregoing and additional features and advantages of the principles of the invention will become more readily apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

fig. 1 illustrates an inverter according to some embodiments, wherein the inverter illustrates a difference between a clock signal (CK) and an inverted clock signal (CKB).

Fig. 2 is an example diagram of a dynamic trigger with a data-independent P-stack feedback mechanism according to some embodiments.

Fig. 3 is an example waveform diagram associated with a dynamic flip-flop having a data-independent P-stack feedback mechanism, according to some embodiments.

Fig. 4A illustrates a string of multiple inverters showing the difference between a clock signal (CK) and an inverted clock signal (CKB), according to some embodiments.

Fig. 4B is an example diagram of another dynamic trigger with a data-independent P-stack feedback mechanism according to some embodiments.

Fig. 5 is another example waveform diagram associated with a dynamic flip-flop having a data-independent P-stack feedback mechanism, according to some embodiments.

FIG. 6A is another example waveform diagram illustrating a pass simulation associated with a dynamic flip-flop having a data-independent P-stack feedback mechanism.

Fig. 6B is a waveform diagram illustrating a failed simulation.

FIG. 7 is an example block diagram of a computing system including a dynamic trigger with a data-independent P-stack feedback mechanism in accordance with an embodiment of the inventive concepts disclosed herein.

Detailed Description

Reference will now be made in detail to embodiments of the present inventive concept, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present inventive concepts. It will be appreciated, however, by one skilled in the art that the inventive concept may be practiced without such specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail as not to unnecessarily obscure aspects of the embodiments.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first circuit may be referred to as a second circuit, and similarly, a second circuit may be referred to as a first circuit, without departing from the scope of the inventive concept.

The terminology used herein in the description of the inventive concept is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used in the description of the inventive concept and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein indicates and includes any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The components and features of the drawings are not necessarily to scale.

Embodiments disclosed herein relate to dynamic flip-flops with data independent P-stack feedback mechanisms that may be integrated into a single stage combinational circuit. Various single stage combinational circuits can be integrated into the dynamic flip-flops disclosed herein using the data pin independent P-stack feedback mechanism described in detail below, as well as other innovative delay techniques. This may allow the circuit to operate at similar clock-to-output (CK 2Q) speeds and with similar settings for the data pins, as compared to conventional flip-flops. Since the typical N can be eliminated: the need for p-channel metal oxide semiconductor field effect transistor (PMOS) devices in 1MUX uses fewer devices and therefore requires less circuit area. By using different polygon length techniques (poly length techniques) in the circuit, leakage power can also be recovered. Better settings can be achieved even with similar CK2Q delays maintained, as compared to simply combining MUXs and flip-flops. In dense areas where routing trace availability is low, routing congestion can be improved. The complete cell can be modeled accurately, rather than relying on a wire model (wiremodel). The overall data-to-output (D2Q) benefit of using the dynamic flip-flops disclosed herein becomes more apparent as process, temperature, and supply voltage (PVT) decreases. In summary, the dynamic flip-flop disclosed herein has a better area and significantly improves the placement of the data pins than simply combining a conventional flip-flop and a combinational circuit.

Fig. 1 illustrates an inverter 102 according to some embodiments, the inverter 102 illustrating the difference between a clock signal (CK) and an inverted clock signal (CKB), as the difference relates to fig. 2. Fig. 2 is an example diagram of a dynamic flip-flop 100 having a data-independent P-stack feedback mechanism (hereinafter, also referred to as a "P-stack feedback circuit") 105 according to some embodiments. Reference is now made to fig. 1 and 2.

Dynamic flip-flop 100 may include a data independent P-stack feedback circuit 105. The data-independent P-stack feedback circuit 105 may include a first P-type transistor P1 gated by a first inversion signal ZZ1N (e.g., a first dynamic inverting network signal) that is an inversion of the first signal ZZ1 (e.g., a first dynamic inverting network signal). The data independent P-stack feedback circuit 105 may also include a second P-type transistor P2 gated by the inverted clock signal CKB. In some embodiments, the drain of the second P-type transistor P2 is coupled to the source of the first P-type transistor P1. In some embodiments, the source of the second P-type transistor P2 is coupled to the node 125, and the node 125 is configured to receive a second inverted signal ZZ2N (e.g., a second dynamic net signal) that is an inverse of the second signal ZZ2 (e.g., the second dynamic net signal).

In some embodiments, the source of the second P-type transistor P2 is coupled directly to the node 125 configured to receive the second inverted signal ZZ2N instead of a constant power supply such as VDD. In some embodiments, the drain of the second P-type transistor P2 is directly coupled to the source of the first P-type transistor P1. The data independent P-stack feedback circuit 105 need not include a transistor gated by the data input signal D.

Dynamic flip-flop 100 may also include an N-stack portion 110, N-stack portion 110 including an N-type transistor N1 gated by data input signal D. The N-stack portion may further include a second N-type transistor N2 gated by the feedback signal FB, a third N-type transistor N3 gated by the clock signal CK, and a fourth N-type transistor N4 gated by the first inversion signal ZZ 1N.

The data independent P-stack feedback circuit 105 may further include a third P-type transistor P3 gated by the feedback signal FB and a fourth P-type transistor P4 gated by the inverted clock signal CKB. In some embodiments, the drain of the first P-type transistor P1 is coupled to the node DN. The dynamic flip-flop 100 may further include a fifth N-type transistor N5 gated by the inverted clock signal CKB and coupled to the node DN. The dynamic flip-flop 100 may further include a sixth N-type transistor N6 gated by the first inverted signal ZZ1N and coupled to the node DN.

Dynamic flip-flop 100 may also include an intermediate portion 115, and intermediate portion 115 may include a fifth P-type transistor P5 gated by feedback signal FB and coupled to node 118 associated with first signal ZZ 1. The sixth P-type transistor P6 may be gated by the clock signal CK and coupled to the node 118 associated with the first signal ZZ 1. The middle portion 115 may further include an inverter 130 coupled to a fifth P-type transistor P5. In addition, an inverter 135 may be disposed between the node 118 and the fourth N-type transistor N4 of the N-stack portion 110.

The dynamic flip-flop 100 may further include an output section 120. The output section 120 may include a seventh P-type transistor P7 gated by the first signal ZZ1, an eighth P-type transistor P8 gated by the clock signal CK, a ninth P-type transistor P9 gated by the second inverted signal ZZ2N, a seventh N-type transistor N7 gated by the clock signal CK, an eighth N-type transistor N8 gated by the first signal ZZ1, and a ninth N-type transistor N9 gated by the second inverted signal ZZ 2N. Node 122 is associated with signal ZZ 2. The output section 120 may further include inverters 140 and 145.

Fig. 3 is an example waveform diagram 300 associated with a dynamic flip-flop 100 having a data-independent P-stack feedback mechanism, according to some embodiments. Reference is now made to fig. 1, 2 and 3.

In a conventional flip-flop, an additional P-type transistor is provided between the transistors P1 and P2. This additional P-type transistor disposed in the P-stack of the conventional flip-flop receives the data input signal D. By removing this additional P-type transistor from the P-stack, a race condition may occur between the evaluation path (i.e., the N-stack of the N-stack portion 110) and the feedback path, since the feedback path will now be independent of the data pin state.

However, to overcome this race condition, connecting the source of P-type transistor P2 to node 125 associated with the ZZ2N signal instead of VDD has the following effect according to embodiments disclosed herein. As shown in window 305, when clock signal CK transitions from logic 0 to logic 1 and D is logic 1, node 118 associated with the ZZ1 signal transitions from logic 1 to logic 0 due to the N-stack evaluation of N-stack portion 110; node 122 associated with the ZZ2 signal transitions from a logic 0 to a logic 1; signal ZZ2N transitions from a logic 1 to a logic 0; and the output signal QN transitions from logic 1 to logic 0. During the same period, the inverted clock signal CKB transitions from logic 1 to logic 0, and the P-type transistor P2 is turned on.

Due to V_GS＝V_CKBMinus V_ZZ2N(Here, V)_GSRepresenting the gate voltage V of the P-type transistor P2_CKBAnd source voltage V_ZZ2NThe difference between) in this case, 0 minus 0 is 0, which is smaller than V of PMOS_TH(Here, V)_THRepresenting the threshold voltage for turning on the PMOS) and thus the P-type transistor P2 is turned off and the feedback P stack is turned off. Therefore, P-stack can no longer lead to a race condition with the evaluation of N-stack. In other words, the faster the node 125 associated with signal ZZ2N is pulled to zero, the faster the feedback P-stack turns off.

When the clock signal CK is logic 0, the node 118 associated with the signal ZZ1 is pulled to logic 1, or in other words, is precharged. As shown in window 310, when data input D is a logic 0, and clock signal CK transitions from a logic 0 to a logic 1, then signal ZZ2N transitions from a logic 0 to a logic 1; node DN transitions from logic 0 to logic 1; the feedback signal FB transitions from logic 1 to logic 0 and the output signal QN transitions from logic 0 to logic 1.

Fig. 4A illustrates a string of multiple inverters showing the difference between a clock signal (CK) and an inverted clock signal (CKB), according to some embodiments. Fig. 4B is an example diagram of another dynamic trigger 400 with a data-independent P-stack feedback mechanism according to some embodiments. Some of the components of dynamic flip-flop 400 are the same as or similar to those of dynamic flip-flop 100, and the description of these components need not be repeated for the sake of brevity. Reference is now made to fig. 4A and 4B.

N: the 1 Multiplexer (MUX) may be integrated with a dynamic flip-flop 400 having a data independent P-stack feedback mechanism. With N: the "N" increase in the 1MUX, N of N-stack portion 410: the parallel 2-depth N-stack (2-deep N-stack) of the 1MUX adds extra capacitance on node 118 associated with signal ZZ1, which may slow down the transition of the ZZ1 signal from logic 1 to logic 0. In addition, the transition of the ZZ2 signal from logic 0 to logic 1 and the transition of the ZZ2N signal from logic 1 to logic 0 may also be slowed. Due to the slowed ZZ2N transition from logic 1 to logic 0, the feedback loop may use the evaluation of the N-stack of N-stack portion 410 to begin the race condition.

To eliminate any contention between the evaluation of the N-stack portion 410 and the feedback P-stack of the data-independent P-stack feedback circuit 405, various design techniques (e.g., different VT injections, longer polygon lengths, longer feedback P-stack, delaying the inverted clock signal CKB transition using multiple delay stages between the clock signal CK and the inverted clock signal CKB, etc.) may be used to slow down the non-critical feedback P-stack. Thus, P-stacking may be slowed down and leakage power may be reduced.

Dynamic flip-flop 400 may include a data independent P-stack feedback circuit 405, an intermediate circuit 415, an N-stack portion 410, and an output portion 420. In some embodiments, the data independent P-stack feedback circuit 405 includes one or more delay stages 435 disposed anywhere within the P-stack in 405. For example, one or more delay stages 435 may be disposed above or below P1. As another example, one or more delay stages 435 may be disposed above or below P2. As another example, one or more delay stages 435 may be disposed between P1 and P2. The non-critical feedback P-stack may be slowed down using various design techniques described above. In some embodiments, one or more delay stages 435 include two or more inverters. In some embodiments, a first inverter of the two or more inverters is coupled to a source of the first P-type transistor P1, and a second inverter of the two or more inverters is coupled to a drain of the second P-type transistor P2. In some embodiments, the one or more delay stages 435 include three delay stages.

The N-stack portion 410 may include a plurality of N-type transistors (e.g., N1a, N4a through NAn), each gated by a data input signal (e.g., a0, a1 through AN). The N-stack portion 410 may include a plurality of N-type select transistors (e.g., N1b, N4 b-NSn), each gated by a select signal (e.g., S0, S1-SN). The N-stack portion 410 may further include an N-type transistor N2 gated by the feedback signal FB, an N-type transistor N3 gated by the clock signal CK, and an N-type transistor N4 gated by the first inversion signal ZZ 1N.

Fig. 5 is another example waveform diagram 500 associated with a dynamic flip-flop 400 having a data-independent P-stack feedback mechanism, according to some embodiments. Reference is now made to fig. 4A, 4B and 5.

When the clock signal CK is logic 0, the node 118 associated with the signal ZZ1 is pulled to logic 1, or in other words, it is precharged. As shown in window 510, with all MUX inputs A [0 … N-1] set to logic 0, when clock signal CK transitions from logic 0 to logic 1, output signal QN transitions from logic 0 to logic 1.

Considering the case where the MUX input A [0 … … N-1] transitions from logic 0 to logic 1, the select signal S0[0 … … N-1] transitions from logic 0 to logic 1, and the clock signal CK is at logic 0. A and S0 may be input buses each having N bits. In the waveform shown in fig. 5, only one input a and the corresponding selection signal S0 are drawn as an example. In practice, there may be a plurality of inputs A [0 … … N-1] and a plurality of corresponding select signals S0[0 … … N-1 ]. When clock signal CK transitions from logic 0 to logic 1, the NMOS stack evaluation of N-stack portion 410 pulls node 118 associated with signal ZZ1 from logic 1 to logic 0, and thus, as shown in window 505, output signal QN transitions from logic 1 to logic 0. The data independent P-stack feedback circuit 405 eliminates any race condition within the circuit.

FIG. 6A is another example waveform diagram 600 illustrating a pass condition (past condition) associated with a dynamic trigger having a data-independent P-stack feedback mechanism. Window 605 is similar to window 510 of fig. 5. Fig. 6B is a waveform diagram 602 illustrating a failed simulation 610 in the case where race conditions are not mitigated. As disclosed herein, the data independent P-stack feedback circuit 405 eliminates any race condition within the circuit such that the fail condition 610 does not occur.

Thus, various single-stage combinational circuit elements can be integrated into a dynamic flip-flop with P-stack feedback and inventive delay techniques that are independent of the data pin. This allows the circuit to operate at similar or better speeds (CK to Q) and with similar or better settings for the data pins than conventional dynamic flip-flops. The result is a better area and a significant improvement in the placement of the data pins than simply combining the combinatorial circuit with a conventional dynamic flip-flop. The area benefit is due to the elimination of the typical N: there is a need for PMOS devices in the 1MUX while using fewer devices. Leakage power may also be recovered by using mixed VT and different polygon length techniques within the circuit. Better setup is achieved than simply combining a MUX with a dynamic flip-flop with a similar CK2Q delay. Routing congestion is improved in dense areas where routing trace availability is very low. Furthermore, the complete cell is accurately modeled, rather than relying on a line model.

FIG. 7 is an example block diagram of a computing system including a dynamic trigger 100/400 with a data-independent P-stack feedback mechanism 105/405 in accordance with an embodiment of the inventive concepts as disclosed herein. A dynamic flip-flop 100/400 as disclosed herein may be electrically connected to the system bus 705. Computing system 700 may also include a clock 710, Random Access Memory (RAM) and/or flash memory 715, a memory controller 745, a user interface 720, a modem 725 (such as a baseband chipset), and/or Automatic Test Equipment (ATE)735, any or all of which may be electrically coupled to system bus 705.

If computing system 700 is a mobile device, it may also include a battery 740 to power computing system 700. Although not shown in fig. 7, the computing system 700 may also include an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. The memory controller 745 and the RAM and/or flash memory 715 may constitute a solid state drive/disk (SSD) that uses non-volatile memory to store data.

In example embodiments, the computing system 700 may be used as a computer, a portable computer, an ultra mobile pc (umpc), a workstation, a netbook, a PDA, a web tablet, a wireless phone, a mobile phone, a smart phone, an electronic book, a PMP (portable multimedia player), a digital camera, a digital audio recorder/player, a digital image/video recorder/player, a portable game machine, a navigation system, a black box, a three-dimensional television, a device capable of transmitting and receiving information under a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computing network, one of various electronic devices constituting a telematics network, an RFID, or one of various electronic devices constituting a computing system.

The various operations of the methods described above may be performed by any suitable means such as various hardware and/or software components, circuits, and/or modules capable of performing the described operations.

The blocks or steps of the methods or algorithms and functions described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a tangible, non-transitory computer-readable medium. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), registers, hard disk, a removable disk, a CD ROM, or any other form of storage medium known in the art.

The following discussion is intended to provide a brief, general description of one or more suitable machines in which certain aspects of the present inventive concepts may be implemented. Typically, one or more machines include a system bus to which a processor, memory (e.g., RAM, ROM, or other state-preserving medium), storage devices, video interfaces, and input/output interface ports are connected. One or more machines may be controlled, at least in part, by input from conventional input devices, such as keyboards, mice, etc., as well as by instructions received from another machine, interaction with a Virtual Reality (VR) environment, biometric feedback, or other input signals. As used herein, the term "machine" is intended to broadly encompass a single machine, a virtual machine, or a system of communicatively coupled machines, virtual machines, or devices operating together. Exemplary machines include computing devices (such as personal computers, workstations, servers, portable computers, handheld devices, telephones, tablets, etc.) and transportation devices (such as private or public transportation vehicles (e.g., cars, trains, taxis, etc.)).

One or more machines may include embedded controllers (such as programmable or non-programmable logic devices or arrays, Application Specific Integrated Circuits (ASICs), embedded computers, smart cards, etc.). One or more machines may utilize one or more connections to one or more remote machines, such as through a network interface, modem, or other communicative coupling. The machines may be interconnected by a physical and/or logical network, such as an intranet, the internet, a local area network, a wide area network, etc. Those skilled in the art will appreciate that network communications may utilize a variety of wired and/or wireless short-range or long-range carriers and protocols, including Radio Frequency (RF), satellite, microwave, Institute of Electrical and Electronics Engineers (IEEE)545.11, bluetooth, optical, infrared, cable, laser, etc.

Embodiments of the inventive concept may be described by reference to or in conjunction with associated data including functions, procedures, data structures, application programs, etc., which when accessed by a machine results in the machine performing tasks or defining abstract data types or low-level hardware contexts. For example, the associated data may be stored in volatile and/or non-volatile memory (e.g., RAM, ROM, etc.) or in other storage devices and their associated storage media (including hard drives, floppy disks, optical storage, tapes, flash memory, memory sticks, digital video disks, biological storage, etc.). The associated data may be transmitted over transmission environments including physical and/or logical networks in the form of packets, serial data, parallel data, propagated signals, etc., and may be used in a compressed or encrypted format. The associated data may be used in a distributed environment and stored locally and/or remotely for machine access.

Having described and illustrated the principles of the inventive concept with reference to illustrated embodiments, it will be recognized that the illustrated embodiments can be modified in arrangement and detail, and can be combined in any desired manner, without departing from such principles. Although the foregoing discussion has focused on particular embodiments, other configurations are also contemplated. In particular, even though expressions such as "embodiments according to the inventive concept" or the like are used herein, these phrases are meant to generally refer to embodiment possibilities and are not intended to limit the inventive concept to particular embodiment configurations. As used herein, these terms may refer to the same or different embodiments that are combinable into other embodiments.

Embodiments of the inventive concepts may include a non-transitory machine-readable medium comprising instructions executable by one or more processors, the instructions including instructions for performing the elements of the inventive concepts described herein.

The above illustrative embodiments should not be construed as limiting the inventive concept thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in those embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims.