阅读说明：本技术 一种支持写暗示的硬件高速缓存数据装入方法 (Hardware cache data loading method supporting write hint ) 是由 过锋 陈芳园 高红光 吴珊 赵冠一 孙红辉 陈正博 于 2019-09-11 设计创作，主要内容包括：本发明包括下述步骤：S1、确定需要目标主存的主存数据行的地址信息,该地址信息由写暗示指令携带；S2、通过CPU向目标Cache发出写暗示指令,所述写暗示指令生成写暗示标记,并且将要携带的目标主存的主存数据行地址映射为目标Cache中的缓存行；S3、判断映射的目标Cache中对应的缓存行是否访问命中；S4、确定映射的目标Cache中对应的缓存行命中,则判断缓存行是否有效；S5、确定缓存行有效时,则将该缓存行淘汰回主存；S6、设置缓存行有效,并结束处理,后续对写暗示装入的缓存行进行访问时,按照正常的高速缓存访问方式进行。本发明通过在硬件高速缓存中直接占用缓存行,而不读取并装入对应的主存行,显著降低缓存行第一次访问主存的延迟。(The invention comprises the following steps: s1, determining the address information of main memory data lines needing target main memory, wherein the address information is carried by the write hint instruction; s2, sending a write hint instruction to the target Cache through the CPU, wherein the write hint instruction generates a write hint mark and maps a main memory data line address of a target main memory to be carried into a Cache line in the target Cache; s3, judging whether the corresponding Cache line in the mapped target Cache is accessed and hit; s4, determining whether the corresponding Cache line in the mapped target Cache is hit, and judging whether the Cache line is effective; s5, when the cache line is determined to be valid, the cache line is eliminated back to the main memory; and S6, setting the cache line to be effective, finishing the processing, and performing the subsequent access to the cache line loaded by the write hint according to a normal cache access mode. The invention directly occupies the cache line in the hardware cache, and does not read and load the corresponding main memory line, thereby obviously reducing the delay of the cache line accessing the main memory for the first time.)

1. A hardware Cache data loading method supporting write hint is characterized in that the method is used for improving the reading and writing speed of the Cache data loaded into a main memory for the first time, and comprises the following steps: s1, determining the address information of main memory data lines needing target main memory, wherein the address information is carried by the write hint instruction; s2, sending a write hint instruction to the target Cache through the CPU, wherein the write hint instruction generates a write hint mark and maps a main memory data line address of a target main memory to be carried into a Cache line in the target Cache; s3, judging whether the corresponding Cache line in the mapped target Cache is accessed and hit; s4, determining whether the corresponding Cache line in the mapped target Cache is hit, and judging whether the Cache line is effective; s5, when the cache line is determined to be valid, the cache line is eliminated back to the main memory; and S6, setting the cache line to be effective, finishing the processing, and performing the subsequent access to the cache line loaded by the write hint according to a normal cache access mode.

2. A method of hardware cache data loading with support for write hints according to claim 1, wherein: in step S1, the main memory data line of the target main memory is a data unit having the same size as the Cache line of the target Cache, and the address information of the target main memory written to imply instruction pickup may be any address position in the main memory data line.

3. A method of hardware cache data loading with support for write hints according to claim 1, wherein: the address information of the target main memory to be mapped in step S2 is the start address of the main memory line where the address is located, and since the main memory data line of the target main memory and the Cache line of the target Cache have the same size, the address of the target Cache to be mapped is also the start address of the Cache line.

4. A method of hardware cache data loading with support for write hints according to claim 1, wherein: the step S3 of "determining whether the corresponding Cache line in the mapped target Cache is hit by access" specifically includes: s31, reading Tag content of a Tag domain corresponding to the mapping Cache line by the target Cache; s32, comparing the content of the action address in the Tag with the initial address of the main memory data line of the target main memory; s33, when the two addresses are determined to be the same and the Cache line marked in the Tag is valid, the Cache line of the mapped target Cache is judged to be hit.

5. The method for loading data into the hardware cache memory supporting the write hint as claimed in claim 1, wherein the step S4 "determining whether the cache line is valid" is specifically: and reading the data of the valid bit of the data of the buffer line, further judging whether the cache line data exists according to the mark of the valid bit, and if the mark of the valid bit exists, indicating that the data of the buffer line exists and the cache line is valid.

6. The method for loading data into the hardware cache memory according to claim 1, wherein the step S6 "proceeding according to the normal cache access manner" means that the subsequent write operation to the cache line is marked by using a fine-grained write mask manner, that is, the write data is first updated to the corresponding position of the cache line, and the write mask is updated according to the data granularity.

7. A method of hardware cache data loading with support for write hints according to claim 6, wherein: when the cache line is explicitly or implicitly eliminated back to the main memory, the hardware cache device provides the cache line to update the corresponding write mask, so as to ensure the consistency of data access.

Technical Field

The invention relates to the field of computer storage systems, in particular to a hardware cache data loading method supporting write hint.

Background

With the great improvement of the computing power of the processor, the slow memory access capability of the chip is improved to become an important factor for restricting the performance of the chip. Hardware Cache (Cache) devices are an important technical approach to improve data access performance with spatial and temporal locality.

At present, the size of a cache is one of important indexes of a CPU, and the structure and the size of the cache have great influence on the speed of the CPU. In short, the cache is used for storing some commonly used or to-be-used data or instructions, and when the data or instructions are needed, the data or instructions are directly read from the cache, so that the data or instructions are much faster than the data or instructions read from a memory or even a hard disk, and the processing speed of a CPU (central processing unit) can be greatly improved.

The existing hardware cache has longer delay when the data is loaded into the main memory for the first time, and the generated data dependency has larger influence on the performance of a subsequent instruction pipeline. Especially for the main memory write access which does not care the original data content, unnecessary first access delay is brought, so that a large amount of data read-write time is wasted, and unnecessary performance loss is caused.

Therefore, there is a need for a hardware cache data loading method supporting write hints, which can significantly reduce the delay of the cache line accessing the main memory for the first time by directly occupying the cache line in the hardware cache without actually reading and loading the corresponding main memory line for the main memory write access that does not care about the original data content, thereby improving the actual operating performance of the application.

Disclosure of Invention

In order to solve the above problems, the technical solution adopted by the present invention is to provide a hardware cache data loading method supporting write hint, which is used for regulating and controlling the reading and writing of a cache memory and a main memory by a CPU, thereby reducing the delay of the cache line accessing the main memory for the first time.

The hardware cache data loading method supporting the write hint comprises the following steps: s1, determining the address information of main memory data lines needing target main memory, wherein the address information is carried by the write hint instruction; s2, sending a write hint instruction to the target Cache through the CPU, wherein the write hint instruction generates a write hint mark and maps a main memory data line address of a target main memory to be carried into a Cache line in the target Cache; s3, judging whether the corresponding Cache line in the mapped target Cache is accessed and hit; s4, determining whether the corresponding Cache line in the mapped target Cache is hit, and judging whether the Cache line is effective; s5, when the cache line is determined to be valid, the cache line is eliminated back to the main memory; and S6, setting the cache line to be effective, finishing the processing, and performing the subsequent access to the cache line loaded by the write hint according to a normal cache access mode.

Further, in step S1, the main memory data line of the target main memory is a data unit with the same size as the Cache line of the target Cache, and the address information of the target main memory written to imply that the instruction is picked up may be any address location within the main memory data line.

Further, the address information of the target main memory mapped in step S2 is the starting address of the main memory line where the address is located, and since the main memory data line of the target main memory and the Cache line of the target Cache have the same size, the address of the target Cache mapped is also the starting address of the Cache line.

Further, the step S3 of "determining whether the Cache line corresponding to the mapped target Cache is hit by access" specifically includes: s31, reading out the label domain (Tag) content corresponding to the mapping Cache line by the target Cache; s32, comparing the content of the action address in the Tag with the initial address of the main memory data line of the target main memory; s33, when the two addresses are determined to be the same and the Cache line marked in the Tag is valid, the Cache line of the mapped target Cache is judged to be hit.

Further, in step S4, "determine whether the cache line is valid" specifically includes: and reading the data of the valid bit of the data of the buffer line, further judging whether the cache line data exists according to the mark of the valid bit, and if the mark of the valid bit exists, indicating that the data of the buffer line exists and the cache line is valid.

Further, the step S6, "proceed according to the normal cache access manner" means that the write operation on the cache line is marked by using a fine-grained write mask manner, that is, the write data is updated to the corresponding position of the cache line first, and the write mask is updated according to the data granularity.

Further, when the cache line is explicitly or implicitly eliminated back to the main memory, the hardware cache device provides the corresponding write mask for updating the cache line, and the consistency of data access is ensured.

The data writing into the Cache line of the Cache ensures the consistency of data access by a write mask mode. Meanwhile, when the cache line is explicitly or implicitly eliminated back to the main memory, the hardware cache device provides the write mask corresponding to the cache line update, and the consistency of data access is ensured. The invention carries out the write hint operation by the CPU accessing the write hint interface in the Cache controller, thereby facilitating the adjustment of the write hint process according to the application requirement. The invention can directly occupy the cache line in the hardware cache without actually reading and loading the corresponding main memory line, thereby obviously reducing the delay of the cache line for accessing the main memory for the first time and optimizing the application performance of the cache memory acted by the invention.

Drawings

FIG. 1 is a general flow diagram of a hardware cache data loading method supporting write hints according to the present invention;

FIG. 2 is a flowchart illustrating sub-steps of step S3 of a hardware cache data loading method supporting write hints according to the present invention.

Detailed Description

In order to more clearly illustrate the embodiments of the present invention and/or the technical solutions in the prior art, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.