阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 赵猛 于 2018-07-12 设计创作，主要内容包括：一种半导体结构及其形成方法,所述方法包括：提供基底,基底包括衬底以及凸出于衬底的鳍部,基底用于形成NMOS晶体管；形成横跨鳍部的栅极结构,栅极结构覆盖鳍部的部分顶部和部分侧壁；在栅极结构两侧的鳍部内形成第一防扩散掺杂区,掺杂离子包括Ga离子；在栅极结构两侧的鳍部内形成源漏掺杂区,沿垂直于栅极结构侧壁的方向,源漏掺杂区与第一防扩散掺杂区相邻且位于第一防扩散掺杂区远离栅极结构的一侧。本发明第一防扩散掺杂区的掺杂离子包括Ga离子,掺杂Ga离子有利于保证第一防扩散掺杂区位于源漏掺杂区和沟道区之间的鳍部内,因此可有效抑制源漏掺杂区的掺杂离子向沟道区发生横向扩散并减小沟道漏电流,进而提高半导体结构的电学性能。(A semiconductor structure and method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, and the substrate is used for forming an NMOS (N-channel metal oxide semiconductor) transistor; forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers part of the top and part of the side wall of the fin part; forming first diffusion-preventing doped regions in the fin parts on two sides of the grid structure, wherein the doped ions comprise Ga ions; and forming source and drain doped regions in the fin parts on two sides of the grid structure, wherein the source and drain doped regions are adjacent to the first diffusion-preventing doped region and are positioned on one side of the first diffusion-preventing doped region far away from the grid structure along the direction vertical to the side wall of the grid structure. The doped ions of the first diffusion-preventing doped region comprise Ga ions, and the Ga ions are doped to be beneficial to ensuring that the first diffusion-preventing doped region is positioned in the fin part between the source drain doped region and the channel region, so that the doped ions of the source drain doped region can be effectively inhibited from diffusing transversely to the channel region, the channel leakage current is reduced, and the electrical property of the semiconductor structure is improved.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, and the substrate is used for forming an NMOS transistor;

forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers part of the top and part of the side wall of the fin part;

forming first diffusion-preventing doped regions in fin parts on two sides of the grid structure, wherein doped ions in the first diffusion-preventing doped regions comprise Ga ions;

and forming source and drain doped regions in the fin parts on two sides of the grid structure, wherein the source and drain doped regions are adjacent to the first diffusion-preventing doped region and are positioned on one side of the first diffusion-preventing doped region far away from the grid structure along the direction vertical to the side wall of the grid structure.

2. The method as claimed in claim 1, wherein in the step of forming the first anti-diffusion doped region in the fin portion at two sides of the gate structure, the doping ions in the first anti-diffusion doped region are Ga ions; or, the doping ions In the first diffusion-preventing doping region are Ga ions and In ions.

3. The method of claim 1, wherein before forming the first anti-diffusion doped regions in the fin on both sides of the gate structure, further comprising: removing the fin parts on two sides of the grid structure, and forming grooves exposing the substrate in the fin parts on two sides of the grid structure;

the step of forming source-drain doped regions in the fin portions on the two sides of the grid structure comprises the following steps: and forming the source drain doped region in the groove.

4. The method of claim 3, wherein the step of forming the first anti-diffusion doped region in the fin portion at two sides of the gate structure comprises: and carrying out first ion doping treatment on the side wall of the groove close to one side of the gate structure, and forming the first diffusion-preventing doped region in the side wall of the fin part exposed out of the groove.

5. The method for forming a semiconductor structure according to claim 4, wherein after the first ion doping treatment is performed on the sidewall of the recess close to the side of the gate structure, before the source-drain doped region is formed in the recess, the method further comprises: carrying out second ion doping treatment on the side wall of one side, close to the grid structure, of any one groove, and forming a second diffusion-preventing doped region in the first diffusion-preventing doped region on the side wall of the groove, wherein doped ions of the second ion doping treatment comprise Ga ions;

in the step of forming the source-drain doped region in the fin portion on the two sides of the gate structure, the source-drain doped region in the fin portion on one side of the gate structure is a source region, the source-drain doped region in the fin portion on the other side of the gate structure is a drain region, and the source region is adjacent to the second diffusion-preventing doped region.

6. The method of claim 4, wherein the first ion doping process is an ion implantation process, and the parameters of the first ion doping process comprise: the implanted ions are Ga ions, the implantation energy is 15KeV to 45KeV, the implantation dose is 1E13 atoms per square centimeter to 5E13 atoms per square centimeter, and the implantation angle is 15 degrees to 35 degrees;

alternatively, the first and second electrodes may be,

the implantation energy of Ga ions is 15KeV to 45KeV, the implantation dosage of Ga ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, the implantation energy of In ions is 25KeV to 45KeV, the implantation dosage of In ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the implantation angle is 15 degrees to 35 degrees.

7. The method of claim 5, wherein the dopant ions of the second ion doping process are Ga ions;

alternatively, the first and second electrodes may be,

and the doping ions of the second ion doping treatment are Ga ions and In ions.

8. The method of claim 5, wherein the second ion doping process is an ion implantation process, and the parameters of the second ion doping process comprise: the implanted ions are Ga ions, the implantation energy is 5KeV to 35KeV, the implantation dose is 1E13 atoms per square centimeter to 5E13 atoms per square centimeter, and the implantation angle is 15 degrees to 35 degrees;

alternatively, the first and second electrodes may be,

the implantation energy of Ga ions is 5KeV to 35KeV, the implantation dosage of Ga ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, the implantation energy of In ions is 15KeV to 35KeV, the implantation dosage of In ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the implantation angle is 15 degrees to 35 degrees.

9. The method of forming a semiconductor structure of claim 5, further comprising, after the first ion doping process and before the second ion doping process: removing part of the thickness substrate at the bottom of the groove, wherein the substrate removal amount at the bottom of the groove is a first thickness; after the second ion doping treatment, before forming the source-drain doped region in the groove, the method further includes: removing part of the thickness substrate at the bottom of the groove, wherein the substrate removal amount at the bottom of the groove is a second thickness;

alternatively, the first and second electrodes may be,

after the second ion doping treatment, before forming a source-drain doped region in the groove, the method further includes: and removing part of the thickness substrate at the bottom of the groove, wherein the substrate removal amount at the bottom of the groove is a third thickness.

10. The method of forming a semiconductor structure of claim 9, wherein removing a portion of the thickness of the substrate at the bottom of the recess comprises: and etching the substrate at the bottom of the groove by adopting a dry etching process.

11. The method of claim 9, wherein the first thickness is 30nm to 50nm, the second thickness is 5nm to 15nm, and the third thickness is 35nm to 65 nm.

12. The method for forming a semiconductor structure according to claim 3, wherein the step of forming the source and drain doped regions in the recess comprises: forming a first epitaxial layer on the bottom and the side wall of the groove, and performing first in-situ self-doping in the process of forming the first epitaxial layer to form a bottom source drain doping layer;

and forming a second epitaxial layer covering the bottom source-drain doping layer in the groove, and performing second in-situ self-doping in the process of forming the second epitaxial layer to form a top source-drain doping layer, wherein the concentration of doped ions in the top source-drain doping layer is greater than that of doped ions in the bottom source-drain doping layer.

13. A semiconductor structure, comprising:

the substrate comprises a substrate and a fin part protruding out of the substrate, wherein an NMOS transistor is formed on the substrate;

the grid electrode structure stretches across the fin part and covers part of the top and part of the side wall of the fin part;

the first diffusion-preventing doped region is positioned in the fin parts at two sides of the grid structure, and doped ions of the first diffusion-preventing doped region comprise Ga ions;

and the source-drain doped region is positioned in the fin parts at two sides of the grid structure, is adjacent to the first diffusion-preventing doped region and is positioned at one side of the first diffusion-preventing doped region far away from the grid structure along the direction vertical to the side wall of the grid structure.

14. The semiconductor structure of claim 13, wherein the dopant ions of the first diffusion-preventing doped region are Ga ions; or, the doping ions of the first diffusion-preventing doping region are Ga ions and In ions.

15. The semiconductor structure of claim 13, wherein the first diffusion-preventing doped region has a doping concentration of Ga ions of 1E18 atoms per cubic centimeter to 5E18 atoms per cubic centimeter, and a depth of 10nm to 30nm in a direction perpendicular to the sidewalls of the gate structure;

alternatively, the first and second electrodes may be,

the first diffusion-preventing doping region is formed by doping ions of Ga ions and In ions, the doping concentration of the Ga ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter, the doping concentration of the In ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter, and the depth of the first diffusion-preventing doping region is 10nm to 30nm along the direction perpendicular to the side wall of the grid structure.

16. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises:

the groove is positioned in the fin parts at two sides of the grid structure, and the substrate is exposed at the bottom of the groove;

the first diffusion-preventing doped region is positioned in the fin part of the side wall of the groove close to one side of the grid structure;

the source and drain doped regions are located in the grooves.

17. The semiconductor structure of claim 16, wherein the source drain doped region in the fin on one side of the gate structure is a source region and the source drain doped region in the fin on the other side of the gate structure is a drain region;

the semiconductor structure further includes: and the second diffusion-preventing doped region is positioned on one side of the grid structure, the second diffusion-preventing doped region is positioned in the first diffusion-preventing region on the side wall of the groove, and the doped ions of the second diffusion-preventing doped region comprise Ga ions.

18. The semiconductor structure of claim 17, wherein the dopant ions of the second diffusion-preventing doped region are Ga ions; or, the doping ions of the second diffusion-preventing doping region are Ga ions and In ions.

19. The semiconductor structure of claim 17, wherein the second diffusion-preventing doped region has a doping concentration of Ga ions of 1E18 atoms per cubic centimeter to 5E18 atoms per cubic centimeter, and a depth of 3nm to 20nm in a direction perpendicular to the sidewalls of the gate structure;

alternatively, the first and second electrodes may be,

the doping ions of the second diffusion-preventing doping region are Ga ions and In ions, the doping concentration of the Ga ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter, the doping concentration of the In ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter, and the depth of the second diffusion-preventing doping region is 3nm to 20nm along the direction perpendicular to the side wall of the grid structure.

20. The semiconductor structure of claim 16, wherein the source and drain doped regions are further located within a portion of the thickness of the substrate at the bottom of the recess.

21. The semiconductor structure of claim 20, wherein a distance from a bottom of the source drain doped region to a top of the substrate is 35nm to 65 nm.

22. The semiconductor structure of claim 16, wherein the source drain doped region comprises:

the bottom source drain layer is positioned at the bottom and the side wall of the groove;

and the top source-drain doping layer is positioned in the groove and covers the bottom source-drain doping layer, and the concentration of doped ions in the top source-drain doping layer is greater than that in the bottom source-drain doping layer.

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the gradual development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. To accommodate the reduction in process node, the channel length of the MOSFET has to be shortened. The reduction in channel length has the benefits of increasing the die density of the chip, increasing the switching speed of the MOSFET, etc.

However, as the length of the channel of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate to the channel is deteriorated, so that a sub-threshold leakage (short-channel leakage) phenomenon, i.e., so-called SCE (short-channel leakage) is more likely to occur, and the channel leakage current of the transistor is increased.

In order to reduce the influence of the short channel effect on the semiconductor device and reduce the channel leakage current, an ultra-shallow junction technology is developed, the ultra-shallow junction can better improve the short channel effect of the device, but with the continuous reduction of the size of the device and the continuous improvement of the performance requirement, the junction leakage current phenomenon becomes a problem to be solved urgently by the ultra-shallow junction technology.

Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFETs to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.

However, even with the introduction of FinFET structures in ultra-shallow junction technology, the electrical performance of prior art semiconductor structures is still to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can optimize the electrical performance of the semiconductor structure.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, and the substrate is used for forming an NMOS transistor; forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers part of the top and part of the side wall of the fin part; forming first diffusion-preventing doped regions in fin parts on two sides of the grid structure, wherein doped ions in the first diffusion-preventing doped regions comprise Ga ions; and forming source and drain doped regions in the fin parts on two sides of the grid structure, wherein the source and drain doped regions are adjacent to the first diffusion-preventing doped region and are positioned on one side of the first diffusion-preventing doped region far away from the grid structure along the direction vertical to the side wall of the grid structure.

Accordingly, the present invention also provides a semiconductor structure comprising: the substrate comprises a substrate and a fin part protruding out of the substrate, wherein an NMOS transistor is formed on the substrate; the grid electrode structure stretches across the fin part and covers part of the top and part of the side wall of the fin part; the first diffusion-preventing doped region is positioned in the fin parts at two sides of the grid structure, and doped ions of the first diffusion-preventing doped region comprise Ga ions; and the source-drain doped region is positioned in the fin parts at two sides of the grid structure, is adjacent to the first diffusion-preventing doped region and is positioned at one side of the first diffusion-preventing doped region far away from the grid structure along the direction vertical to the side wall of the grid structure.

Compared with the prior art, the technical scheme of the invention has the following advantages:

forming first diffusion-preventing doped regions in fin parts on two sides of the grid electrode structure, wherein doped ions in the first diffusion-preventing doped regions comprise Ga ions; forming source and drain doped regions in the fin parts on two sides of the grid structure, wherein the source and drain doped regions are adjacent to the first diffusion-preventing doped region and are positioned on one side of the first diffusion-preventing doped region far away from the grid structure along the direction perpendicular to the side wall of the grid structure; compared with common P-type ions (such as B ions), under the same ion implantation depth, the transverse diffusion distance of the Ga ions in the semiconductor is at least two times lower, so that the region and the depth of ion implantation can be better controlled by using the Ga ions, a local high-doped region is formed, and steep doping concentration is obtained, so that the first diffusion-preventing doped region is favorably ensured to be positioned in a fin part between a source-drain doped region and a channel, the transverse diffusion of the doped ions of the source-drain doped region to the channel region can be effectively inhibited, the transverse punch-through of the source-drain doped region and the channel region is prevented, the channel leakage current is favorably reduced, the short channel problem is improved, the Ga ions are also favorable for improving DIBL, the device gain is improved, and the electrical performance of the semiconductor structure is improved.

In an alternative scheme, the doped ions for performing the first ion doping treatment In the fin parts at two sides of the grid electrode structure are In ions and Ga ions; in ions and Ga ions belong to the same group of elements and have similar electrical properties, and In ions are commonly used doping ions In a semiconductor structure, so that the process stability is improved by doping In ions.

Optionally, before forming the first diffusion-preventing doped regions in the fin portions on both sides of the gate structure, the method for forming the semiconductor structure further includes: removing the fin parts on two sides of the grid structure, and forming grooves exposing the substrate in the fin parts on two sides of the grid structure; the first diffusion-preventing doping layer is located in the whole side wall of the fin portion, and therefore the effect that the first diffusion-preventing doping region is used for preventing the source drain doping region and the channel region from being transversely penetrated through is further enhanced.

In an alternative, after the first ion doping treatment is performed on the sidewall of the groove close to one side of the gate structure, before forming a source-drain doped region in the fin portions on both sides of the gate structure, the method further includes: and carrying out second ion doping treatment on the side wall of one side, close to the grid structure, of any groove, forming a second diffusion-preventing doped region in the first diffusion-preventing doped region of the side wall of the groove, wherein the doped ions subjected to the second ion doping treatment comprise Ga ions, and a source drain doped region adjacent to the second diffusion-preventing doped region is used as a source region.

Drawings

Fig. 1 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As is known in the art, the electrical performance of semiconductor structures is still to be improved after the introduction of FinFET structures.

In order to solve the technical problem, a first diffusion-preventing doped region is formed in fin parts on two sides of a grid structure, and doped ions in the first diffusion-preventing doped region comprise Ga ions; forming source and drain doped regions in the fin parts on two sides of the grid structure, wherein the source and drain doped regions are adjacent to the first diffusion-preventing doped region and are positioned on one side of the first diffusion-preventing doped region far away from the grid structure along the direction perpendicular to the side wall of the grid structure; compared with common P-type ions (such as B ions), under the same ion implantation depth, the transverse diffusion distance of the Ga ions in the semiconductor is at least two times lower, so that the region and the depth of ion implantation can be better controlled by using the Ga ions, a local high-doped region is formed, and steep doping concentration is obtained, so that the first diffusion-preventing doped region is favorably ensured to be positioned in a fin part between a source-drain doped region and a channel, the transverse diffusion of the doped ions of the source-drain doped region to the channel region can be effectively inhibited, the transverse punch-through of the source-drain doped region and the channel region is prevented, the channel leakage current is favorably reduced, the short channel problem is improved, the Ga ions are also favorable for improving DIBL, the device gain is improved, and the electrical performance of the semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 1, a base is provided, and the base includes a substrate 100 and a fin 110 protruding from the substrate 100.

The substrate 100 provides a process platform for subsequently forming semiconductor structures. In this embodiment, the substrate is used to form an NMOS transistor.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

With continued reference to fig. 1, a gate structure 210 is formed across the fin 110, wherein the gate structure 210 covers a portion of the top and a portion of the sidewalls of the fin 110.

In this embodiment, the gate structure 210 is a dummy gate structure, the gate structure 210 includes a gate oxide layer 200 and a gate layer 120 located on the gate oxide layer 200, and the gate structure 210 occupies a space for a metal gate structure to be formed subsequently.

The gate oxide layer 200 is made of silicon oxide or silicon oxynitride; the gate layer 120 is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, the gate oxide layer 200 is made of silicon oxide, and the gate layer 120 is made of polysilicon.

In other embodiments, the gate structure may also be a metal gate structure.

With continuing reference to fig. 1, after forming the gate structure 210, the forming method further includes: a first sidewall 125 is formed on a sidewall of the gate structure 210.

In this embodiment, the first sidewall 125 is an Offset Spacer (Offset Spacer), and the first sidewall 125 is used to define an implantation region for a subsequent Low Doped Drain (LDD) ion implantation process.

In this embodiment, the first sidewall spacers 125 are made of silicon nitride. In other embodiments, the material of the first sidewall spacer can also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

Referring to fig. 2, after the forming the first sidewall spacers 125, the forming method further includes: the fin portions 110 on both sides of the gate structure 210 are subjected to a low-doped drain ion implantation process 300, and low-doped regions 115 are formed in the fin portions 110 on both sides of the gate structure 210.

In this embodiment, the substrate is used to form an NMOS transistor, so the doping ions of the low doping region 115 are N-type ions, such as: p, As or Sb.

In other embodiments, after forming the first sidewall spacers, the forming method may further include: and carrying out pocket (pocket) injection process on the fin parts at two sides of the grid structure, and forming pocket regions in the fin parts at two sides of the grid structure.

Referring to fig. 3, after forming the low doped regions 115 in the fins 110 on both sides of the gate structure 210, the forming method further includes: a second sidewall 130 is formed on a sidewall of the first sidewall 125.

The second side wall 130 is used for protecting the side wall of the gate structure 210 in a subsequent process, and the second side wall 130 is further used for defining a formation region of a subsequent source-drain doped region to prevent the source-drain doped region from being too close to a channel region.

In this embodiment, the second sidewall spacers 130 are made of silicon nitride. In other embodiments, the material of the second sidewall spacer can also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

With reference to fig. 3 to fig. 4, after the second sidewall 130 is formed, a first diffusion-preventing doped region 140 is formed in the fin portion 110 at two sides of the gate structure 210, and the doped ions in the first diffusion-preventing doped region 140 include Ga ions.

Compared with common P-type ions (such as B ions), under the same ion implantation depth, the transverse diffusion distance of the Ga ions in the semiconductor is at least two times lower, so that the region and the depth of ion implantation can be better controlled by using the Ga ions, a local high-doped region is formed, and a steep doping concentration is obtained, so that the first diffusion-preventing doped region 140 is favorably ensured to be positioned in the fin part 110 between the source-drain doped region and the channel, the transverse diffusion of the doped ions of the source-drain doped region to the channel region can be effectively inhibited, the transverse punch-through of the source-drain doped region and the channel region is prevented, the channel leakage current is favorably reduced, the short channel problem is improved, and the Ga ions are favorable for improving DIBL, improving the device gain and further improving the electrical performance of the semiconductor structure.

Referring to fig. 3, in the present embodiment, after forming the second sidewall 130 on the sidewall of the first sidewall 125, before forming the first diffusion preventing doping region 140 in the fin 110 at two sides of the gate structure 210, the method further includes: grooves 135 exposing the substrate 100 are formed at both sides of the gate structure 210.

The recess 135 provides a spatial location for the subsequent formation of source and drain doped regions. In the process of forming the first diffusion-preventing doped region 140 (as shown in fig. 4) in the following manner, the first ion doping treatment may be performed on the sidewall of the recess 135 close to the gate structure 210, which is beneficial to positioning the first diffusion-preventing doped region 140 in the entire sidewall of the fin 110, so as to further enhance the effect of the first diffusion-preventing doped region 140 on preventing the source-drain doped region and the channel region from being laterally penetrated.

In this embodiment, the second sidewall 130 is used as an etching mask, and the fin portions 110 on two sides of the gate structure 210 are removed by etching using a dry etching process to form the groove 135. Accordingly, the sidewall of the recess 135 near the gate structure 210 is flush with the sidewall of the second sidewall 130 facing away from the gate structure 210.

The dry etching process is an anisotropic etching process, has good etching profile controllability, is beneficial to enabling the appearance of the groove 135 to meet the process requirements, and has small loss on the substrate 100 below the side wall 130. In other embodiments, the groove 135 may be formed by a wet etching process or a combination of a wet etching process and a dry etching process.

It should be noted that under the action of the first side wall 125 and the second side wall 130, the low-doped region 115 below the first side wall 125 and the second side wall 130 is reserved, which is beneficial to forming an ultra-shallow junction in the source region and the drain region, thereby being beneficial to improving the electrical performance of the semiconductor structure.

Referring to fig. 4, after forming the grooves 135 exposing the substrate 100 in the fins 110 on both sides of the gate structure 210, a first ion doping process 400 is performed on the sidewall of the groove 135 close to one side of the gate structure 210, and a first diffusion-preventing doped region 140 is formed in the sidewall of the fin 110 exposed in the groove 135, where the doping ions in the first diffusion-preventing doped region 140 include Ga ions.

The first diffusion-preventing doped region 140 is formed in the sidewall of the groove 135 close to the side of the gate structure 210, and after a source-drain doped region is formed in the groove 135, the first diffusion-preventing doped region 140 can effectively prevent the source-drain doped region and the channel region from being laterally penetrated.

In this embodiment, the doping ions In the first diffusion-preventing doping region 140 are Ga ions and In ions.

In ions and Ga ions belong to the same group of elements and have similar electrical properties, and In ions are commonly used doping ions In a semiconductor structure, so that the process stability is improved by doping In ions.

Specifically, the first ion doping process 400 is an ion implantation process, and accordingly, implanted ions of the ion implantation process are Ga ions and In ions.

It should be noted that the implantation energy of the ion implantation process is not too small and not too large. If the implantation energy is too small, the doping ions in the first diffusion-preventing doping region 140 are difficult to be implanted into the preset depth, so that the effect of the first diffusion-preventing doping region 140 for inhibiting the doping ions of the source-drain doping region from diffusing to the channel region is reduced; if the energy of the implanted ions is too large, problems such as implantation contamination and particle scattering are easily caused. For this reason, In the present embodiment, the implantation energy of Ga ions is 15KeV to 45KeV, and the implantation energy of In ions is 25KeV to 45 KeV.

In this embodiment, the implantation energies of the Ga ions and the In ions are reasonably set, so that the Ga ions and the In ions can be uniformly distributed In the first diffusion-preventing doping region 140.

It should be noted that the implantation dose of the ion implantation process is not too small and not too large. If the implantation dose is too small, the doping concentration of the first diffusion-preventing doping region 140 is correspondingly too low, the first diffusion-preventing doping region 140 is difficult to inhibit the diffusion of the doping ions of the subsequent source-drain doping region to the channel region, and when the implantation dose is too small, the ion implantation process is easily limited by the capability of the machine or cannot reach the effective ion implantation depth; if the implantation dose is too large, the doping concentration of the first diffusion-preventing doping region 140 is too high, which easily causes too high damage to the lattice structure of the fin 110 by the ion implantation process, and easily converts the fin 110 into an amorphous state too much, thereby causing difficulty in forming an epitaxial layer in the groove 135 by an epitaxial process; moreover, when the implantation dosage is too large, the implanted ions of the ion implantation process are easy to enter the channel region. For this reason, In the present embodiment, the implantation dose of Ga ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the implantation dose of In ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter.

In this embodiment, since the enhanced diffusion effect of Ga ions is smaller than that of In ions, by reasonably setting the implantation doses of Ga ions and In ions, the effect of the first diffusion-preventing doped region 140 blocking diffusion of doped ions In the source/drain doped region to the channel region is further enhanced.

In addition, the implantation angle of the ion implantation process should not be too large, otherwise, the implantation angle is easily in the direction perpendicular to the sidewall of the gate structure 210, so that the depth of the first diffusion-preventing doped region 140 is too large, and the channel region is easily adversely affected. For this reason, in the present embodiment, the implantation angle is 15 to 35 degrees.

It should be noted that, in other embodiments, the doping ions in the first diffusion-prevention doping region may also be only Ga ions. Correspondingly, in order to ensure the effect that the first diffusion-preventing doped region blocks the doped ions of the source-drain doped region from diffusing to the channel region, the doping concentration of the Ga ions is properly increased. Specifically, the parameters of the ion implantation process include: the implantation energy is 15KeV to 45KeV, the implantation dosage is 1E13 atoms per square centimeter to 5E13 atoms per square centimeter, and the implantation angle is 15 degrees to 35 degrees.

Referring to fig. 5 in combination, after forming the first diffusion preventing doped region 140 in the sidewall of the recess 135 near the side of the gate structure 210, the forming method includes: a portion of the thickness of the substrate 100 at the bottom of the recess 135 is removed.

After the first ion doping process 400, the substrate 100 at the bottom of the groove 135 also usually has doped ions, and by removing the substrate 100 with a part of the thickness and removing the substrate material doped with ions, the epitaxial growth in the groove 135 is facilitated when a source-drain doped region is formed in the subsequent process.

Specifically, the amount of the substrate 100 removed from the bottom of the groove 135 is a first thickness, which is not too small nor too large. If the first thickness is too small, it is difficult to completely remove the substrate material doped with ions in the substrate 100 at the bottom of the groove 135, thereby affecting the subsequent epitaxial growth in the groove 135; if the first thickness is too large, the distance from the bottom of the subsequently formed source-drain doped region to the bottom of the substrate 100 is too small, which is likely to have a bad influence on the electrical performance of the semiconductor structure. For this reason, in the present embodiment, the first thickness is 30nm to 50 nm.

In this embodiment, a dry etching process is used to etch a portion of the thickness of the substrate 100 at the bottom of the groove 135. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for reducing the probability of loss of the substrate 100 and the fin part 110 on the side wall of the groove 135, and is favorable for ensuring that the removal amount of the substrate 100 at the bottom of the groove 135 meets the process requirements.

In other embodiments, the substrate with a partial thickness may be removed by a wet etching process or a combination of dry etching and wet etching.

Referring to fig. 6 in combination, it should be noted that after removing a portion of the thickness of the substrate 100 at the bottom of the groove 135, the forming method further includes: and performing second ion doping treatment 500 on the side wall of any one of the grooves 135 close to one side of the gate structure 210, and forming a second diffusion-preventing doped region 145 in the first diffusion-preventing doped region 140 on the side wall of the groove 135, wherein the doping ions of the second ion doping treatment 500 include Ga ions.

In the step of forming the source-drain doped regions in the fin portions 110 on the two sides of the gate structure 210, the source-drain doped region in the fin portion 110 on one side of the gate structure 210 is a source region, the source-drain doped region in the fin portion 110 on the other side of the gate structure 210 is a drain region, and the second diffusion-preventing doped region 145 is adjacent to the source region, so that a shallower junction can be formed in the source region, junction current can be reduced, and a short channel effect can be improved.

From the foregoing analysis, it is known that the Ga ions can effectively inhibit the dopant ions in the source region from laterally diffusing into the channel region, and prevent the source region and the channel region from laterally penetrating, thereby being beneficial to reducing the channel leakage current. Therefore, in this embodiment, the doping ions of the second ion doping process 500 are Ga ions.

Specifically, the process of the second ion doping treatment 500 is an ion implantation process, and accordingly, the implanted ions of the ion implantation process are Ga ions.

The implantation energy of the ion implantation process is not too small or too large. If the energy of the implanted ions is too small, the doped ions in the second diffusion-preventing doped region 145 are difficult to be implanted into the predetermined depth, so that the effect of the second diffusion-preventing doped region 145 for inhibiting the doped ions of the source region from diffusing into the channel region is reduced; if the energy of the implanted ions is too large, problems such as implantation contamination and particle scattering are easily caused. For this reason, in the present embodiment, the implantation energy of Ga ions is 5KeV to 35 KeV.

The implantation dosage of the ion implantation process is not required to be too small or too large. If the implantation dose is too small, the doping concentration of the second diffusion-preventing doping region 145 is too low, the second diffusion-preventing doping region 145 is difficult to inhibit the diffusion of the doping ions of the subsequent source region to the channel region, and when the implantation dose is too small, the ion implantation process is easily limited by the capability of the machine or cannot reach the effective ion implantation depth; if the implantation dose is too large, the doping concentration of the second diffusion-preventing doping region 145 is too high, which easily causes too high damage to the lattice structure of the fin 110 by the ion implantation process, and easily converts the fin 110 into an amorphous state too much, thereby causing difficulty in forming an epitaxial layer in the groove 135 by an epitaxial process; moreover, when the implantation dosage is too large, the implanted ions of the ion implantation process are easy to enter the channel region. For this reason, in the present embodiment, the implantation dose of Ga ions is 1E13 atoms per square centimeter to 5E13 atoms per square centimeter.

The implantation angle of the ion implantation process should not be too large, otherwise it is easy to be in the direction perpendicular to the sidewall of the gate structure 210, so that the depth of the second anti-diffusion doped region 145 is too large, which is easy to have a bad effect on the channel region. For this reason, in the present embodiment, the implantation angle is 15 to 35 degrees.

In other embodiments, the doping ions In the second diffusion-preventing doping region may also be Ga ions and In ions. Correspondingly, the parameters of the ion implantation process include: the implantation energy of Ga ions is 5KeV to 35KeV, the implantation dose of Ga ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, the implantation energy of In ions is 15KeV to 35KeV, the implantation dose of In ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the implantation angle is 15 degrees to 35 degrees.

In this embodiment, after the first ion doping process 400 is performed, the second ion doping process 500 is performed. In other embodiments, the sequence of the first ion doping process and the second ion doping process may also be changed.

With reference to fig. 7, it should be further noted that, after forming the second diffusion preventing doping regions 145 in the first diffusion preventing doping regions 140 on the sidewalls of the grooves 135, the forming method includes: a portion of the thickness of the substrate 100 at the bottom of the recess 135 is removed.

After the second ion doping process 500, the substrate 100 at the bottom of the groove 135 also usually has doped ions, and by removing the substrate 100 with a part of the thickness, the substrate material doped with ions is removed, so that the epitaxial growth in the groove 135 is facilitated when a source-drain doped region is formed in the subsequent process.

Specifically, the removal amount of the substrate 100 at the bottom of the groove 135 is a second thickness, which is not too small nor too large. If the second thickness is too small, it is difficult to completely remove the substrate material doped with ions in the substrate 100 at the bottom of the groove 135, thereby affecting the subsequent epitaxial growth in the groove 135; if the second thickness is too large, the distance from the bottom of the subsequently formed source-drain doped region to the bottom of the substrate 100 is easily too small, and the electrical performance of the semiconductor structure is easily affected. For this purpose, the second thickness is 5nm to 15 nm.

In this embodiment, a dry etching process is used to etch a portion of the thickness of the substrate 100 at the bottom of the groove 135. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for reducing the probability of loss of the side wall of the groove 135 and the fin part 100, and is favorable for ensuring that the removal amount of the substrate 100 at the bottom of the groove 135 meets the process requirements.

In other embodiments, the substrate with a partial thickness may be removed by a wet etching process or a combination of dry etching and wet etching.

It should be noted that, in this embodiment, the substrate 100 at the bottom of the groove 135 is subjected to two etching processes, which is beneficial to completely removing the substrate material containing the dopant ions at the bottom of the groove 135, so as to be beneficial to performing the subsequent epitaxial growth in the groove 135.

In other embodiments, the substrate at the bottom of the groove may be etched once. Specifically, after the first diffusion-preventing doped region and the second diffusion-preventing doped region are formed, part of the thickness substrate at the bottom of the groove is removed. The substrate at the bottom of the groove is subjected to one-time etching treatment, so that the process steps are simplified, and the process cost is reduced.

Accordingly, in order to ensure the normal operation of the subsequent epitaxial process, the substrate removal amount at the bottom of the groove is a third thickness, and the third thickness is 35nm to 65 nm.

Referring to fig. 8, a source-drain doped region 150 is formed in the fin portion 110 at two sides of the gate structure 210, and along a direction perpendicular to the sidewall of the gate structure 210, the source-drain doped region 150 is adjacent to the first diffusion-preventing doped region 140 and is located at a side of the first diffusion-preventing doped region 140 away from the gate structure 210.

Specifically, after removing a thickness of the substrate 100 at the bottom of the groove 135, an epitaxial layer (not shown) is formed in the groove 135, and a source/drain doped region 150 is formed in the epitaxial layer.

In this embodiment, the step of forming the source/drain doped region 150 includes: forming a first epitaxial layer on the bottom and the sidewall of the groove 135 (as shown in fig. 7), and performing a first in-situ self-doping in the process of forming the first epitaxial layer to form a bottom source drain doping layer 151; forming a second epitaxial layer covering the bottom source-drain doping layer 151 in the groove 135, and performing second in-situ self-doping in the process of forming the second epitaxial layer to form a top source-drain doping layer 152, wherein the concentration of doped ions in the top source-drain doping layer 152 is greater than that of doped ions in the bottom source-drain doping layer 151.

The source-drain doped region 150 comprises a bottom source-drain doped layer 151 and a top source-drain doped layer 152, the concentration of doped ions in the top source-drain doped layer 152 is greater than that in the bottom source-drain doped layer 151, the bottom source-drain doped layer 151 is closer to the channel region, and the concentration of doped ions in the bottom source-drain doped layer 151 is smaller, so that the probability of diffusion of doped ions in the source-drain doped region 150 to the substrate 100 and the fin portion 110 is reduced, and the electrical performance of the semiconductor can be further improved. The concentration of the doped ions in the top source-drain doped layer 152 is relatively high, and when a contact hole plug electrically connected with the top source-drain doped layer 152 is formed subsequently, the contact resistance between the source-drain doped region 150 and the contact hole plug is reduced.

In this embodiment, the materials and the forming processes of the first epitaxial layer and the second epitaxial layer are the same.

Specifically, the substrate is used for forming an NMOS transistor, so the materials of the first epitaxial layer and the second epitaxial layer are SiC or Si, and the first epitaxial layer and the second epitaxial layer provide a tensile stress effect for a channel region of an N-type transistor, thereby facilitating improvement of carrier mobility of the N-type transistor.

Correspondingly, the invention also provides a semiconductor structure. With continued reference to fig. 8, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: the substrate comprises a substrate 100 and a fin part 110 protruding from the substrate 100, wherein an NMOS transistor is formed on the substrate; a gate structure 210 spanning the fin 110 and covering a portion of the top and a portion of the sidewalls of the fin 110; the first diffusion-preventing doped region 140 is located in the fin portion 110 at two sides of the gate structure 210, and doped ions of the first diffusion-preventing doped region 140 include Ga ions; and the source-drain doped region 150 is positioned in the fin portion 110 at two sides of the gate structure 210, and the source-drain doped region 150 is adjacent to the first diffusion-preventing doped region 140 and positioned at one side of the first diffusion-preventing doped region 140 far away from the gate structure 210 along a direction perpendicular to the side wall of the gate structure 210.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

In this embodiment, the gate structure 210 includes a gate oxide layer 200 and a gate layer 120 on the gate oxide layer 200.

The gate oxide layer 200 is made of silicon oxide or silicon oxynitride; the gate layer 120 is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, the gate oxide layer 200 is made of silicon oxide, and the gate layer 120 is made of polysilicon.

In other embodiments, the gate structure may also be a metal gate structure.

In this embodiment, the semiconductor structure further includes: a first sidewall 125 on a sidewall of the gate structure 210; a second sidewall 130 on a sidewall of the first sidewall 125; and a low doped region 115 located in fin 110 on both sides of gate structure 210.

In this embodiment, the first sidewall 125 is an Offset Spacer (Offset Spacer), and the first sidewall 125 is used to define the area of the low-doped region 115

In this embodiment, the first sidewall spacers 125 are made of silicon nitride. In other embodiments, the material of the first sidewall spacer can also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

In this embodiment, the second sidewall 130 is used to protect the gate structure 210 during the formation of the semiconductor structure, and is also used to define the region of the source-drain doped region 150, so as to prevent the source-drain doped region 150 from being too close to the channel region.

In this embodiment, the second sidewall spacers 130 are made of silicon nitride. In other embodiments, the material of the second sidewall spacer can also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

In this embodiment, an NMOS transistor is formed on the substrate, so the doped ions in the low doped region 115 are N-type ions, such as: p, As or Sb. The low-doped region 115 is located in the fin 110 below the first sidewall 125 and the second sidewall 130, which is beneficial to forming an ultra-shallow junction in the source region and the drain region, and is beneficial to improving the electrical performance of the semiconductor structure.

The first diffusion-preventing doped region 140 is configured to inhibit the doped ions of the source-drain doped region 150 from diffusing to the channel region, and prevent the source-drain doped region 150 and the channel region from being laterally penetrated, so as to reduce channel leakage current and improve electrical performance of the semiconductor structure.

In this embodiment, the doping ions in the first diffusion-preventing doping region 140 include Ga ions.

Among them, Ga ions have better activity and higher solid solubility than common dopant ions In, so Ga ions are more easily activated In semiconductors and have higher doping concentration; compared with common P-type ions (such as B ions), the transverse diffusion distance of the Ga ions in the semiconductor is at least two times lower under the same ion implantation depth, so that the Ga ions are favorable for forming a local high-doped region in the first diffusion-preventing doped region 140 to obtain a steep doping concentration, the first diffusion-preventing doped region 140 is favorable for ensuring that the first diffusion-preventing doped region 140 is positioned in the fin portion 110 between the source-drain doped region 150 and the channel region, the transverse diffusion of the doped ions of the source-drain doped region 150 to the channel region can be effectively inhibited, the transverse punch-through of the source-drain doped region 150 and the channel region is prevented, the channel leakage current is favorably reduced, the short channel problem is improved, and the Ga ions are favorable for improving DIBL, the device gain and the electrical performance of the semiconductor structure.

In this embodiment, the doping ions In the first diffusion-preventing doping region 140 are Ga ions and In ions.

In ions and Ga ions belong to the same group of elements and have similar electrical properties, and In ions are commonly used doping ions In a semiconductor structure, so that the process stability is improved by doping In ions.

In this embodiment, the semiconductor structure further includes: a recess 135 (as shown in fig. 3), wherein the recess 135 is located in the fin 110 at two sides of the gate structure 210, and the bottom of the recess 135 is exposed out of the substrate 100.

Specifically, the sidewall of the groove 135 close to the gate structure 210 and the sidewall of the second sidewall 130 facing away from the gate structure 210 are flush.

In this embodiment, the first diffusion-preventing doped region 140 is located in the fin portion 110 on the sidewall of the groove 135 close to one side of the gate structure 210, the source-drain doped region 150 is located in the groove 135, and the first diffusion-preventing doped region 140 can effectively prevent doped ions in the source-drain doped region 150 from laterally diffusing into the fin portion 110 under the gate structure 210, so as to further enhance the effect of the first diffusion-preventing doped region 140 on preventing the source-drain doped region 150 and the channel region from laterally penetrating.

It should be noted that the concentration of the dopant ions in the first diffusion-preventing doping region 140 is not too small, and is not too large. If the concentration of the doped ions is too small, the first diffusion-preventing doped region 140 is difficult to inhibit the doped ions of the source-drain doped region 150 from diffusing into the channel region; if the concentration of the doped ions is too high, the damage degree of the process for forming the first diffusion-preventing doped region 140 to the lattice structure of the substrate 100 is too high, and the substrate 100 is excessively converted into an amorphous state, thereby causing adverse effects on the formation of the source-drain doped region 150.

For this reason, In the present embodiment, the doping concentration of Ga ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter, and the doping concentration of In ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.

It should be noted that the depth of the first anti-diffusion doping region 140 in the direction perpendicular to the sidewall of the gate structure 210 is not too small nor too large. If the depth is too small, the effect of the first diffusion-preventing doped region 140 for inhibiting the diffusion of the doped ions in the source-drain doped region 150 to the channel region is easily reduced; if the depth is too large, the first anti-diffusion doped region 140 is too close to the channel region, which may easily affect the electrical performance of the semiconductor structure. For this, the depth of the first diffusion preventing doping region 140 is 10nm to 30nm in a direction perpendicular to the sidewall of the gate structure 210. Wherein, the depth of the first diffusion-preventing doped region 140 refers to: the distance from the sidewall of the groove 135 close to one side of the gate structure 210 to the boundary of the first diffusion-preventing doped region 140 is along the direction perpendicular to the sidewall of the gate structure 210.

In other embodiments, the doping ions of the first diffusion-preventing doping region may also be only Ga ions. Accordingly, in order to secure the diffusion preventing effect of the first diffusion preventing doped region, the doping concentration of Ga ions is 1E18 atoms per cubic centimeter to 5E18 atoms per cubic centimeter, and the depth of the first diffusion preventing doped region is 10nm to 30nm in a direction perpendicular to the side wall of the gate structure.

In this embodiment, the source-drain doped region 150 located in the fin portion 110 on one side of the gate structure 210 is a source region, and the source-drain doped region 150 located in the fin portion 110 on the other side of the gate structure 210 is a drain region; the semiconductor structure further includes a second anti-diffusion doping region 145 located at one side of the gate structure 210, the second anti-diffusion doping region 145 is located in the first anti-diffusion doping region 140 on the sidewall of the groove 135, and the doping ions of the second anti-diffusion doping region 145 include Ga ions.

In this embodiment, the second anti-diffusion doped region 145 is adjacent to the source region, which is beneficial to forming a shallower junction in the source region, reducing junction current, and improving short channel effect.

From the foregoing analysis, it is known that the Ga ions can effectively inhibit the dopant ions in the source region from laterally diffusing into the channel region, and prevent the source region and the channel region from laterally penetrating, thereby being beneficial to reducing the channel leakage current.

In this embodiment, the doping ions of the second anti-diffusion doping region 145 are Ga ions.

It should be noted that the concentration of the dopant ions in the second diffusion-preventing doping region 145 is not too small or too large. If the concentration of the doping ions is too small, the second diffusion-preventing doping region 145 is difficult to inhibit the doping ions of the source region from diffusing into the channel region; if the concentration of the doped ions is too high, the damage degree of the process for forming the second diffusion-preventing doped region 145 to the lattice structure of the substrate 100 is too high, and the substrate 100 is excessively converted into an amorphous state, thereby causing adverse effects on the formation of the source-drain doped region 150.

For this reason, in the present embodiment, the doping concentration of Ga ions is 1E18 atoms per cubic centimeter to 5E18 atoms per cubic centimeter.

It should be noted that the depth of the second anti-diffusion doped region 145 in the direction perpendicular to the sidewall of the gate structure 210 is not too small nor too large. If the depth is too small, the effect of the second diffusion-preventing doped region 145 in suppressing the diffusion of the dopant ions in the source region to the channel region is easily reduced; if the depth is too great, the second diffusion preventing doped region 145 is too close to the channel region, which may easily affect the electrical performance of the semiconductor structure. The second diffusion preventing doping region 145 has a depth of 3nm to 20nm in a direction perpendicular to the sidewalls of the gate structure 210. Wherein, the depth of the second diffusion preventing doping region 145 refers to: the groove 135 is close to the sidewall of one side of the gate structure 210 to the distance from the boundary of the second diffusion-preventing doped region 145 in the direction perpendicular to the sidewall of the gate structure 210.

In other embodiments, the doping ions of the second diffusion-prevention doping region may also be Ga ions and In ions. Correspondingly, In order to guarantee the diffusion prevention effect of the second diffusion prevention doped region, the doping concentration of Ga ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter, the doping concentration of In ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter, and the depth of the second diffusion prevention doped region is 3nm to 20nm along the direction vertical to the side wall of the gate structure.

In this embodiment, the source-drain doped region 150 is located in the groove 135.

Specifically, the source-drain doped region 150 includes a bottom source-drain doped layer 151 and a top source-drain doped layer 152 located on the bottom source-drain doped layer 151. Specifically, the bottom source drain doping layer 151 is located at the bottom and the side wall of the groove 135, and the top source drain doping layer 152 is located in the groove 135 and covers the bottom source drain doping layer 151.

In this embodiment, the concentration of the doped ions in the top source-drain doped layer 152 is greater than the concentration of the doped ions in the bottom source-drain doped layer 151, the bottom source-drain doped layer 151 is closer to the channel region, and the concentration of the doped ions in the bottom source-drain doped layer 151 is smaller, so that the probability that the doped ions in the source-drain doped region 150 diffuse into the substrate 100 and the fin portion 110 is favorably reduced, and thus the electrical performance of the semiconductor structure can be further improved. The concentration of the doped ions in the top source-drain doped layer 152 is relatively high, and when a contact hole plug electrically connected with the top source-drain doped layer 152 is formed subsequently, the contact resistance between the source-drain doped region 150 and the contact hole plug is reduced.

In this embodiment, the bottom source-drain doping layer 151 includes a first epitaxial layer doped with N-type ions, the top source-drain doping layer 152 includes a second epitaxial layer doped with N-type ions, and the first epitaxial layer and the second epitaxial layer are made of the same material.

Specifically, the semiconductor structure is an NMOS transistor, so the materials of the first epitaxial layer and the second epitaxial layer are SiC or Si, and the first epitaxial layer and the second epitaxial layer provide a tensile stress effect for a channel region of an N-type transistor, thereby facilitating improvement of carrier mobility of the N-type transistor.

It should be noted that, in the doping process for forming the first diffusion-preventing doping region 140 and the second diffusion-preventing doping region 145, ions are also doped in the substrate 100 at the bottom of the groove 135, so that before the source-drain doping region 150 is formed in the groove 135, a part of the thickness of the substrate 100 at the bottom of the groove 135 is also removed. Therefore, in this embodiment, the source/drain doped region 150 is also located in the substrate 100 with a partial thickness at the bottom of the groove 135.

In this embodiment, according to the depths of the first diffusion-preventing doped region 140 and the second diffusion-preventing doped region 145 in the fin portion 110, the distance from the bottom of the source-drain doped region 150 to the top of the substrate 100 is 35nm to 65 nm.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.