阅读说明：本技术 互补信号生成电路 (Complementary signal generating circuit ) 是由 雷述宇 于 2019-10-31 设计创作，主要内容包括：本申请提供一种互补信号生成电路,涉及电路技术领域。该互补信号生成电路包括：第一容性电路、第二容性电路和感性电路；第一容性电路和第二容性电路分别包括至少一个容性元件,感性电路包括至少一个感性元件；第一容性电路的第一端分别与电源和感性电路的第一端电连接；第一容性电路的第二端接地；第二容性电路的第一端与感性电路的第二端电连接,第二容性电路的第二端接地。通过电源为第一容性电路输入一次能量后,能量可以在第一容性电路和第二容性电路反复振荡,使第一容性电路和第二容性电路产生互补信号,相对于现有的生成互补信号的电路而言,可以有效减少能量浪费,降低互补信号生成电路的能耗。(The application provides a complementary signal generating circuit, relates to circuit technical field. The complementary signal generating circuit includes: a first capacitive circuit, a second capacitive circuit, and an inductive circuit; the first capacitive circuit and the second capacitive circuit respectively comprise at least one capacitive element, and the inductive circuit comprises at least one inductive element; the first end of the first capacitive circuit is electrically connected with the power supply and the first end of the inductive circuit respectively; the second end of the first capacitive circuit is grounded; the first end of the second capacitive circuit is electrically connected with the second end of the inductive circuit, and the second end of the second capacitive circuit is grounded. After the power supply inputs energy for the first capacitive circuit for one time, the energy can repeatedly oscillate in the first capacitive circuit and the second capacitive circuit, so that the first capacitive circuit and the second capacitive circuit generate complementary signals.)

1. A complementary signal generating circuit, comprising: a first capacitive circuit, a second capacitive circuit, and an inductive circuit; wherein the first and second capacitive circuits each comprise at least one capacitive element and the inductive circuit comprises at least one inductive element;

the first end of the first capacitive circuit is electrically connected with a power supply and the first end of the inductive circuit respectively; the second end of the first capacitive circuit is grounded;

the first end of the second capacitive circuit is electrically connected with the second end of the inductive circuit, and the second end of the second capacitive circuit is grounded.

2. The complementary signal generating circuit according to claim 1, further comprising: a compensation circuit;

the compensation circuit is electrically connected with a first end of the first capacitive circuit or a first end of the second capacitive circuit;

the compensation period of the compensation signal output by the compensation circuit is larger than or equal to the period of the complementary signal output by the first capacitive circuit and the second capacitive circuit.

3. The complementary signal generating circuit according to claim 2, wherein the compensation signal output from the compensation circuit is input at a peak position of the complementary signal output from the first capacitive circuit or the second capacitive circuit.

4. The complementary signal generating circuit according to claim 3, further comprising: a first peak clamp and a second peak clamp;

the first peak value clamping circuit is electrically connected with the first end of the first capacitive circuit and is used for clamping the peak value of a complementary signal output by the first capacitive circuit at a preset peak value;

the second peak clamping circuit is electrically connected with the first end of the second capacitive circuit and is used for clamping the peak value of the complementary signal output by the second capacitive circuit at a preset peak value.

5. The complementary signal generating circuit according to any of claims 1-4, wherein the first capacitive circuit, the second capacitive circuit each comprise a plurality of capacitive elements;

a plurality of the capacitive elements are connected in series or in parallel.

6. The complementary signal generating circuit of claim 5, wherein the first capacitive circuit and the second capacitive circuit each comprise a plurality of capacitors connected in parallel.

7. The complementary signal generating circuit of claim 6, wherein said first capacitive circuit comprises M capacitors connected in parallel;

the second capacitive circuit also comprises M capacitors connected in parallel;

wherein M is an integer greater than 1.

8. Complementary signal generating circuit according to any of the claims 1-4, wherein the inductive circuit comprises at least one inductor.

9. The complementary signal generating circuit of claim 8, wherein the inductive circuit comprises a plurality of inductors;

a plurality of said inductors are connected in series.

10. The complementary signal generating circuit of claim 4, wherein the first peak clamp circuit and the second peak clamp circuit each comprise: and a diode.

Technical Field

The present disclosure relates to the field of circuit technologies, and in particular, to a complementary signal generating circuit.

Background

In the field of electronic circuit technology, complementary signals refer to two signals with a phase difference of 180 degrees. The complementary signal may be applied to a digital circuit or an analog circuit as a switching signal, a clock signal, or the like, and for example, the complementary signal may be used to implement a switching power supply, a timer, or the like.

Currently, the complementary signal is generally generated by an inverter. For example, the complementary signal generating circuit may include two sets of inverters; each group of inverters can comprise a P-type transistor, an N-type transistor and a capacitor, the P-type transistor and the N-type transistor are connected in parallel and then connected in series with the capacitor, and the capacitors are all grounded; the two groups of inverters are connected in series, and the P-type transistors of the two groups of inverters are electrically connected with a Drain Voltage (VDD) power supply. By inputting a low level signal and a high level signal to the complementary signal generating circuit, respectively, two sets of inverters can generate complementary signals having a phase difference of 180 degrees.

However, when the above-mentioned conventional complementary signal generating circuit generates the complementary signal, the capacitor repeatedly charges and discharges to the ground, and the process of discharging to the ground causes a large waste of energy, resulting in a high power consumption of the complementary signal generating circuit.

Disclosure of Invention

The present application provides a complementary signal generating circuit which can reduce power consumption of the circuit when generating a complementary signal.

The complementary signal generating circuit provided by the embodiment of the application comprises: a first capacitive circuit, a second capacitive circuit, and an inductive circuit; the first capacitive circuit and the second capacitive circuit respectively comprise at least one capacitive element, and the inductive circuit comprises at least one inductive element; the first end of the first capacitive circuit is electrically connected with the power supply and the first end of the inductive circuit respectively; the second end of the first capacitive circuit is grounded; the first end of the second capacitive circuit is electrically connected with the second end of the inductive circuit, and the second end of the second capacitive circuit is grounded.

Optionally, the complementary signal generating circuit further comprises: a compensation circuit; the compensation circuit is electrically connected with the first end of the first capacitive circuit or the first end of the second capacitive circuit; the compensation period of the compensation signal output by the compensation circuit is larger than or equal to the period of the complementary signal output by the first capacitive circuit and the second capacitive circuit.

Optionally, the compensation signal output by the compensation circuit is input at a peak position of the complementary signal output by the first capacitive circuit or the second capacitive circuit.

Optionally, the complementary signal generating circuit further comprises: a first peak clamp and a second peak clamp; the first peak value clamping circuit is electrically connected with the first end of the first capacitive circuit and is used for clamping the peak value of the complementary signal output by the first capacitive circuit at a preset peak value; the second peak clamping circuit is electrically connected with the first end of the second capacitive circuit and is used for clamping the peak value of the complementary signal output by the second capacitive circuit at a preset peak value.

Optionally, the first capacitive circuit and the second capacitive circuit each comprise a plurality of capacitive elements; the plurality of capacitive elements are connected in series or in parallel.

Optionally, the first capacitive circuit and the second capacitive circuit each include a plurality of capacitors connected in parallel.

Optionally, the first capacitive circuit comprises M capacitors connected in parallel; the second capacitive circuit also comprises M capacitors connected in parallel; wherein M is an integer greater than 1.

Optionally, the inductive circuit comprises at least one inductor.

Optionally, the inductive circuit comprises a plurality of inductors; the plurality of inductors are connected in series.

Optionally, the first peak clamp and the second peak clamp each comprise: and a diode.

In the embodiment of the application, after energy is input to the first capacitive circuit once through the power supply, the energy can repeatedly oscillate in the first capacitive circuit and the second capacitive circuit, so that the first capacitive circuit and the second capacitive circuit can generate complementary signals, and the complementary signals are generated based on the repeated oscillation of the energy in the first capacitive circuit and the second capacitive circuit, so that compared with a circuit which generates complementary signals based on repeated charging and ground discharging in the prior art, the complementary signal generating circuit can effectively reduce energy waste and reduce the energy consumption of the complementary signal generating circuit.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 shows a schematic structural diagram of a complementary signal generating circuit provided in an embodiment of the present application;

FIG. 2 shows a schematic diagram of complementary signals provided by an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a connection between a complementary signal generating circuit and a TOF sensing array according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram illustrating another structure of a complementary signal generating circuit provided in an embodiment of the present application;

FIG. 5 is a graph showing a comparison of compensation periods provided by embodiments of the present application;

fig. 6 is a schematic diagram illustrating another structure of a complementary signal generating circuit provided in an embodiment of the present application;

fig. 7 is a schematic diagram illustrating another structure of a complementary signal generating circuit provided in an embodiment of the present application;

fig. 8 shows a schematic diagram of another structure of a complementary signal generating circuit provided in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it is noted that the terms "first", "second", "third", and the like are used merely for distinguishing between descriptions and are not intended to indicate or imply relative importance.

The embodiment of the application provides a complementary signal generating circuit, which can generate two paths of complementary signals with the phase difference of 180 degrees. The complementary signal generating circuit can be applied to the field of radar, for example, based on the complementary signal generating circuit, a Low-Voltage Differential Signaling (LVDS) technology is utilized in high-speed radars such as a Digital Beam Forming (DBF) system radar and a phased array radar, so that point-to-point single-plate interconnection is realized, and the problem of transmission of large data volume caused by the large increase of the signal bandwidth and the number of signal channels to be processed in the high-speed radar is solved.

Alternatively, the complementary signal generating circuit can also be applied to the field of laser ranging. Taking a Time of flight (TOF) sensing array as an example, in the TOF sensing array, in order to perform phase modulation on a laser waveform reflected by an object to realize ranging, a Photodiode (PD) conversion unit in each pixel needs to modulate and transfer a phase difference of charges generated based on echo + background light by a half period in a Time-sharing manner to charge storage units C1 and C2, respectively, and then distance information is obtained by calculating a charge amount difference between the two charge storage units C1 and C2. In the process, the transmission gate TX1 arranged between the PD and the C1 and the transmission gate TX2 arranged between the PD and the C2 need to be turned on in a time-sharing manner, and are a pair of complementary signals. That is, the complementary signal generated by the complementary signal generating circuit may be applied to the TOF sensing array for realizing the time-sharing conduction of the transmission gate TX1 and the transmission gate TX 2.

Still alternatively, the complementary signal generating circuit can also be applied to some radio frequency power supplies and switching power supplies. For example, the complementary signal generating circuit may form part of a mass spectrometer radio frequency power supply with a signal source, a signal coupling circuit, a driving circuit, and the like, the signal source generates two sinusoidal signals RF and AC, the complementary signal generating circuit may generate two complementary signals RF + and RF-and two complementary signals AC + and AC-based on RF and AC, respectively, and the signal coupling circuit may couple the four complementary signals, so that the driving circuit may amplify the coupled signal to generate a high voltage radio frequency voltage, and the like.

It should be noted that, for a specific application scenario and a related field of the complementary signal generating circuit, the application is not limited herein.

Fig. 1 shows a schematic structural diagram of a complementary signal generating circuit provided in an embodiment of the present application.

As shown in fig. 1, the complementary signal generating circuit may include: a first capacitive circuit 100, a second capacitive circuit 200 and an inductive circuit 300; the first capacitive circuit 100 and the second capacitive circuit 200 each include at least one capacitive element, and the inductive circuit 300 includes at least one inductive element. The first terminal 101 of the first capacitive circuit 100 is electrically connected to the power supply and the first terminal 301 of the inductive circuit 300, respectively; the second terminal 102 of the first capacitive circuit 100 is grounded; the first terminal 201 of the second capacitive circuit 200 is electrically connected to the second terminal 302 of the inductive circuit 300, and the second terminal 202 of the second capacitive circuit 200 is grounded.

The capacitive element may be an element whose current phase leads the voltage phase, and the inductive element may be an element whose current phase lags the voltage phase. The Vin terminal shown in fig. 1 may be used for accessing a power supply, and when the power supply is turned on, that is, Vin is turned on, the capacitive element in the first capacitive circuit 100 may be charged through the first terminal 101 of the first capacitive circuit 100. When Vin is disconnected, the first capacitive circuit 100 is at the maximum forward voltage, the first capacitive circuit 100 starts to discharge, and the electric energy stored in the capacitive element in the first capacitive circuit 100 may sequentially pass through the inductive circuit 300 and the first end 201 of the second capacitive circuit 200, enter the second capacitive circuit 200, and charge the capacitive element in the second capacitive circuit 200. As the charging process for the capacitive element in the second capacitive circuit 200 proceeds, the voltage of the first capacitive circuit 100 gradually decreases to 0, and the forward current of the inductive circuit 300 (from the first end 301 of the inductive circuit 300 to the second end 302 of the inductive circuit 300) increases to the maximum.

Since the current phase of the inductive element in the inductive circuit 300 lags behind the voltage phase, the current has a holding characteristic, and no sudden change of the current occurs, so that the capacitive element in the second capacitive circuit 200 is continuously charged, and the forward current of the inductive circuit 300 gradually decreases to 0. At this time, the reverse voltage of the first capacitive circuit 100 reaches a maximum value, and the forward voltage of the second capacitive circuit 200 reaches a maximum value.

When the forward current of the inductive circuit 300 gradually decreases to 0, the second capacitive circuit 200 starts to discharge, and the electric energy stored in the capacitive element of the second capacitive circuit 200 sequentially passes through the inductive circuit 300 and the second end 102 of the first capacitive circuit 100 in the reverse direction, enters the first capacitive circuit 100, and starts to charge the capacitive element of the first capacitive circuit 100. When the first capacitive circuit 100 is at the highest forward voltage value again, the second capacitive circuit 200 is charged again.

As the charging and discharging processes of the first capacitive circuit 100 and the second capacitive circuit 200 proceed, an oscillating circuit with sequential cyclic discharging is formed between the first capacitive circuit 100 and the second capacitive circuit 200. Assuming that the first end 101 of the first capacitive circuit 100 and the first end 301 of the inductive circuit 300 intersect at a point a, and the first end 201 of the second capacitive circuit 200 and the second end 302 of the inductive circuit 300 intersect at a point B, after the oscillating circuit is formed, the points a and B in the circuit may output two complementary signals with a phase difference of 180 degrees.

Fig. 2 shows a schematic diagram of complementary signals provided by an embodiment of the present application.

As shown in fig. 2, if the signal output from point a is an a signal and the signal output from point B is a B signal, the a signal and the B signal are complementary signals, and the phase difference is 180 degrees.

Alternatively, the peak, peak-valley, and period of the a and B signals are all the same.

Fig. 3 shows a schematic connection diagram of a complementary signal generation circuit and a TOF sensing array according to an embodiment of the present application.

As shown in fig. 3, taking the TOF sensing array as an example, the a signal output from the point a may be connected to a transmission gate TX1 arranged between C1 and PD in the TOF sensing array, and the B signal output from the point B may be connected to a transmission gate TX2 arranged between PD and C2 in the TOF sensing array. When the PD receives the echo + background light signal, first, the first capacitive circuit 100 is at a forward voltage, and when the voltage value of the a signal is higher than the turn-on voltage of the transmission gate TX1, the TX1 is turned on; while the second capacitive circuit 200 is at a low potential, TX2 is off, and the photo-generated charge in the PD is transferred into C1 via TX 1. As the charging process for the capacitive element in the second capacitive circuit 200 proceeds, during the process that the voltage of the first capacitive circuit 100 gradually decreases to 0, the first capacitive circuit 100 will switch to the low voltage level, and TX1 will switch to the off state; the second capacitive circuit 200 is gradually at a forward voltage, and when the voltage value of the B signal is higher than the turn-on voltage of the transmission gate TX2, the TX2 is turned on, and the photo-generated charges in the PD are transferred to the C2 through TX 2. After repeated modulation of N periods, the phase modulation and demodulation function of the laser reflection waveform can be realized.

As described above, in the embodiment of the present application, after energy is input to the first capacitive circuit once by the power supply, the energy may repeatedly oscillate in the first capacitive circuit and the second capacitive circuit, so that the first capacitive circuit and the second capacitive circuit may generate complementary signals, and since the complementary signals are generated based on the repeated oscillation of the energy in the first capacitive circuit and the second capacitive circuit, compared with a circuit in the prior art that generates complementary signals based on repeated charging and discharging to ground, energy waste may be effectively reduced, and energy consumption of the complementary signal generating circuit may be reduced.

In practical implementation of the complementary signal generating circuit provided in the embodiment of the present application, since the first capacitive circuit and the second capacitive circuit actually have resistors (e.g., a wire resistor, an element resistor, etc.), an oscillation process of energy between the first capacitive circuit and the second capacitive circuit is actually damped oscillation, which may cause gradual energy loss, and further cause amplitude attenuation of the complementary signal.

To avoid amplitude attenuation of the complementary signal, the complementary signal circuit may be energized to maintain the complementary signal output for a long time.

In one embodiment, the first capacitive circuit may be charged by turning Vin on again to supplement the energy oscillating between the first capacitive circuit and the second capacitive circuit.

In another implementation, the compensation circuit may be added to the complementary signal generating circuit described in the foregoing embodiment to supplement energy. Fig. 4 shows another schematic structural diagram of the complementary signal generating circuit provided in the embodiment of the present application.

As shown in fig. 4, in this embodiment, the complementary signal generating circuit may further include: a compensation circuit 400; the compensation circuit 400 is electrically connected to the first terminal 101 of the first capacitive circuit 100 or the first terminal 201 of the second capacitive circuit 200; the compensation period of the compensation signal output by the compensation circuit 400 is greater than or equal to the period of the complementary signal output by the first capacitive circuit 100 and the second capacitive circuit 200.

Alternatively, the oscillator circuit may be forced to be excited periodically by the compensation circuit 400, the excitation period also being referred to as the compensation period. The compensation circuit 400 may be connected to the first capacitive circuit 100 for energy compensation, and may also be connected to the second capacitive circuit 200 for energy compensation, which is not limited herein.

Assuming that the complementary signal output by the complementary signal generating circuit has a period of T1 and the compensation signal output by the compensation circuit has a compensation period of T2, T2 may be greater than or equal to T1.

Fig. 5 shows a comparison graph of compensation periods provided by the embodiments of the present application.

As shown in fig. 5, for example, when T2 is 3T1, the amplitude of the signal output at A, B has already been attenuated to some extent after oscillation for three cycles, and in the fourth cycle, the compensation circuit may perform energy compensation on the complementary signal generating circuit, and after the compensation, the peak value of the complementary signal may be restored to the peak value of the first cycle again. This process does not require a full energy re-input for each cycle, thus further reducing the power consumption of the complementary signal generating circuit.

Alternatively, the complementary signal generating circuit may be energy-compensated by the compensation circuit cycle by cycle, that is, T2 is T1, so as to form constant amplitude oscillation, and the amplitude of the A, B-point output signal is kept stable, which is not limited herein.

Alternatively, the compensation signal output by the compensation circuit may be input at a peak position of the complementary signal output by the first capacitive circuit or the second capacitive circuit. Or, the compensation signal can be input at a valley position or other positions, and when the compensation signal is input through the compensation circuit, the interference of the compensation signal on the complementary signal can be reduced to the maximum extent by keeping the input compensation signal and the complementary signal in the same period and the same phase.

Alternatively, in this embodiment, the period of the complementary signal output at point A, B depends on the compensation period of the compensation circuit, and therefore, the period of the complementary signal can also be adjusted by controlling the compensation period of the compensation circuit, such as: increase or decrease.

The compensation circuit may be a common signal compensation circuit such as a signal modulation circuit or a signal amplification circuit, and may adjust the amplitude, the period, and the like of the complementary signal to compensate the complementary signal. Based on the technical solutions disclosed in the embodiments of the present application, a person skilled in the art selects different compensation circuits to compensate the complementary signals, and the present application does not limit the specific structure of the compensation circuits.

Fig. 6 shows a schematic diagram of another structure of a complementary signal generating circuit provided in an embodiment of the present application.

Optionally, as shown in fig. 6, the complementary signal generating circuit may further include: a first peak clamp 510 and a second peak clamp 520; the first peak clamping circuit 510 is electrically connected to the first end 101 of the first capacitive circuit 100, and is configured to clamp a peak of a complementary signal output by the first capacitive circuit 100 at a predetermined peak; the second peak clamping circuit 520 is electrically connected to the first end 201 of the second capacitive circuit 200, and is configured to clamp a peak of the complementary signal output by the second capacitive circuit 200 at a predetermined peak.

The preset peak value may be a peak value of a complementary signal required by a subsequent unit connected to the complementary signal generating circuit, for example, the subsequent unit may be an optical signal acquisition device, the optical signal acquisition device may include a channel 1 and a channel 2, and the complementary signals are the above-mentioned a signal and B signal; then, when the output signal is an a signal, the channel 1 may perform optical signal acquisition; and when the output signal is a B signal, optical signal acquisition is performed by the channel 2, and the like. The magnitude of the preset peak may be 2.5 volts (V), 3.0V, etc., and the present application does not limit the magnitude of the preset peak.

In the embodiment of the present application, the first peak clamping circuit and the second peak clamping circuit may clamp the peak values of the complementary signal output by the first capacitive circuit and the complementary signal output by the second capacitive circuit to the preset peak values, that is, the peak value of the complementary signal output at point A, B may be kept at the preset peak value, so as to ensure the stability of the complementary signal output by the complementary signal generating circuit, thereby ensuring the safety of the rear-stage unit.

Alternatively, to ensure that the period and peak value of the complementary signal are the same, the structures of the first capacitive circuit and the second capacitive circuit may be the same.

In one embodiment, the first capacitive circuit and the second capacitive circuit each include a plurality of capacitive elements; the plurality of capacitive elements are connected in series or in parallel.

Fig. 7 shows a schematic diagram of another structure of a complementary signal generating circuit provided in an embodiment of the present application.

Alternatively, as shown in fig. 7, each of the first capacitive circuit 100 and the second capacitive circuit 200 may include a plurality of capacitors 110(210) connected in parallel. And the inductive circuit 300 may comprise at least one inductor 310. For example, the inductive circuit 300 may include a plurality of inductors 310 connected in series; alternatively, there may be only one inductor 310.

The first capacitive circuit 100 and the second capacitive circuit 200 are formed by a plurality of capacitors, and can also have a good filtering effect.

Alternatively, the first capacitive circuit may comprise M capacitors connected in parallel; the second capacitive circuit may also comprise M capacitors connected in parallel; wherein M is an integer greater than 1, for example, M may be 2, 3, 5, 8, 10, etc., and the specific value of M is not limited in the present application. That is, in the present application, the number of capacitors included in the first capacitive circuit and the second capacitive circuit and the connection relationship between the capacitors may be the same, that is, the first capacitive circuit and the second capacitive circuit may be two identical circuits.

Please continue to refer to fig. 7:

optionally, in some embodiments of the present application, a switch S may be disposed between the Vin terminal and the first terminal of the first capacitive circuit, and the complementary signal generating circuit may be powered on or powered off at the Vin terminal by turning on or off the switch S.

Optionally, the first peak clamp circuit and the second peak clamp circuit may each comprise: and a diode.

Fig. 8 shows a schematic diagram of another structure of a complementary signal generating circuit provided in an embodiment of the present application.

As shown in fig. 8, the first peak clamp circuit 510 may include: a first diode D1, a second diode D2. The positive pole of D1 is connected to the negative pole of D2, and is commonly connected to the signal output terminal (101) of the first capacitive circuit 100. The negative electrode of D1 is grounded, and the positive electrode of D2 is externally connected with a power supply voltage (Vcc). When the output voltage of the signal output terminal of the first capacitive circuit 100, that is, the output voltage of the a signal is greater than VCC +0.7V, the diode D2 is turned on; when the output voltage of the A signal is less than VCC-0.7V, the diode D1 is turned on, so that the output voltage of the A signal can be clamped between Vcc-0.7V and Vcc +0.7V by using a Vcc external power supply and a grounding terminal. Where Vcc may be 2.5V, 3.0V, etc., and the application is not limited thereto.

It should be noted that the specific circuit structure of the second peak clamp circuit may be the same as that of the first peak clamp circuit, and is not described herein again.

Optionally, in other embodiments of the present application, the adjustment of the output voltages of the signal a and the signal B may also be implemented by detecting a peak voltage of the signal a or the signal B, and adjusting the power input power of the Vin end according to the magnitude of the peak voltage. For example, a first detection threshold, a second detection threshold and a third detection threshold may be preset, where the third detection threshold is greater than the second detection threshold, and the second detection threshold is greater than the first detection threshold; the first detection threshold, the second detection threshold and the third detection threshold correspond to input power Vin1, Vin2 and Vin3 respectively, and Vin1 is greater than Vin2 and Vin2 is greater than Vin 3. Taking the signal a as an example, when the peak voltage of a exceeds the first detection threshold but does not exceed the second detection threshold, the input power Vin1 may be selected as the input power at the Vin end; when the peak voltage of a exceeds the second detection threshold but does not exceed the third detection threshold, the input power Vin2 may be selected as the input power at the Vin end; when the peak voltage of a exceeds the third detection threshold, the input power Vin3 may be selected as the input power of the Vin end; thus, the control of the output voltage of the a signal can be achieved by controlling the input power of the input signal at the Vin terminal. So that the voltage value does not exceed the preset voltage value (such as 2.5V and 3.0V).

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.