阅读说明：本技术 锁相回路装置与频率产生方法 (Phase-locked loop device and frequency generation method ) 是由 杨育哲 于 2020-04-23 设计创作，主要内容包括：锁相回路装置包含数字控制振荡器电路、时钟发生器电路系统、时间数字转换器电路以及逻辑控制电路。数字控制振荡器电路用以响应于多个数位码产生第一频率信号。时钟发生器电路系统用以根据第一频率信号产生多个第二频率信号,并根据选择信号从多个第二频率信号中选出第三频率信号与第四频率信号,以产生输出信号。时间数字转换器电路用以检测输出信号与参考信号之间的延迟差,以产生多个数位码。逻辑控制电路用以根据多个数位码产生选择信号。(The phase-locked loop device comprises a digital control oscillator circuit, a clock generator circuit system, a time-to-digital converter circuit and a logic control circuit. The numerically controlled oscillator circuit is used for responding to a plurality of digital codes to generate a first frequency signal. The clock generator circuit system is used for generating a plurality of second frequency signals according to the first frequency signal and selecting a third frequency signal and a fourth frequency signal from the plurality of second frequency signals according to the selection signal so as to generate an output signal. The time-to-digital converter circuit is used for detecting a delay difference between the output signal and the reference signal to generate a plurality of digital codes. The logic control circuit is used for generating a selection signal according to a plurality of digital codes.)

1. A phase-locked loop device, comprising:

a digitally controlled oscillator circuit for generating a first frequency signal in response to a plurality of digital codes;

the clock generator circuit system is used for generating a plurality of second frequency signals according to the first frequency signal and selecting a third frequency signal and a fourth frequency signal from the plurality of second frequency signals according to a selection signal so as to generate an output signal;

a time-to-digital converter circuit for detecting a delay difference between the output signal and a reference signal to generate the plurality of digital codes; and

the logic control circuit is used for generating the selection signal according to the plurality of digital codes.

2. The phase-locked loop device of claim 1, wherein the clock generator circuitry comprises:

a multi-phase generator circuit for generating the plurality of second frequency signals according to the first frequency signal;

a multiplexer circuit for selecting the third frequency signal and the fourth frequency signal from the plurality of second frequency signals according to the selection signal; and

the logic gate circuit is used for generating the output signal according to the third frequency signal and the fourth frequency signal.

3. The apparatus of claim 2, wherein the multiphase generator circuit is a four-phase generator circuit, and the phases of the second clock signals are sequentially 90 degrees apart.

4. The phase-locked loop apparatus as claimed in claim 1, wherein a duty cycle of said output signal is less than a duty cycle of said first frequency signal.

5. The phase-locked loop apparatus as claimed in claim 1, wherein said time-to-digital converter circuit is configured to detect a period between a rising edge of said output signal and a rising edge of said reference signal to generate a first one of said plurality of digital codes, and detect a period between a falling edge of said output signal and said rising edge of said reference signal to generate a second one of said plurality of digital codes.

6. The apparatus according to claim 1, wherein the logic control circuit is configured to predict a first rising edge of the output signal according to the digital codes, and select a signal having a falling edge that occurs earliest within a predetermined period from the plurality of second frequency signals as the third frequency signal, wherein the predetermined period is a period between the first rising edge and a rising edge of the reference signal.

7. The apparatus of claim 1, wherein the logic control circuit is further configured to select a signal having a sub-phase of the third frequency signal from the plurality of second frequency signals as the fourth frequency signal.

8. A method for generating a frequency, the method comprising:

generating a first frequency signal in response to a plurality of digital codes;

generating a plurality of second frequency signals according to the first frequency signals;

selecting a third frequency signal and a fourth frequency signal from the plurality of second frequency signals according to the selection signal to generate an output signal;

detecting a delay difference between the output signal and a reference signal to generate the plurality of digital codes; and

the selection signal is generated according to the plurality of digital codes.

9. The method according to claim 8, wherein selecting the third frequency signal and the fourth frequency signal from the plurality of second frequency signals according to the selection signal comprises:

predicting a first rising edge of the output signal from the plurality of digital codes; and

selecting a signal having a falling edge that appears earliest in a predetermined period as the third frequency signal from the plurality of second frequency signals, wherein the predetermined period is a period between the first rising edge and a rising edge of the reference signal.

10. The method of claim 8, wherein selecting the third frequency signal and the fourth frequency signal from the plurality of second frequency signals according to the selection signal further comprises:

and selecting a signal having a sub-phase of the third frequency signal from the plurality of second frequency signals as the fourth frequency signal.

Technical Field

The present application relates to phase-locked loop devices, and more particularly, to an all-digital phase-locked loop device and a frequency generation method thereof.

Background

In recent years, the all-digital phase-locked loop has gradually replaced the analog phase-locked loop due to better re-configuration, easy technology migration, self-calibration capability, and so on. In some related art, a time-to-digital converter circuit is used to evaluate the phase error of an all-digital phase-locked loop. In such techniques, to be able to correctly lock the phase, the delay time in the time-to-digital converter circuit must cover at least half a cycle of the signal generated by the digital oscillator. This results in a significant increase in hardware cost and power consumption.

Disclosure of Invention

In some embodiments, a phase-locked loop device includes a digitally controlled oscillator circuit, clock generator circuitry, a time-to-digital converter circuit, and a logic control circuit. The numerically controlled oscillator circuit is used for responding to a plurality of digital codes to generate a first frequency signal. The clock generator circuit system is used for generating a plurality of second frequency signals according to the first frequency signal and selecting a third frequency signal and a fourth frequency signal from the plurality of second frequency signals according to the selection signal so as to generate an output signal. The time-to-digital converter circuit is used for detecting a delay difference between the output signal and the reference signal to generate a plurality of digital codes. The logic control circuit is used for generating a selection signal according to a plurality of digital codes.

In some embodiments, the frequency generation method comprises the following operations: generating a first frequency signal in response to a plurality of digital codes; generating a plurality of second frequency signals according to the first frequency signals; selecting a third frequency signal and a fourth frequency signal from the plurality of second frequency signals according to the selection signal to generate an output signal; detecting a delay difference between the output signal and a reference signal to generate a plurality of digital codes; and generating a selection signal according to the plurality of digital codes.

The features, operation, and efficacy of the present application are described in detail in the preferred embodiments with reference to the figures.

Drawings

Fig. 1 is a schematic diagram of a pll device according to some embodiments of the present application;

FIG. 2A is a circuit diagram of a time To Digital Converter (TDC) circuit of FIG. 1 according to some embodiments of the present application;

FIG. 2B is a conceptual diagram illustrating the operation of the TDC circuit of FIG. 2A according to some embodiments of the present application;

FIG. 3A is a schematic circuit diagram of the clock generator circuitry of FIG. 1 according to some embodiments of the present application;

FIG. 3B is a schematic diagram illustrating some of the waveforms in FIG. 3A according to some embodiments of the present application;

FIG. 4 is a schematic diagram illustrating waveforms of the output signal and the reference signal of FIG. 1 according to some embodiments of the present application; and

fig. 5 is a flow chart of a method of frequency generation according to some embodiments of the present application.

Description of the symbols:

100: phase-locked loop device

110: digitally controlled oscillator circuit

120: clock generator circuitry

130: time-to-digital converter circuit

140: logic control circuit

150: frequency tracking circuit system

152: frequency generating circuit

154: counter circuit

156: flip-flop circuit

160: adder circuit

170: digital low-pass filter circuit

180: control circuit

CK1, CK2-1, CKR, CK2, CK3, CK 4: frequency signal

CKV: output signal

And (3) CP: duty cycle

CV: count value

CW: control character

FCW: frequency control character

FREF: reference signal

NR, NF: digital code

SC: control signal

SEL: selection signal

W1, W2, W3: control character

210: inverter circuit

220: d type flip-flop circuit

230: thermometer code edge detector circuit

D [0] to D [ L ], Q [0] to Q [ L ]: bit

T1-T6: time of day

TR, TF, TP: period of time

Td: local time

310: multiphase generator circuit

320: multiplexer circuit

330: logic gate circuit

PP: period of time

PI: during a predetermined period

500: frequency generation method

S510, S520, S530, S540, S550: operation of

Detailed Description

All words used herein have their ordinary meaning. The above-mentioned words have definitions in commonly used dictionaries, and any use of the words discussed herein that are included in the context of this patent application is intended to be exemplary only and should not be used in a manner that would limit the scope and meaning of this patent application. Likewise, this patent application is not limited to the various embodiments shown in this specification.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or the two or more elements operating or acting together. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected in some manner by at least one transistor and/or at least one active and passive component to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like are used herein to describe and distinguish between various components. Accordingly, a first component herein may also be referred to as a second component without departing from the spirit of the present patent application. For ease of understanding, similar components in the various figures will be designated with the same reference numerals.

Fig. 1 is a schematic diagram of a pll device 100 according to some embodiments of the present application. In some embodiments, the pll device 100 may be an all digital (all digital) pll. The pll device 100 comprises a digitally controlled oscillator circuit 110, a clock generator circuit system 120, a time To Digital Converter (TDC) circuit 130, a logic control circuit 140, a frequency tracking circuit system 150, an adder circuit 160, a digital low pass filter circuit 170, and a control circuit 180.

The dco circuit 110 generates the clock signal CK1 in response to the digital code NR and the digital code NF. In detail, the dco circuit 110 adjusts the clock signal CK1 according to a control signal SC generated based on the digital code NR and the digital code NF. In some embodiments, the digitally controlled oscillator circuit 110 may be implemented by a series of multi-stage delay circuits (e.g., a ring oscillator), but the present application is not limited thereto.

The clock generator circuit system 120 generates a plurality of clock signals (e.g., CK2 of FIG. 3A) according to the clock signal CK1, and selects two clock signals (e.g., CK3 and CK4 of FIG. 3A) from the plurality of clock signals according to the selection signal SEL to generate the output signal CKV. The TDC circuit 130 is coupled to the clock generator circuit system 120 to receive the output signal CKV and detect a delay difference (e.g., the period TR and the period TF in fig. 2B) between the output signal CKV and the reference signal FREF to generate the digital code NR and the digital code NF.

The logic control circuit 140 generates a selection signal SEL and a control word W2 according to the digital code NR and the digital code NF. In some embodiments, the selection signal SEL may be used to shorten the duty cycle of the output signal CKV. In some embodiments, the logic control circuit 140 may be implemented by at least one digital signal processing circuit having operational capabilities to perform the related operations described later in fig. 4.

The clock tracking circuitry 150 generates the control word W1 according to one of the clock signals CK2 (CK 2-1) generated by the clock generator circuitry 120 (FIG. 3A) to reduce the frequency error between the output signal CKV and the reference signal FREF. In some embodiments, the frequency tracking circuitry 150 includes a frequency generation circuit 152, a counter circuit 154, and a flip-flop circuit 156. The clock generation circuit 152 is triggered according to the clock signal CK2-1 to generate the clock signal CKR according to the reference signal FREF. The counter circuit 154 is triggered to generate a count value CV according to the clock signal CK 2-1. The flip-flop circuit 156 is triggered to output the counter value CV as the control word W1 according to the clock signal CKR. The above-mentioned arrangement of the frequency tracking circuit system 150 is used for example, and the present application is not limited thereto.

The adder circuit 160 adds the control word W1, the control word W2, and the clock control word FCW to generate the control word W3. The digital low pass filter circuit 170 is coupled to the adder circuit 160 to receive the control word W3 and generate the control word CW based on the control word W3. The control circuit 180 is coupled to the digital low-pass filter circuit 170 to receive the control word CW and output the control signal SC accordingly. By the above arrangement, a negative feedback control mechanism of the digitally controlled oscillator circuit 110 can be implemented. In some embodiments, each of adder circuit 160, digital low pass filter circuit 170, and control circuit 180 may be implemented by one or more digital logic circuits.

Fig. 2A is a circuit schematic diagram of the TDC circuit 130 of fig. 1 according to some embodiments of the present application. In this example, the TDC circuit 130 includes a plurality of inverter circuits 210, a plurality of D-type flip-flop circuits 220, and a thermometer code (thermometer code) edge detector circuit 230. The plurality of inverter circuits 210 are connected in series and output a plurality of bits D [0] D [ L ] in sequence according to the output signal CKV. The D-type flip-flop circuit 220 is triggered according to the reference signal FREF to generate a plurality of bits Q [0] Q [ L ] according to the plurality of bits D [0] D [ L ]. A portion of D-type flip-flop circuit 220 is configured to have an inverting output (e.g., an odd number of D-type flip-flop circuits 220). Thus, the output of the D-type flip-flop circuit 220 is inverted with respect to its input. For example, bit Q [0] is inverted to bit D [0 ]. The thermometer code edge detector circuit 230 analyzes the delay difference between the reference signal FREF and the output signal CKV according to the plurality of bits Q0-Q L to output the digital code NR and the digital code NF.

Fig. 2B is a conceptual diagram illustrating operation of the TDC circuit 130 of fig. 2A according to some embodiments of the present application. As shown in FIG. 2B, the rising edge of the output signal CKV is at time T1, the falling edge of the output signal CKV is at time T2, and the rising edge of the reference signal FREF is at time T3. There is a period TR between the time T1 and the time T3, a period TF between the time T2 and the time T3, and the difference between the period TR and the period TF is a period TP. The period TP is a duty cycle of the output signal CKV (e.g., a period from a rising edge to a falling edge).

When the output signal CKV transitions from low to high at time T1, the bits D [0] D [ L ] are sequentially switched to logic 0 or logic 1. When the output signal CKV transitions from high to low at time T2, the bits D [0] D [ L ] are sequentially switched to logic 1 or logic 0. When the reference signal FREF transitions from low to high at time T3, the D-flip-flop circuits 220 are triggered to output the bits D [0] D [ L ] as bits Q [0] Q [ L ]. Due to the delay of the plurality of inverter circuits 210, during the above-described operation, a portion of the bits Q [0] to Q [ L ] is logic value 1 and another portion of the bits Q [0] to Q [ L ] is logic value 0. By analyzing the distribution of the logic values of the bits Q0-Q L, the period TR and the period TF can be detected to analyze the delay difference between the output signal CKV and the reference signal FREF. For example, as shown in fig. 2B, the period PP of the output signal CKV can be divided into a plurality of local time Td, wherein each local time Td corresponds to 1 delay of the inverter circuit 210. Thus, by analyzing the plurality of bits Q [0] to Q [ L ], the number of local times Td corresponding to the period TR and the number of local times Td corresponding to the period TF can be obtained. In some embodiments, the thermometer code edge detector circuit 230 may analyze the plurality of bits Q [0] Q [ L ] to generate a digital code NR corresponding to the period TR and a digital code NF corresponding to the period TF. Thus, the logic control circuit 140 can obtain the information of the period TR and the period TF according to the digital code NR and the digital code NF, and accordingly generate the corresponding selection signal SEL.

Fig. 3A is a circuit schematic of the clock generator circuitry 120 of fig. 1 according to some embodiments of the present application. The clock generator circuitry 120 includes a multi-phase generator circuit 310, a multiplexer circuit 320, and a logic gate circuit 330. The multiphase generator circuit 310 generates a plurality of clock signals CK2 according to the clock signal CK1, wherein the phases of the plurality of clock signals CK2 are different from each other. In this case, the multiphase generator circuit 310 can be a four-phase generator circuit, which generates 4 clock signals CK2 according to the clock signal CK1, wherein the phases of the clock signals CK2 are sequentially different by 90 degrees (as shown in fig. 3B). In some embodiments, the duty cycle of the clock signal CK1 is the same as the duty cycle CP of each of the plurality of clock signals CK 2. In some embodiments, the multi-phase generator circuit 310 may be implemented by a plurality of flip-flop circuits and/or a plurality of logic gate circuits.

The multiplexer circuit 320 selects the clock signal CK3 and the clock signal CK4 from the clock signals CK2 according to the selection signal SEL. The logic gate circuit 330 generates the output signal CKV according to the clock signal CK3 and the clock signal CK 4. In some embodiments, the multiplexer circuit 320 can output the clock signal CK2 as the clock signal CK3 and the clock signal CK 4. In some embodiments, the multiplexer circuit 320 can output the same clock signal CK2 as the clock signal CK3 and the clock signal CK 4. Referring also to fig. 3B, fig. 3B is a schematic diagram illustrating some of the waveforms of fig. 3A according to some embodiments of the present application. In this example, the logic gate circuit 330 may be an AND (AND) gate circuit. When the clock signal CK3 and the clock signal CK4 are both high, the logic gate circuit 330 outputs the output signal CKV with high level. On the contrary, when the clock signal CK3 or the clock signal CK4 is at a low level, the logic gate circuit 330 outputs the output signal CKV having a low level. The above-described arrangement of the clock generator circuitry 120 is for example and the present application is not limited thereto.

To illustrate the operation of the logic control circuit 140 of fig. 1, referring to fig. 4, fig. 4 is a schematic diagram illustrating waveforms of the output signal CKV and the reference signal FREF of fig. 1 according to some embodiments of the present disclosure. In this example, the duty cycle of the output signal CKV is 25% and the period of the reference signal FREF is known. For example, the period of the reference signal FREF is set to 2.25 times the period PP of the output signal CKV. Thus, according to the digital code NR and the digital code NF, the logic control circuit 140 can predict the timing of the rising edge of the output signal CKV. For example, if the phase is correctly locked, the logic control circuit 140 can know that the difference between the rising edge of the output signal CKV at time T1 and the rising edge of the reference signal FREF at time T2 is 0.25 times the period PP according to the digital code NR and the digital code NF; the logic control circuit 140 knows that the difference between the rising edge of the output signal CKV at time T3 and the rising edge of the reference signal FREF at time T4 is 0.5 times the period PP. By analogy, the logic control circuit 140 may predict that the next rising edge of the output signal CKV (i.e., the rising edge corresponding to the time T5) will occur at a position (hereinafter referred to as predicted position) with a period PP that is 0.75 times different from the next rising edge of the reference signal FREF (i.e., the rising edge corresponding to the time T6). The above prediction operations are used as examples and the present application is not limited thereto. In some embodiments, the logic control circuit 140 may further consider the delay time of the circuit processing in the prediction process to improve the prediction accuracy.

After the predicted position is known, the logic control circuit 140 selects a signal having a falling edge that occurs earliest within a predetermined period PI between the predicted position and a rising edge of the reference signal FREF from the plurality of clock signals CK2 as the clock signal CK 3. Next, the logic control circuit 140 selects a signal having a sub-phase of the clock signal CK3 from the plurality of clock signals CK2 as the clock signal CK 4. In this way, the duty cycle (i.e., the period TP) of the output signal CKV can be smaller than the duty cycle CP of the clock signal CK 1.

In some related art, the duty cycle of the output signal of the digital oscillator circuit is at least 50%. In such techniques, to lock the phase, the delay time within the TDC circuit needs to be set to at least cover half the period of the output signal. As such, the number of delay circuits (e.g., the plurality of inverter circuits 210 of fig. 2A) in the TDC circuit is quite large, which results in a significant increase in hardware cost. Further, in these techniques, a delay circuit within the TDC circuit is set to operate at the frequency of the output signal of the digital oscillator circuit (typically several gigahertz (GHz)), resulting in an increase in the overall power consumption. Compared to the related art, the clock generator circuit system 120 can generate the output signal CKV with a lower duty cycle according to the clock signal CK 1. As a result, the number of delay circuits in the TDC circuit 130 can be reduced, thereby reducing hardware cost and power consumption.

In some embodiments, logic control circuit 140 includes a normalization circuit (not shown) and a selection circuit (not shown). The normalization circuit generates a control word W2 according to the digital code NR and the digital code NF, and calculates the number of the local time Td corresponding to the period TR and the number of the local time Td corresponding to the period TF in FIG. 2B. The selection circuit can calculate the predicted position according to the above information generated by the normalization circuit to generate the selection signal SEL for selecting the clock signal CK3 and the clock signal CK 4.

Fig. 5 is a flow chart of a method 500 for frequency generation according to some embodiments of the present application. In operation S510, a first frequency signal is generated in response to a plurality of digital codes. In operation S520, a plurality of second frequency signals are generated according to the first frequency signal. In operation S530, a third frequency signal and a fourth frequency signal are selected from the plurality of second frequency signals according to the selection signal to generate an output signal. In operation S540, a delay difference between the output signal and the reference signal is detected to generate a plurality of digital codes. In operation S550, a selection signal is generated according to a plurality of digital codes.

The above descriptions of the operations can refer to the above embodiments, and thus are not repeated herein. The operations of the frequency generation method 500 are merely examples and need not be performed in the order of the examples. Various operations under the frequency generation method 500 may be added, substituted, omitted, or performed in a different order as appropriate without departing from the manner of operation and scope of various embodiments of the present patent application. Alternatively, one or more operations under the frequency generation method 500 may be performed simultaneously or partially simultaneously.

In summary, the phase-locked loop device and the frequency generating method in some embodiments of the present application can reduce the duty cycle of the output signal of the digitally controlled oscillator circuit to reduce the time span required to be covered by the TDC circuit. Thus, hardware cost and power consumption can be reduced.

Although the embodiments of the present application have been described above, these embodiments are not intended to limit the present application, and those skilled in the art can apply variations to the technical features of the present application according to the explicit or implicit contents of the present application, and all such variations may fall within the scope of the patent protection sought by the present application, in other words, the scope of the patent protection sought by the present application shall be subject to the protection scope defined by the claims of the present application.