阅读说明：本技术 用于改善锁定时间的装置和方法 (Apparatus and method for improving lock time ) 是由 W·李 M·纳斯罗拉西 K·恩谷因 于 2018-06-29 设计创作，主要内容包括：本发明提供一种用于改善锁相环的锁定时间的装置,其中,该装置包括：环形振荡器,其包括至少两个延迟级,其中每个延迟级具有可控制的延迟；以及多相频率监测器,耦接到环形振荡器以监测环形振荡器的至少两个延迟级的输出处的频率。(The invention provides a device for improving the locking time of a phase-locked loop, wherein the device comprises: a ring oscillator comprising at least two delay stages, wherein each delay stage has a controllable delay; and a multi-phase frequency monitor coupled to the ring oscillator to monitor a frequency at an output of at least two delay stages of the ring oscillator.)

1. An apparatus, comprising:

an oscillator comprising at least two delay circuits coupled together in a ring, wherein each delay circuit has an adjustable propagation delay;

a first counter coupled to an output of a first delay circuit of the at least two delay circuits; and

a second counter coupled to an output of a second delay circuit of the at least two delay circuits, wherein the delay of the at least two delay circuits is adjusted according to the outputs of the first and second counters.

2. The apparatus of claim 1, wherein each delay circuit comprises a first circuit to control a first delay of the delay circuit and a second circuit to control a second delay of the delay circuit, wherein the first delay is greater than the second delay.

3. The apparatus of claim 1, comprising:

a first timing circuit coupled to an output of the first counter; and

a second timing circuit coupled to an output of the second counter.

4. The apparatus of claim 3, comprising a frequency divider coupled to the first and second timing circuits, wherein the frequency divider provides a clock to sample inputs of the first and second timing circuits.

5. The device of claim 1, comprising logic to generate an average of outputs of the first and second timing circuits.

6. The apparatus of claim 1, comprising a frequency divider coupled to an output of the oscillator.

7. The apparatus of claim 6, comprising one of a phase detector, a phase frequency detector, or a time-to-digital converter coupled to an output of the oscillator.

8. The apparatus of claim 7, comprising a lock detector coupled to an output of the phase frequency detector.

9. The apparatus of claim 8, comprising a loop filter to receive an output of the phase frequency detector, wherein an output of the loop filter is coupled to the oscillator.

10. The apparatus of claim 9, wherein an output of the loop filter is to adjust a delay of each delay circuit by a first delay amount, wherein outputs of the first and second counters are to adjust a delay of each delay circuit by a second delay amount, wherein the first delay amount is shorter than the second delay amount.

11. An apparatus, comprising:

a ring oscillator comprising at least two delay stages, wherein each delay stage has a controllable delay; and

a multi-phase frequency monitor coupled to the ring oscillator for monitoring frequencies at outputs of at least two delay stages of the ring oscillator.

12. The apparatus of claim 11, wherein the polyphase frequency monitor comprises at least two counters that count respective frequencies of the at least two delay stages.

13. The apparatus of claim 11, comprising logic to generate an average frequency based on respective frequencies of the at least two delay stages.

14. The apparatus of claim 13, wherein the logic is to adjust the delay of the at least two delay stages of the ring oscillator according to the average frequency.

15. The apparatus of claim 11, wherein each delay stage comprises a first circuit to control a first delay of the delay stage and a second circuit to control a second delay of the delay stage, wherein the first delay is greater than the second delay.

16. The apparatus of claim 11, wherein the ring oscillator is part of a phase locked loop.

17. A system, comprising:

a memory;

a processor coupled to the memory, wherein the processor comprises a phase locked loop comprising the apparatus of any of claims 1 to 10; and

a wireless interface allowing the processor to communicate with another device.

18. A system, comprising:

a memory;

a processor coupled to the memory, wherein the processor comprises a phase locked loop comprising the apparatus of any of claims 11 to 15; and

a wireless interface allowing the processor to communicate with another device.

19. An apparatus, comprising:

means for enabling a first electrical loop comprising an oscillator and a multi-phase monitor coupled to the oscillator;

means for determining a first code to adjust a propagation delay of a delay circuit of the oscillator, wherein the first code is determined from one or more outputs of the multi-phase monitor;

means for applying the first code to the delay circuit;

means for freezing the first code when a lock indicator indicates that the frequency of the oscillator is substantially close to a target frequency;

means for disabling the first electrical loop; and

means for enabling a second electrical loop comprising a frequency divider, a phase detector, a filter, and an oscillator, wherein the second electrical loop provides a second code to the oscillator to adjust a delay of a delay circuit.

20. The device of claim 19, comprising means for monitoring phase error and determining whether to increase or decrease a value of the second code.

21. A method, comprising:

enabling a first electrical loop comprising an oscillator and a multi-phase monitor coupled to the oscillator;

determining a first code to adjust a propagation delay of a delay circuit of the oscillator, wherein the first code is determined from one or more outputs of the multi-phase monitor;

applying the first code to the delay circuit;

freezing the first code when a lock indicator indicates that the frequency of the oscillator is substantially close to a target frequency;

disabling the first electrical loop; and

enabling a second electrical loop comprising a frequency divider, a phase detector, a filter, and an oscillator, wherein the second electrical loop provides a second code to the oscillator to adjust a delay of the delay circuit.

22. The method of claim 21, comprising: monitoring phase error and determining whether to increase or decrease the value of the second code.

Background

In clock systems using a ring oscillator based phase locked loop, multi-band oscillators are commonly used for power equalization, dynamic range, and adjustment range for temperature drift. However, existing clock sources have long lock times, which increases the delay in entering a low power state or the delay that exists in entering and exiting from a low power state.

Drawings

Embodiments of the present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

Figure 1A illustrates a ring oscillator capable of coarse/fine grain delay adjustment according to some embodiments.

Fig. 1B illustrates a graph showing frequency and code for different coarse and fine granularity adjustments, in accordance with some embodiments.

Fig. 2 illustrates a counter-based frequency measurement device according to some embodiments of the present disclosure.

FIG. 3 illustrates a clock system having a multi-phase frequency measurement device coupled to a ring oscillator according to some embodiments of the present disclosure.

Fig. 4 illustrates a Phase Locked Loop (PLL) having an apparatus for improving lock time according to some embodiments of the present disclosure.

Fig. 5A shows a timing diagram illustrating the lock time of a conventional PLL.

Fig. 5B illustrates a timing diagram showing reduced lock times for a PLL using a multi-phase frequency measurement device, in accordance with some embodiments.

Fig. 6 illustrates a PLL having an apparatus for improving lock time according to some embodiments of the present disclosure.

FIG. 7 illustrates a flow diagram of a method for reducing lock time, according to some embodiments.

Fig. 8 illustrates a smart device on chip or computer system or SoC (system on a chip) having an apparatus for improving lock time according to some embodiments of the present disclosure.

Detailed Description

To save power, a narrow tuning range of the ring oscillator for the Phase Locked Loop (PLL) is needed, which is just enough to cover voltage and temperature (e.g., -40 to 125 ℃) drift. To cover a wide frequency range, coarse grain tuning is used depending on the application. For example, the coarse-grained adjustment range of core clocks for a processor, such as a general purpose processor, may be in the range of 1.6GHz to 4.0GHz, while the fine-grained adjustment range may be in the range of +/-10%. Herein, the term "coarse-grained code" refers to a digital code used to calibrate or adjust an electrical parameter, such as propagation delay through a circuit element, by a coarse-grained amount.

Conversely, the term "fine-grained code" refers to a digital code used to calibrate or adjust an electrical parameter in a smaller amount than the amount of coarse-grained used by a coarse-grained code. Typically, coarse-grained code is applied to the circuit elements before fine-grained code is applied. The term "adjusting" or "calibrating" with reference to the coarse/fine property generally refers to adjusting the value of a coarse-grained code or a fine-grained code. Herein, the term "code" refers to a digital signature of two or more bits.

Calibrating the coarse/fine granularity adjustment of the ring oscillator to select the correct frequency band or target frequency band may directly affect the lock time of the phase locked loop PLL (or frequency locked loop FLL). The lock time is a performance parameter that indicates when the PLL or FLL has obtained phase and/or frequency lock with respect to the reference clock. In general, when a PLL is declared to be locked, the output of the PLL may be safely used by downstream logic. The lock-on time may affect how often the system enters a low power mode (e.g., sleep state) and returns to an active mode (e.g., operational state) to conserve power. For example, after the PLL declares a successful lock, an operational state or an active state will be declared. In some low power states, the PLL supply voltage may be reduced or shut down, causing the PLL to lose lock. To regain lock, the PLL must begin phase and frequency adjustment until lock is again achieved. This process is time consuming and directly affects the speed at which the processor enters an operational state from a low power consumption state.

When the adjustment process of adjusting coarse/fine-grained codes is accelerated to improve the lock time, a loss of precision may result. Inaccuracies in the frequency adjustment due to acceleration of coarse/fine grain calibration may result in long lock times (e.g., periodic slips) or, in extreme cases, inability to lock.

Various embodiments improve lock time by multiphase frequency measurement. Some embodiments describe an apparatus that shortens the frequency measurement time with the same accuracy (as in the case of long or conventional frequency measurement times) by utilizing the intermediate phase available in the ring oscillator. For example, the intermediate phases from various delay stages or elements in the ring oscillator are monitored to determine the frequency of the oscillator. This frequency information from the intermediate phase is then used to calibrate the coarse-grained code, which results in a faster adjustment of the oscillator frequency towards the target frequency. After the coarse-grained code is determined, the fine-grained code is adjusted to fine-tune the oscillator frequency to achieve the target or desired frequency. Some embodiments directly illustrate the improvement in lock time proportional to the number of stages in the ring oscillator. Since the lock time is mainly determined by coarse grain adjustment, the shortened frequency measurement time can directly shorten the lock time in the PLL. Other technical effects will become apparent from the various embodiments and the accompanying drawings.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Note that in the respective drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and/or have arrows at one or more ends to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, these lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic unit. Any represented signal may actually comprise one or more signals that may propagate in either direction and may be implemented with any suitable type of signal scheme, as dictated by design needs or tendencies.

Throughout the specification and in the claims, the term "connected" refers to a direct connection, such as an electrical, mechanical, or magnetic connection, between the connected objects, without any intervening devices. The term "coupled" refers to a direct or indirect connection through one or more passive or active intermediary devices, such as a direct electrical, mechanical, or magnetic connection or indirect connection between the objects being connected. The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a", "an" and "the" includes plural forms. The meaning of "in.

The term "scaling" generally refers to converting a design (schematic and layout) from one processing technique to another and then reducing its layout area. The term "scaling" also generally refers to reducing the layout and equipment within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up-i.e., respectively scaling down or amplifying) the signal frequency relative to another parameter (e.g., the power supply level). The terms "substantially", "close", "approximately", "close" and "approximately" typically mean within +/-10% of a target value.

Unless otherwise specified the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

For the purposes of this disclosure, the phrases "a and/or B" and "a or B" refer to (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" refers to (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).

In the description and claims, the terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like (if any) are used for descriptive purposes and not necessarily for describing permanent relative positions. For the purposes of this disclosure, the terms "spin" and "magnetic moment" are used equally. More strictly speaking, the direction of the spin is opposite to the direction of the magnetic moment, and the charge of the particle is negative (for example in the case of electrons).

For purposes of example, the transistors in the various circuits and logic blocks described herein are Metal Oxide Semiconductor (MOS) transistors or derivatives thereof, where MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or MOS transistor derivatives further include Tri-Gate and FinFET transistors, cylindrical fully-wrapped-Gate transistors, tunneling fets (tfets), square or rectangular ribbon transistors, ferroelectric fets (fefets), or other devices that perform a transistor function, such as carbon nanotubes or spintronic devices. The symmetrical source and drain terminals of the MOSFET are the same terminal and may be used interchangeably herein. TFET devices, on the other hand, have asymmetric source and drain terminals. Those skilled in the art will appreciate that other transistors, such as bipolar junction transistors (BJTs PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the present disclosure.

It should be noted that those elements of fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Fig. 1A illustrates a ring oscillator 100 capable of coarse/fine grain delay adjustment according to some embodiments. Fig. 1A shows an example of a coarse/fine adjustment architecture, where coarse adjustment sets the frequency target and fine adjustment adjusts the frequency by capacitive adjustment based on the operating environment.

In this example, ring oscillator 100 has five delay stages or elements 101. Each delay stage includes a circuit knob (circuit knobs) to adjust its propagation delay (e.g., the delay from input "in" to output "out") by a coarse-grain metric and a fine-grain metric. In some embodiments, the delay stage 101 includes a plurality of inverters (e.g., 101) coupled in parallel to each other_a1To 101_aN) And the inverter may be enabled or disabled to increase or decrease the drive strength of the delay stage. In some embodiments, each inverter (e.g., 101) may be enabled or disabled by turning on or off devices MP and MN coupled to the inverter_a1). The devices receive a coarse-grained code that determines the device to be turned on or off, and thus the enabled inverter. Here, the coarse-grained adjustment device is an MP₁To MP_NAnd MN₁To MN_N. These devices are coupled in series with the transistors of the inverter. For example, the p-type transistor of the inverter is coupled in series with the MP device, and the n-type transistor of the inverter is coupled in series with the MN device. In some embodiments, the capacitive device C₁To C_NPerforming fine-grained adjustments, capacitive device C₁To C_NUsing controllable switches SW₁To SW_NCoupled to the output "out" of the delay stage. The fine code is applied to the switch SW₁To SW_NWhich couples or decouples the capacitive device to the output node.

In some embodiments, switch SW₁To SW_NImplemented as devices such as n-type transistors, p-type transistors, or a combination of both. In some embodiments, the capacitive device is implemented as a transistor configured as a capacitor, a metal capacitor, or a hybrid of a transistor and a metal capacitor. The various embodiments are not limited to a particular architecture of the ring oscillator. For example, instead of MP₁To MP_NAnd MN₁To MN_NEach delay stage of the ring oscillator may include a large capacitance device for coarse tuning and a small capacitance device for fine tuning, andto add a capacitive device to the output node using digitally controlled switches. Although a ring oscillator 100 having five delay stages is shown, a ring oscillator may have at least two delay stages coupled together in a ring. The maximum number of delay stages may be based on the target frequency requirement.

Fig. 1B illustrates a graph 120 showing frequency and code for different coarse and fine granularity adjustments, in accordance with some embodiments. The figure shows that the coarse grain setting selection is made by the code₁To code_NThe identified main frequency range, and then fine-grained adjustments achieve the operating frequency target of the selected coarse code to compensate for process, voltage, and temperature (PVT) drift. As described above, PLL lock time performance is directly affected by coarse/fine granularity code selection. For example, slowly selecting a target coarse-grained code for a target frequency may slow the PLL lock time. Conversely, attempting to quickly select coarse grain codes may cause PLL loop stability problems and other inaccuracies.

Fig. 2 illustrates a counter-based frequency measurement device 200 according to some embodiments of the present disclosure. In some embodiments, the circuitry of apparatus 200 is coupled to each delay stage of oscillator 101. For example, the output of the delay stage 101 of the oscillator 100 is coupled to a counter 202, and the output of another delay stage 101 of the oscillator 100 is coupled to another counter 202 (not shown). In some embodiments, the counter 202 is an incrementing counter that counts the rising and/or falling edges of a signal at a node "out" of a delay stage coupled to the counter. Thus, the counter 202 determines the frequency of the output of the delay stage. In other embodiments, the counter 202 may be a down counter that starts counting down from a known value. Any suitable counter may be used to implement counter 202.

In some embodiments, the output of counter 202 is sampled by flip-flop 203, where flip-flop 203 uses a clock that is slower than the reference clock of the PLL. For example, a divider 205 is provided, which divider 205 divides the reference clock RefClk by a factor "N" and provides the divided clock Clk to the flip-flop 203 to sample the output of the counter 202. By sampling 202 the output of the counter 202 using the divided clock, a filtering mechanism is introduced. In this way, a more accurate frequency is determined. The output of flip-flop 203 is the measured frequency of the signal generated by the delay stage of the oscillator.

In various embodiments, a Finite State Machine (FSM)204 is provided that receives measured frequency data from the outputs of two or more delay stages of a ring oscillator and uses the data to determine an average frequency. FSM204 then compares the average frequency to the target frequency to determine whether to increase or decrease the value of the coarse-grained code. The coarse-grained code is then provided to all delay stages of the ring oscillator for coarse-grained adjustment. In one example, the measurement accuracy is 2/N (f)_REF) Wherein f is_REFIs the frequency of the reference clock. In a ring oscillator with a minimum band separation of 20MHz, the required accuracy is 10 MHz. Using a 100MHz reference clock, N is 20. With a binary search algorithm designed with a 10-bit coarse-grained adjustment, finding the best frequency band would take 200 clock cycles. This may result in the consumption of a lock time of 2 microseconds. In some embodiments, FSM204 applies the flowchart of fig. 7 to implement a fast lock architecture.

Fig. 3 illustrates a clock system 300 having a multi-phase frequency measurement device 301 coupled to a ring oscillator 100 according to some embodiments of the present disclosure.

By tapping the middle nodes of the oscillator 100, more edges (information) are available. In some embodiments, for each delay stage, multi-phase frequency monitor 301 has the structure shown in fig. 2 (minus FSM204 and the oscillator delay stage). By tapping on different phases, the frequency measurement accuracy is improved by a factor of M. For example, for the same number of reference clock cycles, the improved accuracy is (2/(MN)) f_REF. To achieve the same accuracy, as described above, the lock time is reduced by a factor of M according to some embodiments. In some embodiments, the results from the various counters coupled to their respective delay stage taps are averaged by FSM 304/204. The averaging results improve accuracy.

In order to illustrate how the accuracy is improved,suppose the oscillation frequency (fosc) is 40.4f_REF. In the original scheme of counting the final output of the oscillator 100, the ideal measurement is "41" after one reference clock cycle. However, in FIG. 3, it is assumed that a 5-stage oscillator is used, and the result of counting the frequency at the output of each delay stage is [ 4141404040 ]]. The average result was "40.4". By tapping off different phases, fractional accuracy is improved. Further optimization can be done by measuring the rising and falling edges to reduce the coarse-grained lock time by a factor of 2, e.g. by a factor of 10. In this way, the lock time of the processor is improved, thereby increasing the system response speed. The improved system responsiveness may maximize the chance of entering a low power state when the clock is turned off.

Fig. 4 illustrates a Phase Locked Loop (PLL)400 having means for improving lock time according to some embodiments of the present disclosure. In some embodiments, PLL 400 includes a Phase Detector (PD), a Phase Frequency Detector (PFD), or a time-to-digital converter (TDC)401, a control engine 402, a Digital Loop Filter (DLF)403, oscillator 100, a polyphase frequency monitor 404, a frequency divider 405, a lock detector 406, and a sigma-delta modulator 407 coupled together as shown. The PD, PFD 401 generates up/down pulses or signals according to the phase difference between the reference clock (RefClk) and the feedback clock (FbClk). PD is a circuit that generates up and down signals that represent the phase difference between RefClk and FbClk. The PFD may generate up and down pulses that contain the phase and frequency difference between RefClk and FbClk.

The control engine 402 receives the up/down pulses and generates digital codes for coarse and fine granularity adjustments. The digital code is then filtered by a Digital Loop Filter (DLF). The outputs of the DLF are coarse F and fine F, which are used to adjust the delay of each delay stage of the oscillator 100. Divider 405 receives the output "oscillator clock" of oscillator 100 and divides it to generate the feedback clock (FbClk). In some embodiments, the sigma-delta modulator 407 is used to generate a divide ratio N for the divider. The division ratio N may be an integer or a fraction.

Here, two feedback loops are shown. The first feedback loop is a short loop and includes the control engine 402, the DLF403, the oscillator 100, and the multi-phase frequency monitor 404. The second feedback loop is a longer loop and includes the PD or PFD, 401, the control engine 402, the DLF403, the oscillator 100 and the frequency divider 405. In some embodiments, the first feedback loop is enabled when the PLL wakes up from a reset or low power state that requires PLL relock. The first feedback loop is used to quickly determine a coarse code that causes the oscillator output to approach the target frequency. In the first feedback loop, the divider 405 and the PFD 401 are bypassed to achieve a faster response. In one such embodiment, the output upstream and downstream from the PFD 401 are ignored by the control engine 402 and the output measurements from the polyphase frequency monitor 404 are used to determine the coarse grain codes. In some embodiments, the digital loop filter 403 may also be bypassed in the first feedback loop.

In some embodiments, the multiphase frequency monitor 404 monitors the output out of each delay stage of the oscillator 100₁To out_NAnd determines the clock frequency at the output of each delay stage. The frequencies from each delay stage are then averaged by FSM 304 (here part of multi-phase frequency monitor 404) and the averaged output is a measurement. The output measurements are then received by the control machine 402, which adjusts the coarse and/or fine grain codes to speed up the lock time. The lock detector outputs a lock indicator based on the up/down signal and/or the reference clock (RefClk) and the feedback clock (FbClk).

After FSM 304 determines that the oscillator clock frequency is close to the target frequency (e.g., within 10%), the first feedback loop is disabled and the second feedback loop is enabled. For example, the control engine 402 now uses the up and down signals to control the coarse and fine grain codes and bypass the output measurements. The switching mechanism may be implemented by a multiplexer (not shown). Since the coarse-grained code has already been determined by the first feedback loop, the second feedback loop uses the coarse-grained code produced by the first feedback loop to perform fine-grained adjustments.

In some embodiments, PD or PFD 401 is replaced by a time-to-digital converter (TDC)401 that generates a digital bitstream indicative of the phase error between RetClk and FbClk. The digital bit stream replaces the up/down signal. TDC is a circuit that converts the phase error between RefClk and FbClk to a digital output. The digital output may be in the form of up/down signals, or may be encoded in other formats. These other formats may include an output that may be a real number representing a phase error. For example, real numbers may indicate that RefClk leads FbClk by 10 ps. In another example, another format may indicate numbers such as RefClk leading FbClk (e.g., output ═ 1) or RefClk lagging FbClk (e.g., output ═ 0).

In some embodiments, the lock detector 406 receives a digital output TDC 401 to determine when a lock is indicated. For example, lock detector 406 then indicates lock when the digital output indicates an error below a threshold (e.g., predetermined or programmable). In some embodiments, when the first feedback loop is enabled, the control machine 402 ignores the output of the TDC 401 and uses the output measurement to adjust the coarse grain code (which is then filtered by the digital loop filter 403). Once the target coarse-grained code is determined, the first feedback loop is disabled and the control machine 402 then uses the digital output of the TDC 401 to adjust the fine-grained code.

Fig. 5A shows a timing diagram 500 illustrating the lock time of a conventional phase locked loop. Fig. 5B illustrates a timing diagram 520 showing reduced lock time for a phase locked loop using a multi-phase frequency measurement device, in accordance with some embodiments. In timing diagram 500, the lock time begins after reset (e.g., a signal that causes the PLL to begin locking). After reset, the PLL uses its conventional feedback loop to determine the coarse grain code. Once the coarse-grained code is determined, the "done" signal is determined and the fine-grained code is set for final locking of the PLL. In the timing diagram 500, a search from coarse-grained codes begins immediately after reset using a short feedback loop. Thus, determining coarse-grained code is faster (e.g., 10 times faster) than in the conventional case of timing diagram 500. Once the coarse-grained code is determined, the signal is determined to be "complete" and the first feedback loop (or short feedback loop) is disabled and the second feedback loop (or normal long feedback loop) is enabled to determine the fine-grained code. Once the fine-grained code is set (e.g., within a tolerance), a lock signal is determined.

Fig. 6 illustrates a PLL 600 having means for improving lock time according to some embodiments of the present disclosure. The PLL 600 comprises a PD, PFD or TDC 601, a loop filter 603, an oscillator 100, a polyphase frequency monitor 404, a frequency divider 405, a lock detector 606, and a sigma-delta modulator 407. The PD, PFD, or TDC 601 generates a phase error from a phase difference between a reference clock (RefClk) and a feedback clock (FbClk). As discussed with reference to fig. 4, when PD, PFD are used, an up pulse or signal and a down pulse or signal are generated to indicate phase error. Also, when the TDC 601 is used, a digital bit stream will be generated to indicate the phase error. In fig. 6, a TDC 601 is used to illustrate the apparatus. The loop filter 602 filters the phase error and generates a fine-grained code. In this case, the coarse-grained code is determined prior to the fine-grained code setting, within its tolerance range. The first feedback loop here is much shorter than in fig. 4 and is used to determine the coarse-grained code. The first feedback loop includes the oscillator 100 and the polyphase frequency monitor 404. The second feedback loop includes the PD or TDC 601, the loop filter 602, the oscillator 100, and the frequency divider 405. In this embodiment, the coarse grain code does not pass through the loop filter 602. Once the coarse-grained code is determined, the first feedback loop is disabled and the coarse-grained code is locked. The PLL then uses a conventional long loop (or second loop) to adjust for the fine-grained code. When the fine grain code approaches a predetermined tolerance level, the phase error is small enough for the clock detector 606 to assert lock.

Fig. 7 illustrates a flow diagram 700 of a method for reducing lock time, in accordance with some embodiments. At block 701, the PLL begins to lock (e.g., after reset, after clock power down). At block 702, a first feedback loop (or short loop) is enabled to determine a coarse-grained code. At block 703, FSM 304 determines whether the coarse-grained code causes the oscillation frequency to approach the target frequency. For example, as shown in FIG. 1B, a coarse-grained code is selected that results in a target frequency substantially in the middle of the range of coarse-grained codes. If the coarse-grained code is still far away and the propagation delay of the delay stage needs to be further adjusted by the coarse-grained code, the process continues to block 702 and another coarse-grained code is selected. In another embodiment, when the target frequency is approximately in the middle of the range of coarse-grained codes, the coarse-grained codes are frozen as shown in block 704. The process then continues to block 705 where a second feedback loop (or normal feedback mode) is enabled and the fine grain code is set in block 705. The PLL declares lock when the fine-grained code is jittered near the target frequency.

Fig. 8 illustrates a smart device or computer system or SoC (system on a chip) having an apparatus for improving lock time according to some embodiments of the present disclosure. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, mobile phone or smartphone, wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in the computing device 1600.

In some embodiments, according to some embodiments discussed, the computing device 1600 includes a first processor 1610 with means for improving lock time. Other blocks of the computing device 1600 may also include means for improving lock time, according to some embodiments. Various embodiments of the present disclosure may also include a network interface within 1670, such as a wireless interface, so that system embodiments may be incorporated into a wireless device, such as a cellular telephone or personal digital assistant.

In some embodiments, processor 1610 (and/or processor 1690) may include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. Processing operations include operations related to I/O (input/output) of a human user or other device, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In some embodiments, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. The audio functions may include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

In some embodiments, computing device 1600 includes a display subsystem 1630. Display subsystem 1630 represents hardware (e.g., display device) and software (e.g., driver) components that provide a visual and/or tactile display for user interaction with computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide the display to the user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

In some embodiments, computing device 1600 includes I/O controller 1640. I/O controller 1640 represents hardware devices and software components related to user interaction. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. In addition, I/O controller 1640 illustrates connection points for additional devices that connect to computing device 1600, through which a user may interact with the system. For example, devices that may be connected to the computing device 1600 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or key device, or other I/O devices or other devices used with a particular application such as a card reader.

As described above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. In addition, audio output may be provided instead of, or in addition to, display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which may be managed at least in part by I/O controller 1640. Additional buttons or switches may also be present on computing device 1600 to provide I/O functions managed by I/O controller 1640.

In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that can be included in computing device 1600. The input may be part of direct user interaction, as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting display for brightness detection, applying a flash for a camera, or other features).

In some embodiments, computing device 1600 includes power management 1650 that manages battery power usage, battery charging, and features related to power saving operations. Memory subsystem 1660 includes storage devices for storing information in computing device 1600. The memory may include non-volatile (state does not change if power to the storage device is interrupted) and/or volatile (state is indeterminate if power to the storage device is interrupted) storage devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions by computing device 1600.