阅读说明：本技术 一种带状态监测的可配置一致性验证系统 (Configurable consistency verification system with state monitoring function ) 是由 李峰 朱巍 吴珊 宁永波 菅陆田 谢军 刘佳季 于 2019-09-09 设计创作，主要内容包括：本发明涉及芯片验证技术领域,具体涉及一种带状态监测的可配置一致性验证方法。本发明通过以下技术方案得以实现的：一种带状态监测的可配置一致性验证系统,包含片上网络以及片上网络连接的核组,每个所述核组包含核心、存储控制器和访存一致性处理部件；所述核心用于生成与发送激励；所述访存一致性处理部件接收来自所述核心发送来的激励并从所述存储控制器中取得结果返还至所述核心；所述核心还用于对所述结果进行验证；还包含动态监测模块。本发明的目的是提供一种带状态监测的可配置一致性验证方法,不仅能快速灵活的构建Cache一致性验证环境,且能动态实时的监测各个模块的状态。(The invention relates to the technical field of chip verification, in particular to a configurable consistency verification method with state monitoring. The invention is realized by the following technical scheme: a configurable consistency verification system with state monitoring comprises a network on chip and core groups connected with the network on chip, wherein each core group comprises a core, a storage controller and a memory access consistency processing component; the core is used for generating and sending excitation; the access consistency processing component receives the excitation sent by the core and obtains the result from the storage controller and returns the result to the core; the core is further used for verifying the result; also included is a dynamic monitoring module. The invention aims to provide a configurable consistency verification method with state monitoring, which can quickly and flexibly construct a Cache consistency verification environment and can dynamically monitor the state of each module in real time.)

1. A configurable consistency verification system with state monitoring comprises a network on chip and core groups connected with the network on chip, wherein each core group comprises a core, a storage controller and an access consistency processing component; the core is used for generating and sending excitation; the access consistency processing component receives the excitation sent by the core, obtains the result from the storage controller and returns the result to the core; the core is further used for verifying the result; the system also comprises a dynamic monitoring module, wherein the dynamic monitoring module comprises a core monitoring module, a storage control monitoring module and a consistency protocol processing part monitoring module.

2. The configurable consistency verification system with status monitoring as claimed in claim 1, wherein: the number of the core groups is two or more, and the two or more core groups are connected to the network on chip together.

3. The configurable consistency verification system with status monitoring as claimed in claim 1, wherein: the dynamic monitoring module comprises two monitoring contents, namely self-state real-time monitoring and transmission protocol real-time monitoring.

4. The configurable consistency verification system with status monitoring as claimed in claim 1, wherein: the core and the storage controller are devices to be tested or virtual models, and the access consistency processing component can only be designed to be tested.

5. A verification method of a configurable consistency verification system with status monitoring as claimed in any one of claims 1 to 4, characterized by comprising the steps of: s1, a test environment building step; writing a virtual model of the core and the storage controller, and configuring parameters according to a verification target; s2, excitation generation and result checking; the core generates excitation data and sends the excitation data to the access consistency processing component, the access consistency processing component acquires a result from the storage controller and sends the result back to the core, and the core verifies the result; s3, dynamic monitoring; the dynamic monitoring of the core, the access consistency processing component and the storage controller comprises the dynamic monitoring of the states of the three components and the dynamic monitoring of the transmission protocols among the components.

6. The verification method of the configurable consistency verification system with status monitoring as claimed in claim 5, wherein: the step of S1 and the step of building the test environment specifically comprise the following steps: s10, learning the performance, the architecture and the characteristics of the target to be tested; s11, packaging similar modules, namely packaging the modules with similar structure and function; and S12, a configuration step, namely carrying out parameterization configuration on the core and the storage controller.

7. The verification method of the configurable consistency verification system with status monitoring as claimed in claim 6, wherein: and for each module in the core and the storage controller, a uniform model writing mode is adopted.

Technical Field

The invention relates to the technical field of chip verification, in particular to a configurable consistency verification method with state monitoring.

Background

With the continuous deepening of computer architecture research and the rapid development of integrated circuit design technology, the frequency of processors is greatly improved, and in order to further improve the performance of the processors, multi-core parallel becomes an important development direction for processor development. Although the memory technology is continuously improved, the indexes such as frequency, capacity, read-write speed and the like of the memory can not meet the performance requirement of the processor far, and the problem of a memory wall is generated.

In order to effectively alleviate the problem of a memory wall, a multi-level Cache is commonly added in a processor core at present, so that the memory access speed of the processor core is close to the operation speed, and the accessible space is not reduced, thereby effectively improving the performance.

For example, in the technical solution disclosed in chinese patent document No. CN200810246665.5, a distributed shared storage algorithm is used in one of the steps. In the prior art, a multi-core parallel processor often adopts the distributed shared storage technology. In the technology, the Cache in each processor core can share data with the memory, so that the method is convenient and efficient, and the problem of data consistency among a plurality of cores is caused.

Therefore, a Cache consistency protocol suitable for the overall architecture and performance index of the processor must be designed to uniformly manage data in the Cache and the main memory of each core, and the performance of the processor is improved on the premise of ensuring the access correctness.

Due to the fact that the architectures of the processors are different, performance indexes are emphasized, and the innovation of the network-on-chip structure is added, the high efficiency, the correctness and the stability of a Cache consistency protocol are important in a multi-core processor system. Furthermore, the verification of the Cache consistency protocol can run through the development of the whole processor, and higher requirements are provided for the aspects of rapid environment construction, dynamic real-time error reporting, reusable excitation and the like.

Disclosure of Invention

The invention aims to provide a configurable consistency verification method with state monitoring, which can quickly and flexibly construct a Cache consistency verification environment and can dynamically monitor the state of each module in real time.

A configurable consistency verification system with state monitoring comprises a network on chip and core groups connected with the network on chip, wherein each core group comprises a core, a storage controller and a copy consistency processing component;

the core is used for generating and sending excitation;

the copy consistency processing part receives the excitation sent by the core and obtains the result from the storage controller and returns the result to the core;

the core is further used for verifying the result;

the system also comprises a dynamic monitoring module, wherein the dynamic monitoring module comprises a core monitoring module, a storage control monitoring module and a consistency protocol processing part monitoring module.

Preferably, the number of the core groups is two or more, and the two or more core groups are connected to the network on chip together.

Preferably, the dynamic monitoring module includes two monitoring contents, which are real-time monitoring of self-status and real-time monitoring of transmission protocol.

Preferably, the core and the storage controller are designed to be tested or virtual models, and the copy consistency processing unit is only designed to be tested.

A verification method of a configurable consistency verification system with state monitoring is characterized by comprising the following steps:

s1, a test environment building step;

writing a virtual model of the core and the storage controller, and configuring parameters according to a verification target;

s2, excitation generation and result checking;

the core generates excitation data and sends the excitation data to the copy consistency processing component, the copy consistency processing component acquires a result from the storage controller and sends the result back to the core, and the core verifies the result;

s3, dynamic monitoring; the dynamic monitoring of the core, the copy consistency processing component and the storage controller comprises the dynamic monitoring of the states of the three components and the dynamic monitoring of the transmission protocols among the components.

Preferably, the step of S1 and the step of building a test environment specifically include the following steps:

s10, a step of learning the target to be measured,

learning the performance, architecture and characteristics of the target to be tested;

s11, packaging the similar module,

packaging modules with similar structural functions;

s12, a configuration step, wherein,

and carrying out parameterized configuration on the core and the memory controller.

As the optimization of the invention, a uniform model writing mode is adopted for each module in the core and the storage controller. Preferably, in S02, the excitation rule making step, the test result is a result with error and a result without error.

In summary, the invention has the following beneficial effects:

according to the technical scheme, in the process of processor development, consistency verification environments with different emphasis points can be quickly constructed according to verification targets at different stages, and due to the fact that the test excitation has good transportability, the workload of development of the test excitation is greatly reduced.

In addition, because each module is added with dynamic state monitoring, error reporting becomes efficient and simple, verification efficiency is greatly improved, and especially debugging time of large-scale high-strength test excitation can be greatly shortened. Detailed Description

Description of the drawings:

FIG. 1 is a schematic diagram of the first embodiment.

The specific implementation mode is as follows:

the present invention will be described in further detail with reference to the accompanying drawings.

The present embodiment is only for explaining the present invention, and it is not limited to the present invention, and those skilled in the art can make modifications of the present embodiment without inventive contribution as needed after reading the present specification, but all of them are protected by patent law within the scope of the claims of the present invention.