阅读说明：本技术 一种横向双扩散晶体管及其漂移区的制造方法 (Transverse double-diffusion transistor and manufacturing method of drift region thereof ) 是由 韩广涛 陆阳 周逊伟 于 2016-12-07 设计创作，主要内容包括：本发明公开了一种横向双扩散晶体管漂移区的制造方法,本发明中,利用了胶层和掩膜层的设计,利用涂覆在最后介质层上的胶层作为阻挡,先对第二介质层,或第二和第三介质层,进行各向异性刻蚀,打开漂移区的中间区域,进行第一次漂移区注入,再利用胶层或第三介质层作为阻挡,对第二介质层进行各向同性刻蚀,去除胶层或胶层和第三介质层,利用第二介质层作为阻挡,进行第二次漂移区注入。在两次漂移区注入之间,仅需要进行一次光刻,形成了线性梯度漂移区。本发明减少了工艺流程和制作成本,并能够满足较高关断击穿电压和较低导通阻抗。(The invention discloses a manufacturing method of a transverse double-diffusion transistor drift region, which utilizes the design of an adhesive layer and a mask layer, utilizes the adhesive layer coated on the last dielectric layer as a barrier, performs anisotropic etching on a second dielectric layer or a second dielectric layer and a third dielectric layer, opens the middle region of the drift region, performs first drift region injection, utilizes the adhesive layer or the third dielectric layer as the barrier, performs isotropic etching on the second dielectric layer, removes the adhesive layer or the adhesive layer and the third dielectric layer, and utilizes the second dielectric layer as the barrier to perform second drift region injection. Between two drift region implantations, only one lithography is required to form the linear gradient drift region. The invention reduces the process flow and the manufacturing cost, and can meet the requirements of higher turn-off breakdown voltage and lower on-resistance.)

1. A method for manufacturing a drift region of a lateral double-diffused transistor comprises the following steps:

sequentially depositing at least a first dielectric layer and a second dielectric layer on the surface of the substrate to form a mask layer;

exposing and opening the middle position of the drift region by coating the adhesive layer, performing anisotropic etching on the second dielectric layer by using the adhesive layer as a barrier, and injecting the drift region for the first time to form a first doped region;

performing isotropic etching on the second dielectric layer by using the glue layer coated on the last dielectric layer as a barrier;

removing the glue layer, blocking by using the second dielectric layer, and then injecting the second drift region to form a second doped region;

the first doping area and the second doping area are opposite in type, and the first doping area and the substrate layer are the same in doping type.

2. The method of claim 1, wherein: a well with the same type as the second doping type is arranged at the leading-out position of the drain end of the transverse double-diffusion transistor, and the first doping area is cut into a left part and a right part so as to lead out the second doping area; the first doped region and the substrate have a common depletion effect on the second doped region, so that the concentration of the second doped region is higher, and high turn-off breakdown voltage and low on-resistance are obtained.

3. A method for manufacturing a drift region of a lateral double-diffused transistor is characterized in that:

sequentially depositing at least a first dielectric layer, a second dielectric layer and a third dielectric layer on the surface of the substrate to form a mask layer;

exposing and opening the middle position of the drift region by coating the adhesive layer, performing anisotropic etching on the second dielectric layer and the third dielectric layer by using the adhesive layer as a barrier, and injecting the drift region for the first time to form a first doped region;

removing the adhesive layer and carrying out primary annealing; utilizing the barrier of the third dielectric layer to perform isotropic etching on the second dielectric layer;

removing the third dielectric layer, blocking by using the second dielectric layer, and then injecting the second drift region to form a second doped region;

the first doping area and the second doping area are opposite in type, and the first doping area and the substrate are the same in doping type.

4. The method of claim 3, wherein: a well with the same type as the second doping type is arranged at the leading-out position of the drain end of the transverse double-diffusion transistor, and the first doping area is cut into a left part and a right part so as to lead out the second doping area; the first doped region and the substrate have a common depletion effect on the second doped region, so that the concentration of the second doped region is higher, and high turn-off breakdown voltage and low on-resistance are obtained.

5. A lateral double diffused transistor, characterized by: the drift region is manufactured by the manufacturing method of any one of the preceding claims 1 to 4.

Technical Field

The invention relates to the technical field of electronic devices, in particular to a lateral double-diffusion transistor and a manufacturing method of a drift region of the lateral double-diffusion transistor.

Background

A lateral double diffused transistor (LDMOS) is a short channel laterally conducting MOSFET that is fabricated by two diffusions. With the widespread use of lateral double-diffused transistors (LDMOS) in integrated circuits, the performance requirements for LDMOS are also increasing. In order to obtain a higher off-breakdown voltage (off-BV) and a lower on-resistance (Rdson), the drift region (drift) is often doped linearly and graded.

As shown in fig. 1, the NLDMOS of the prior art has a linear gradient drift region implemented by two photolithography and implantation processes, such as Ndrift1 and Ndrift 2. The above prior art process steps are shown in fig. 2, 3 and 4, where an oxide layer is deposited on the silicon surface and then formed by two photo-lithographies and two implantations of Ndrift1 and Ndrift2, respectively.

In the prior art, since the linear doping of the drift region is generally achieved by two or even multiple times of photolithography and implantation, the process flow is increased, and the process cost is greatly increased.

Disclosure of Invention

In order to provide a lateral double-diffused transistor and a manufacturing method of a drift region thereof, which meet the requirements of higher turn-off breakdown voltage and lower turn-on resistance and have less process flow, and solve the problem of high process cost in the prior art so as to reduce the process cost, the invention provides a manufacturing method of a drift region of a lateral double-diffused transistor.

The technical solution of the present invention is to provide a method for manufacturing a lateral double-diffused transistor drift region, which comprises the following steps:

sequentially depositing at least a first dielectric layer and a second dielectric layer on the surface of the substrate to form a mask layer;

exposing and opening the middle position of the drift region by coating the adhesive layer, performing anisotropic etching on the second dielectric layer by using the adhesive layer as a barrier, and injecting the drift region for the first time to form a first doped region;

performing isotropic etching on the second dielectric layer by using the glue layer coated on the last dielectric layer as a barrier;

removing the glue layer, blocking by using the second dielectric layer, and then injecting the second drift region to form a second doped region;

wherein the first doped region and the second doped region are of the same type and jointly form a linearly graded doped drift region.

Optionally, the first dielectric layer is an oxide layer, and the second dielectric layer is a silicon nitride layer.

Optionally, the thickness of the first dielectric layer is 50-1000 angstroms, and the thickness of the second dielectric layer is 50-3000 angstroms.

Another technical solution of the present invention is to provide a method for manufacturing a lateral double diffused transistor, including the steps of:

sequentially depositing at least a first dielectric layer, a second dielectric layer and a third dielectric layer on the surface of the substrate to form a mask layer;

exposing and opening the middle position of the drift region by coating the adhesive layer, performing anisotropic etching on the second dielectric layer and the third dielectric layer by using the adhesive layer as a barrier, and injecting the drift region for the first time to form a first doped region;

removing the adhesive layer and carrying out primary annealing; utilizing the barrier of the third dielectric layer to perform isotropic etching on the second dielectric layer;

removing the third dielectric layer, blocking by using the second dielectric layer, and then injecting the second drift region to form a second doped region;

wherein the first doped region and the second doped region are of the same type and jointly form a linearly graded doped drift region.

Optionally, the first dielectric layer is an oxide layer, the second dielectric layer is a silicon nitride layer, and the third dielectric layer is also an oxide layer.

Optionally, the thickness of the first dielectric layer is 50-1000 angstroms, the thickness of the second dielectric layer is 50-3000 angstroms, and the thickness of the third dielectric layer is 50-3000 angstroms.

In another aspect of the present invention, a method for manufacturing a lateral double diffused transistor includes the following steps:

sequentially depositing at least a first dielectric layer and a second dielectric layer on the surface of the substrate to form a mask layer;

exposing and opening the middle position of the drift region by coating the adhesive layer, performing anisotropic etching on the second dielectric layer by using the adhesive layer as a barrier, and injecting the drift region for the first time to form a first doped region;

performing isotropic etching on the second dielectric layer by using the glue layer coated on the last dielectric layer as a barrier;

removing the glue layer, blocking by using the second dielectric layer, and then injecting the second drift region to form a second doped region;

the first doping area and the second doping area are opposite in type, and the first doping area and the substrate layer are the same in doping type.

Optionally, a well with the same type as the second doping type is arranged at the drain end leading-out position of the lateral double-diffusion transistor, and the first doping region is cut into a left part and a right part, so that the leading-out of the second doping region is realized; the first doped region and the substrate have a common depletion effect on the second doped region, so that the concentration of the second doped region is higher, and high turn-off breakdown voltage and low on-resistance are obtained.

In another aspect of the present invention, a method for manufacturing a lateral double diffused transistor includes the following steps:

sequentially depositing at least a first dielectric layer, a second dielectric layer and a third dielectric layer on the surface of the substrate to form a mask layer;

exposing and opening the middle position of the drift region by coating the adhesive layer, performing anisotropic etching on the second dielectric layer and the third dielectric layer by using the adhesive layer as a barrier, and injecting the drift region for the first time to form a first doped region;

removing the adhesive layer and carrying out primary annealing; utilizing the barrier of the third dielectric layer to perform isotropic etching on the second dielectric layer;

removing the third dielectric layer, blocking by using the second dielectric layer, and then injecting the second drift region to form a second doped region;

the first doping area and the second doping area are opposite in type, and the first doping area and the substrate are the same in doping type.

Optionally, a well with the same type as the second doping type is arranged at the drain end leading-out position of the lateral double-diffusion transistor, and the first doping region is cut into a left part and a right part, so that the leading-out of the second doping region is realized; the first doped region and the substrate have a common depletion effect on the second doped region, so that the concentration of the second doped region is higher, and high turn-off breakdown voltage and low on-resistance are obtained.

In another aspect of the present invention, a lateral double diffused transistor is provided, in which the drift region is manufactured by any one of the above manufacturing methods.

Compared with the prior art, the method of the invention has the following advantages: according to the invention, by utilizing the design of the glue layer and the mask layer, the glue layer coated on the last dielectric layer is used as a barrier, anisotropic etching is firstly carried out on the second dielectric layer or the second and third dielectric layers, the middle area of the drift region is opened, the first drift region injection is carried out, then the glue layer or the third dielectric layer is used as a barrier, isotropic etching is carried out on the second dielectric layer, the glue layer or the glue layer and the third dielectric layer are removed, and the second drift region injection is carried out by using the second dielectric layer as a barrier. Between two drift region implantations, only one lithography is required to form the linear gradient drift region. The invention reduces the process flow and the manufacturing cost, and can meet the requirements of higher turn-off breakdown voltage and lower on-resistance.

Drawings

FIG. 1 is a schematic diagram of a prior art N-type laterally double diffused transistor;

FIG. 2 is a schematic diagram of a prior art method of depositing an oxide layer on a substrate;

FIG. 3 is a schematic illustration of a first lithography and implant in the prior art;

FIG. 4 is a schematic illustration of a second photolithography and implant in the prior art;

FIG. 5 is a schematic structural diagram of a first embodiment of an N-type LDMOS transistor of the present invention;

FIG. 6 is a schematic view of a mask layer formed over a substrate according to one embodiment of the present invention;

FIG. 7 is a schematic view of a first implant in accordance with one embodiment of the present invention;

FIG. 8 is a schematic diagram of an isotropic etch in accordance with an embodiment of the present invention;

fig. 9 is a schematic diagram of a second implantation in accordance with an embodiment of the present invention.

FIG. 10 is a schematic structural diagram of a second N-type LDMOS transistor according to an embodiment of the present invention;

FIG. 11 is a schematic view of a second first implant in accordance with the present invention;

FIG. 12 is a schematic view of a second isotropic etch in accordance with an embodiment of the present invention;

fig. 13 is a schematic diagram of a second implantation in accordance with the present invention.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to only these embodiments. The invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention.

In the following description of the preferred embodiments of the present invention, specific details are set forth in order to provide a thorough understanding of the present invention, and it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are in simplified form and are not to precise scale, which is only used for convenience and clarity to assist in describing the embodiments of the present invention.

Referring to fig. 5, a structure of a first embodiment of an N-type ldmos transistor according to the present invention is illustrated. The invention can form the linear gradient drift region as shown in the figure by one-time photoetching and two-time injection, mainly utilizes the design of a mask layer and a step sequence, and is implemented by two embodiments according to whether an annealing process is needed or not.

In the occasion that the annealing process is not needed, the glue layer is used as the barrier layer, the layer number of the mask layer can be reduced, and the method is realized by adopting the following steps:

sequentially depositing at least a first dielectric layer and a second dielectric layer on the surface of a substrate P-sub (the substrate is of a P type) to form a mask layer; for convenience of description, only two layers are taken as an example for description, the first dielectric layer is an oxide layer, and the second dielectric layer is a silicon nitride layer. Meanwhile, due to the design of at least two layers, from the scheme realization, other dielectric layers can be arranged between the first dielectric layer and the second dielectric layer, or other dielectric layers can be arranged below the first dielectric layer or above the second dielectric layer.

Exposing and opening the middle position of the N-type drift region by coating the adhesive layer, performing anisotropic etching on the second dielectric layer by using the adhesive layer as a barrier, and injecting the drift region for the first time to form a first doped region; it is preferable in this embodiment that the first doped region is deeper than the second doped region in terms of the characteristics of the device.

Performing isotropic etching on the second dielectric layer by using the glue layer coated on the last dielectric layer as a barrier; and under the condition that the second dielectric layer is positioned on the last layer, the last dielectric layer is the second dielectric layer.

Removing the glue layer, blocking by using the second dielectric layer, and then injecting the second drift region to form a second doped region; the second doped region is shallower than the first doped region and is located around the first doped region.

The first doped region and the second doped region are of the same type, and if the first doped region and the second doped region are N-type LDMOS, the first doped region and the second doped region jointly form a linear gradient doped N-type drift region. Similarly, the P-type LDMOS and the P-type LDMOS form a P-type drift region doped in a linear gradient manner.

The thickness of the first dielectric layer is 50-1000 angstroms, and the thickness of the second dielectric layer is 50-3000 angstroms. The full name of the angstrom unit is angstrom-strean, 1 angstrom (A), etc. is 0.1 nanometer.

In the occasion of needing the annealing process, the glue layer needs to be removed before annealing, so the mask layer with at least three dielectric layers is adopted, the specific implementation principle is consistent with the method, but the specific implementation process is slightly different. The present invention will be described in detail in the following drawings for the fabrication of an LDMOS in this case, also taking the N-type as an example.

Referring to fig. 6, a state of laying down a mask layer on a substrate is illustrated according to an embodiment of the present invention. The mask layer comprises a three-layer structure including a first dielectric layer, a second dielectric layer and a third dielectric layer. As shown in the figure, the first dielectric layer is an oxide layer oxide positioned on the surface of the substrate P-sub, the second dielectric layer Nitride is a silicon Nitride layer positioned on the first dielectric layer oxide, and the third dielectric layer is also an oxide layer oxide positioned on the second dielectric layer Nitride. The thickness of the first dielectric layer is 50-1000 angstroms, the thickness of the second dielectric layer is 50-3000 angstroms, and the thickness of the third dielectric layer is 50-3000 angstroms.

In addition to the masking layer structure of fig. 6, the layers may be replaced, and other dielectric layers may be disposed between the layers.

Referring to FIG. 7, a first injection condition of an embodiment of the present invention is illustrated. And arranging an exposure glue layer Photoresist on the third dielectric layer oxide, opening the middle position of the N-type drift region, performing anisotropic etching on the second dielectric layer and the third dielectric layer by using the glue layer as a barrier, and injecting Ndrift into the drift region for the first time to form a first doped region.

Referring to FIG. 8, a state of isotropic etching according to an embodiment of the present invention is illustrated. After the first implant is completed as shown in fig. 7, the glue layer is then removed and a first anneal is performed. And performing isotropic etching on the silicon nitride layer serving as the second dielectric layer by using the oxide layer serving as the third dielectric layer for blocking. To form a region for a second implant to facilitate a next second drift region Ndrift implant.

Referring to fig. 9, a second implantation state according to an embodiment of the present invention is illustrated. After the isotropic etching of the second dielectric layer as shown in fig. 8 is completed, the third dielectric layer is removed, the second dielectric layer is used for blocking, and the second doping region is formed by injecting the second drift region Ndrift. The first doped region and the second doped region are of the same type, and the first doped region and the second doped region jointly form a linear gradient doped N-type drift region. Similarly, the P-type LDMOS and the P-type LDMOS form a P-type drift region doped in a linear gradient manner.

Referring to fig. 10, a structure of a second embodiment of an N-type ldmos transistor of the present invention is illustrated. The invention can form the drift region as shown in the figure by one-time photoetching and two-time injection, mainly utilizes the design of a mask layer and a step sequence, and is implemented by two embodiments according to whether an annealing process is needed or not.

In the occasion that the annealing process is not needed, the glue layer is used as the barrier layer, the layer number of the mask layer can be reduced, and the method is realized by adopting the following steps:

sequentially depositing at least a first dielectric layer and a second dielectric layer on the surface of a substrate P-sub (the substrate is of a P type) to form a mask layer; for convenience of description, only two layers are taken as an example for description, the first dielectric layer is an oxide layer, and the second dielectric layer is a silicon nitride layer. Meanwhile, due to the design of at least two layers, from the scheme realization, other dielectric layers can be arranged between the first dielectric layer and the second dielectric layer, or other dielectric layers can be arranged below the first dielectric layer or above the second dielectric layer.

Exposing and opening the middle position of the N-type drift region by coating the adhesive layer, performing anisotropic etching on the second dielectric layer by using the adhesive layer as a barrier, and injecting P-top of the drift region for the first time to form a first doped region; in this embodiment, different from the first embodiment, the depth of the first doped region is shallower than that of the second doped region.

Performing isotropic etching on the second dielectric layer by using the glue layer coated on the last dielectric layer as a barrier;

removing the glue layer, blocking by using the second dielectric layer, and then injecting the N-drift region for the second time to form a second doped region; in this embodiment, different from the first embodiment, the second doped region is deeper than the first doped region and separates the first doped region from the substrate, and the range of the second doped region is larger than that of the first doped region.

The first doping area and the second doping area are opposite in type, and the first doping area and the substrate layer are the same in doping type. The substrate in the figure is P-type, the first doped region is P-type, and the second doped region is N-type. An N well nwell with the same doping type as the second doping type is arranged at the leading-out position of the drain end of the transverse double-diffusion transistor, and the first doping region is cut into a left part and a right part so as to realize the leading-out of the second doping region; the first doped region and the substrate have a common depletion effect on the second doped region, so that the concentration of the second doped region is higher, and high turn-off breakdown voltage and low on-resistance are obtained. Similarly, in the case of a P-type LDMOS, the substrate is N-type, so the first doped region is N-type and the second doped region is P-type.

In the occasion of needing the annealing process, the glue layer needs to be removed before annealing, so the mask layer with at least three dielectric layers is adopted, the specific implementation principle is consistent with the method, but the specific implementation process is slightly different. The present invention will be described in detail in the following drawings for the fabrication of an LDMOS in this case, also taking the N-type as an example.

Referring to fig. 11, a state at the time of the second first injection of the embodiment of the present invention is illustrated. Since the state of the mask layer formed over the substrate is the same as that in fig. 6, the contents of this portion can be referred to fig. 6, and no additional drawings are provided. After the mask layer with the three-layer structure is laid, the middle position of the N-type drift region is opened through coating the glue layer and exposing, the glue layer is used as a barrier, anisotropic etching is conducted on the second dielectric layer and the third dielectric layer, the P-top of the drift region for the first time is injected, and a first doped region is formed, is of a P type and is the same as the type of the substrate.

Referring to FIG. 12, the state of isotropic etching according to the second embodiment of the present invention is illustrated. After the first implant is completed as shown in fig. 11, the glue layer is then removed and a first anneal is performed. And performing isotropic etching on the silicon nitride layer serving as the second dielectric layer by using the oxide layer serving as the third dielectric layer for blocking. To form a region for a second implant to facilitate a next second drift region Ndrift implant.

Referring to fig. 13, a second implantation state according to an embodiment of the present invention is illustrated. After the isotropic etching of the second dielectric layer as shown in fig. 12 is completed, the third dielectric layer is removed, the second dielectric layer is used for blocking, and the second drift region Ndrift implantation is performed to form a second doped region, wherein the second doped region is N-type. Namely, the types of the first doped region and the second doped region are opposite, and the first doped region is the same as the substrate doping type.

The substrate in the figure is P-type, the first doped region is P-type, and the second doped region is N-type. An N well nwell with the same doping type as the second doping type is arranged at the leading-out position of the drain end of the transverse double-diffusion transistor, and the first doping region is cut into a left part and a right part so as to realize the leading-out of the second doping region; the first doped region and the substrate have a common depletion effect on the second doped region, so that the concentration of the second doped region is higher, and high turn-off breakdown voltage and low on-resistance are obtained. Similarly, in the case of a P-type LDMOS, the substrate is N-type, so the first doped region is N-type, the second doped region is P-type, and a P-well pwell having the same type as the second doped region is provided at the drain leading-out of the lateral double-diffused transistor.

In the invention, the drift region has field oxide (locos), small field oxide (mini-locos) or Shallow Trench Isolation (STI).

In addition, although the embodiments are described and illustrated separately, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and reference may be made to one of the embodiments without explicit mention.

The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.