阅读说明：本技术 一种针对射频芯片热集中点的三维堆叠散热模组制作方法 (manufacturing method of three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration points ) 是由 郁发新 冯光建 张兵 王志宇 周琪 于 2019-09-24 设计创作，主要内容包括：本发明公开了一种针对射频芯片热集中点的三维堆叠散热模组制作方法,具体包括如下步骤：101)上散热底座制作步骤、102)散热底座制作步骤、103)芯片集成步骤；本发明通过在芯片底部设置散热微流通道做散热器,同时在芯片发热点位置或附近区域分布设置加装二次散热微流通道,使该区域热量能够更快的被散热流体带走,避免了热点因为热量较大而导致芯片失效的问题的一种针对射频芯片热集中点的三维堆叠散热模组制作方法。(The invention discloses a three-dimensional stacking heat dissipation module manufacturing method aiming at a radio frequency chip heat concentration point, which specifically comprises the following steps of 101) manufacturing an upper heat dissipation base, 102) manufacturing a heat dissipation base, and 103) integrating a chip, wherein a heat dissipation micro-flow channel is arranged at the bottom of the chip to serve as a heat radiator, and a secondary heat dissipation micro-flow channel is distributed and arranged at the position of a chip heating point or a nearby area, so that the heat in the area can be quickly taken away by heat dissipation fluid, and the problem that the chip fails due to the fact that a hot spot is large in heat is solved.)

1, method for manufacturing three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration points, which is characterized by comprising the following steps:

101) an upper heat dissipation base manufacturing step: the upper heat dissipation base comprises an upper layer and a lower layer, wherein silicon oxide or silicon nitride is deposited on the surfaces of the upper layer and the lower layer or an insulating layer is formed by direct thermal oxidation, and a seed layer is manufactured above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; manufacturing RDL on the seed layer;

manufacturing microfluidic grooves on the upper surfaces of the upper layer and the lower layer through photoetching and etching processes; the micro-flow grooves directly pass through the heating point area of the radio frequency chip, or are uniformly distributed in the area outside the heating point area of the radio frequency chip;

forming an upper heat dissipation base with micro-circulation inside on the upper surfaces of the upper layer and the lower layer through a eutectic bonding process;

102) the manufacturing step of the heat dissipation base comprises the following steps: repeating the step 101) to manufacture a lower heat dissipation base, and bonding the upper heat dissipation base and the lower heat dissipation base through a eutectic bonding process; wherein, the micro-flow grooves of the upper heat dissipation base and the lower heat dissipation base are stacked in a cross distribution manner;

103) chip integration step: and attaching the radio frequency chip to the corresponding position on the surface of the heat dissipation base to form the three-dimensional stacked heat dissipation module.

2. The method for manufacturing a three-dimensional stacked heat dissipation module aiming at a heat concentration point of a radio frequency chip, according to claim 1, wherein the RDL manufacturing process comprises RDL wiring and a PAD, an insulating layer is manufactured by depositing silicon oxide or silicon nitride, a chip PAD is exposed by photoetching and dry etching, RDL wiring arrangement is performed by photoetching and electroplating processes, wherein the RDL wiring adopts or a mixture of more of copper, aluminum, nickel, silver, gold and tin, the RDL wiring adopts a layer or multilayer structure, the thickness range is 10nm to 1000um, bonding metal is manufactured by photoetching and electroplating processes to form the PAD, and the opening diameter of the PAD is 10um to 10000 um.

3. The method of claim 2, wherein the RDL is covered with an insulating layer and the pads are exposed by a windowing process.

4. The method for manufacturing three-dimensional stacked heat dissipation modules aiming at radio frequency chip heat concentration points according to claim 2, wherein the thickness of the insulation layer ranges from 10nm to 100um, the seed layer has a structure of layers or multi-layer structures, the thickness ranges from 1nm to 100um, the material is or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and the thickness of the insulation layer ranges from 10nm to 1000 um.

5. The method for manufacturing three-dimensional stacked heat dissipation modules for heat concentration points of RF chips as claimed in claim 1, wherein the upper and lower layers are wafers of 4, 6, 8, 12 inches, the thickness is 200um to 2000um, and the material is glass, quartz, silicon carbide, alumina, epoxy resin or polyurethane.

6. The method of claim 1, wherein the micro-flow grooves have a depth of 10um to 700um and a length of 100um to 10 mm.

7. The method of claim 1, wherein the micro-grooves of the lower heat spreader base are vertically disposed.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of three-dimensional stacked heat dissipation modules for radio frequency chip heat concentration points.

Background

The rapid development of electronic products is the main driving force of the evolution of packaging technology, and miniaturization, high density, high frequency, high speed, high performance, high reliability and low cost are the mainstream development directions of advanced packaging, wherein system-in-package is the most important and most potential of the technology for satisfying the high-density system integration.

In various system-in-package (SIP) packages, a silicon interposer is used as a substrate technology of the SIP package, which provides the shortest connection distance, the smallest pad size and the smallest center-to-center distance for the chip-to-chip and the chip-to-PCB. Advantages of silicon interposer technology over other interconnect technologies, such as wire bonding, include: better electrical performance, higher bandwidth, higher density, smaller size, lighter weight.

However, a silicon interposer embedding process needs to use a relatively harsh heat dissipation structure, for some radio frequency chips, the heating positions may be only some points with a small area, and even if the whole radiator works fully under the chip, the heat dissipation capability of the radiator is still very little to the heating points with the small area, which may cause the chip to fail.

Disclosure of Invention

The invention overcomes the defects of the prior art and provides methods for manufacturing the three-dimensional stacking heat dissipation module aiming at the heat concentration point of the radio frequency chip.

The technical scheme of the invention is as follows:

method for manufacturing three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration points, comprising the following steps:

101) an upper heat dissipation base manufacturing step: the upper heat dissipation base comprises an upper layer and a lower layer, wherein silicon oxide or silicon nitride is deposited on the surfaces of the upper layer and the lower layer or an insulating layer is formed by direct thermal oxidation, and a seed layer is manufactured above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; manufacturing RDL on the seed layer;

manufacturing microfluidic grooves on the upper surfaces of the upper layer and the lower layer through photoetching and etching processes; the micro-flow grooves directly pass through the heating point area of the radio frequency chip, or are uniformly distributed in the area outside the heating point area of the radio frequency chip;

forming an upper heat dissipation base with micro-circulation inside on the upper surfaces of the upper layer and the lower layer through a eutectic bonding process;

102) the manufacturing step of the heat dissipation base comprises the following steps: repeating the step 101) to manufacture a lower heat dissipation base, and bonding the upper heat dissipation base and the lower heat dissipation base through a eutectic bonding process; wherein, the micro-flow grooves of the upper heat dissipation base and the lower heat dissipation base are stacked in a cross distribution manner;

103) chip integration step: and attaching the radio frequency chip to the corresponding position on the surface of the heat dissipation base to form the three-dimensional stacked heat dissipation module.

, the RDL manufacturing process comprises RDL routing and a PAD, an insulating layer is manufactured by depositing silicon oxide or silicon nitride, a chip PAD is exposed by photoetching and dry etching, RDL routing arrangement is performed by photoetching and electroplating processes, wherein the RDL routing adopts or a mixture of copper, aluminum, nickel, silver, gold and tin, the RDL routing adopts a layer or multilayer structure, the thickness range is 10nm to 1000um, bonding metal is manufactured by photoetching and electroplating processes to form the PAD, and the window diameter of the PAD is 10um to 10000 um.

, covering an insulating layer on the surface of the RDL and exposing the pad through a windowing process.

, the thickness of the insulating layer is 10nm to 100um, the seed layer is layer or multi-layer structure, the thickness is 1nm to 100um, the material is or a mixture of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, the thickness of the insulating layer is 10nm to 1000 um.

And , adopting wafers of 4, 6, 8 and 12 inches wafers as the upper layer and the lower layer, wherein the thickness ranges from 200um to 2000um, and the materials are glass, quartz, silicon carbide, alumina, epoxy resin or polyurethane.

Step , the microfluidic channel has a depth in the range of 10um to 700um and a length in the range of 100um to 10 mm.

, the micro-flow grooves of the lower heat sink base are vertically distributed.

Compared with the prior art, the invention has the advantages that: according to the invention, the heat dissipation micro-flow channel is arranged at the bottom of the chip to serve as a radiator, and the secondary heat dissipation micro-flow channels are distributed and arranged at the position of the heating point of the chip or in the area near the heating point of the chip, so that the heat in the area can be quickly taken away by the heat dissipation fluid, and the problem that the chip fails due to the fact that the hot point has large heat is avoided.

Drawings

FIG. 1 is a schematic diagram of an RF chip according to the present invention;

FIG. 2 is a schematic view of an upper heat sink base according to the present invention;

FIG. 3 is a schematic view of a lower heat sink base according to the present invention;

FIG. 4 is a schematic cross-sectional view of samples of the present invention;

fig. 5 is an overall cross-sectional view of the lower heat sink base of the present invention employing vertical micro-flow grooves.

The labels in the figure are: the chip comprises a radio frequency chip 101, a heating point area 102, an upper heat dissipation base 103, a micro-flow groove 104, a lower heat dissipation base 105 and a micro-flow groove 106 which is vertically distributed.

Detailed Description

Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.

It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein by .

Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.

The invention is further described in conjunction with the figures and the detailed description.