阅读说明：本技术 一种具有防溢锡结构的新三维异构堆叠方法 (novel three-dimensional heterogeneous stacking method with anti-overflow tin structure ) 是由 郁发新 冯光建 王志宇 陈华 张兵 于 2019-09-27 设计创作，主要内容包括：本发明公开了一种具有防溢锡结构的新三维异构堆叠方法,具体包括如下步骤：101)金属柱制作步骤、102)再次处理步骤、103)镀锡步骤、104)防溢步骤；本发明提供凸点或焊圈和焊盘金属就会有一定的距离为焊锡保留提供足够空间的一种具有防溢锡结构的新三维异构堆叠方法。(The invention discloses novel three-dimensional heterogeneous stacking methods with anti-overflow tin structures, which specifically comprise the following steps of 101) metal column manufacturing step, 102) retreating step, 103) tin plating step and 104) anti-overflow step, and the invention provides novel three-dimensional heterogeneous stacking methods with anti-overflow tin structures, wherein distances are provided between bumps or welding rings and pad metals to provide enough space for solder reservation.)

1, novel three-dimensional heterogeneous stacking method with anti-overflow tin structure, which is characterized by comprising the following steps:

101) coating th layer of photoresist on the seed layer, removing part of the seed layer through a developing process to expose an area to be electroplated, and electroplating metal to form a metal column, wherein the upper surface of the metal column is a plane;

102) and a second treatment step: coating a second layer of photoresist on the upper surface of the carrier plate processed in the step 101), exposing and developing to expose the part of the metal column, and removing the exposed area at the top of the part of the metal column by wet etching to form a groove; wherein, the depth range of the etched groove is 1nm to 100um, and the etching width range is 1um to 1000 um;

103) tin plating, namely soldering tin on the electroplated metal area, removing the second layer of photoresist, the th layer of photoresist and the seed layer, coating soldering flux, cleaning the soldering flux after refluxing to obtain a structure of the carrier plate with the soldering tin layer on the upper surface;

104) an anti-overflow step: and arranging the chip on the soldering tin in the step 103) to form a new chip module, carrying out surface welding on the new chip module and the new chip module, and welding the new chip module and the new chip module to be tightly combined to form the three-dimensional stacking of the anti-overflow tin structure.

2. The new three-dimensional heterogeneous stacking method with anti-overflow Sn structure as claimed in claim 1, wherein the seed layer has or multi-layer structure with thickness ranging from 1nm to 100 μm, and the material is or more of Ti, Cu, Al, Ag, Pd, Au, Tl, Sn and Ni.

3. The new three-dimensional heterogeneous stacking method with anti-overflow tin structure as claimed in claim 1, wherein the thickness of the metal pillar ranges from 1nm to 100um, the structure of the metal pillar itself is layers or multi-layer structure, the material is or more mixed in titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, gallium metal alloy.

Technical Field

The invention relates to the technical field of semiconductors, in particular to an novel three-dimensional heterogeneous stacking method with a tin overflow prevention structure.

Background

The microwave millimeter wave radio frequency integrated circuit technology is the basis of modern national defense weaponry and internet industry, and along with the rapid rise of the economy of internet plus such as intelligent communication, intelligent home, intelligent logistics, intelligent transportation and the like, the microwave millimeter wave radio frequency integrated circuit which bears the functions of data access and transmission also has huge practical requirements and potential markets.

However, for the rf chip, such as the analog chip, the area of the analog chip cannot be reduced by the same factor as that of the digital chip , so that the rf microsystem with very high frequency does not have enough area to place the PA/LNA and needs to stack the PA/LNA.

In practical applications, the module stacking process is a process of performing metal fusion bonding on the metal dams on the upper and lower surfaces of the module, for wafer-level bonding process and large-sized chip bonding process, extremely harsh bonding conditions are required to avoid the tin overflow surface on the surfaces of the metal dams or the interconnection pads in the bonding process, for the dams with large areas , the problem that tin overflow does not occur on all chips is basically not realized, and when tin overflow occurs in , the amount of tin on the surface of the dam is greatly reduced, which is very disadvantageous for the subsequent metal fusion process.

Disclosure of Invention

The invention overcomes the defects of the prior art and provides novel three-dimensional heterogeneous stacking methods with a tin overflow prevention structure.

The technical scheme of the invention is as follows:

A new three-dimensional heterogeneous stacking method with a tin overflow prevention structure specifically comprises the following steps:

101) coating th layer of photoresist on the seed layer, removing part of the seed layer through a developing process to expose an area to be electroplated, and electroplating metal to form a metal column, wherein the upper surface of the metal column is a plane;

102) and a second treatment step: coating a second layer of photoresist on the upper surface of the carrier plate processed in the step 101), exposing and developing to expose the part of the metal column, and removing the exposed area at the top of the part of the metal column by wet etching to form a groove; wherein, the depth range of the etched groove is 1nm to 100um, and the etching width range is 1um to 1000 um;

103) tin plating, namely soldering tin on the electroplated metal area, removing the second layer of photoresist, the th layer of photoresist and the seed layer, coating soldering flux, cleaning the soldering flux after refluxing to obtain a structure of the carrier plate with the soldering tin layer on the upper surface;

104) an anti-overflow step: and arranging the chip on the soldering tin in the step 103) to form a new chip module, carrying out surface welding on the new chip module and the new chip module, and welding the new chip module and the new chip module to be tightly combined to form the three-dimensional stacking of the anti-overflow tin structure.

And , the seed layer has layers or multi-layer structure, thickness of 1nm to 100um, and material selected from or mixture of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.

, the thickness of the metal column ranges from 1nm to 100um, the structure of the metal column is layers or multi-layer structure, the material is or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and gallium metal alloy.

Compared with the prior art, the invention has the advantages that the protective patterns with different heights are manufactured around the cofferdam or the welding pad, so that the protective patterns can be preferentially contacted to form a surrounding block in the bonding engineering of the wafer or the chip, and thus, the distance between the salient point or the welding ring and the pad metal is to provide enough space for the solder reservation, thereby ensuring that the subsequent metal melting provides three-dimensional stacking of the anti-overflow tin structure.

Drawings

Fig. 1 is a schematic view of a carrier according to the present invention;

FIG. 2 is a schematic view of the seed layer and the electroplating area of FIG. 1;

FIG. 3 is a schematic illustration of the plating area of FIG. 2 according to the present invention;

FIG. 4 is a schematic view of FIG. 3 with a second layer of photoresist provided in accordance with the present invention;

FIG. 5 is a schematic view of FIG. 4 with grooves according to the present invention;

FIG. 6 is a schematic view of FIG. 5 illustrating the removal of the second layer of photoresist;

FIG. 7 is a schematic view of the invention shown in FIG. 6 with the solder removed from the th layer of photoresist;

FIG. 8 is a schematic view of the present invention;

FIG. 9 is a schematic view of a second carrier board of the present invention having metal posts and top solder;

FIG. 10 is a schematic view of FIG. 9 after photoresist removal in accordance with the present invention;

FIG. 11 is a schematic view of the invention shown in FIG. 10 with solder removed;

FIG. 12 is a schematic view of FIG. 11 with portions of the metal pillar removed in accordance with the present invention;

FIG. 13 is a second schematic of the present invention.

The carrier board 101, th layer of photoresist 102, the region to be electroplated 103, the metal pillar 104, the second layer of photoresist 105, and the top solder 106 are marked.

Detailed Description

Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.

It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein by .

Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.

The invention is further described in conjunction with the figures and the detailed description.