Power amplifier
阅读说明：本技术 功率放大器 (Power amplifier ) 是由 文剑 杨梅 宋征华 熊险峰 C·梅罗尼 于 2014-06-30 设计创作，主要内容包括：本发明的各种实施例提供了一种功率放大器,包括：钳位电路(N1),被配置为从电源提供钳位电压；放大器对(N2),具有耦合到钳位电路的多个第一输入端、多个第二输入端和用于提供放大的信号的输出端；以及偏置电路(N3),耦合在钳位电路和放大器对的多个第二输入端之间并且被配置为调节放大器对的输入偏置电压以便使得放大器对的输出偏置电压随着电源电压的变化而成比例地改变。(Various embodiments of the present invention provide power amplifiers including a clamp circuit (N1) configured to provide a clamp voltage from a power supply, an amplifier pair (N2) having a plurality of inputs coupled to the clamp circuit, a plurality of second inputs, and an output for providing an amplified signal, and a bias circuit (N3) coupled between the clamp circuit and the plurality of second inputs of the amplifier pair and configured to adjust an input bias voltage of the amplifier pair such that an output bias voltage of the amplifier pair varies proportionally with variations in the supply voltage.)
An kind of power amplifier, comprising:
a clamp circuit configured to provide a clamp voltage from a power supply at a supply voltage suppression node;
a bias circuit comprising a buffer circuit having a input coupled to receive a th voltage derived from the clamped voltage and a second input coupled to receive a second voltage derived from the clamped power supply, the buffer circuit having an output to generate a bias voltage, and
an amplifier pair having a th plurality of inputs coupled to the clamping voltage at the clamping circuit, an output for providing an amplified signal, and a second plurality of inputs, and
wherein a bias voltage generated at an output of the buffer circuit is coupled to a second plurality of inputs of the amplifier pair to adjust the input bias voltage of the amplifier pair such that the output of the amplifier pair changes proportionally with changes in the voltage of the power supply.
2. The power amplifier of claim 1, wherein:
the clamp circuit includes two or more voltage dividing resistors for dividing a voltage of the power supply;
wherein a voltage divided by the voltage dividing resistor is coupled to a supply voltage suppression node which is further coupled to the th plurality of inputs of the amplifier pair through th plurality of bias resistors, respectively, and
the supply voltage suppression node is coupled to ground through a capacitor, providing the clamped voltage at the supply voltage suppression node.
3. The power amplifier of claim 2, wherein:
the bias circuit further includes a buffer and a second buffer, wherein each buffers have at least inputs and outputs,
inputs of the buffer are coupled to the supply voltage suppression node;
an output of the buffer is coupled to a input of the second buffer via a resistor;
the supply voltage suppression node is coupled to a second input of the second buffer;
a second resistor is coupled between the output of the second buffer and the th input
Outputs of the second buffer are coupled to the second plurality of inputs of the amplifier pair via a second plurality of bias resistors, respectively.
4. The power amplifier according to claim 3, wherein the th buffer is configured to amplify the clamp voltage when the power supply remains unchanged, and output the clamp voltage as it is when the power supply drops.
5. The power amplifier of claim 3, wherein the third buffer is coupled between the supply voltage suppression node and a second input of the second buffer.
6. The power amplifier of claim 1, further comprising:
a plurality of bias point entries configured to apply the bias voltage to th plurality of inputs of the amplifier pair, respectively, and
a capacitor coupled between the supply voltage suppression node and ground.
7. The power amplifier of claim 1 wherein the bias circuit further comprises an th buffer, the th buffer having an input coupled to the supply voltage suppression node and an output coupled to a th input of the buffer circuit.
8. The power amplifier of claim 7, wherein the buffer is configured to amplify the clamped voltage at a power supply level and is further configured to not amplify the clamped voltage at a second power supply level lower than the power supply level.
9. The power amplifier of claim 8, wherein the bias circuit further comprises a second buffer coupled between the supply voltage suppression node and a second input of the buffer circuit.
10. The power amplifier of claim 1, further comprising a plurality of bias resistors configured to apply the bias voltage to the second plurality of inputs, respectively, that are amplifier pairs.
11. The power amplifier of any of claims 1-10, wherein the amplifier pair is configured as a class ab amplifier.
12, , a circuit comprising:
an audio amplifier having an audio signal input and a bias signal input; and
a bias circuit having an output coupled to a bias signal input of the audio amplifier;
wherein the bias circuit comprises:
circuitry configured to generate an th voltage from a supply voltage at a supply voltage suppression node;
an th buffer circuit having an input coupled to the supply voltage suppression node, the th buffer circuit configured to operate with a variable gain to generate a second voltage from the th voltage, and
an amplifier circuit having a input coupled to receive the th voltage and a second input configured to receive the second voltage, wherein an output of the amplifier circuit generates a bias signal for application to the bias signal input.
13. The circuit of claim 12, wherein the variable gain comprises a switching gain comprising a unity gain setting and a non-unity gain setting.
14. The circuit of claim 13, wherein the buffer circuit operates at the unity gain setting when the supply voltage is at an voltage level, and the buffer circuit operates at the non-unity gain when the supply voltage is at a second voltage level.
15. The circuit of claim 14, wherein the th voltage level is less than the second voltage level.
16. The circuit of claim 12, further comprising a second buffer circuit coupled between the supply voltage suppression node and the th input of the amplifier circuit.
17. The circuit of any of claims 12-16, , further including a capacitor coupled between the supply voltage inhibit node and a reference supply node.
18, a method for adjusting a bias voltage of a power amplifier including a clamp circuit, an amplifier pair, and a bias circuit, comprising:
providing a clamping voltage from a supply voltage through the clamping circuit;
adjusting, by the bias circuit, an input bias voltage of the amplifier pair such that an output of the amplifier pair changes in proportion to a change in the power supply; and
providing an amplified output by the amplifier pair;
wherein adjusting the input bias voltage comprises:
comparing an th voltage derived from the clamping voltage to a second voltage derived from the bias voltage to generate a bias voltage;
applying the clamping voltage to a plurality of th inputs of the amplifier pair, and
applying the bias voltage to a plurality of second inputs of the amplifier pair.
19. The method of claim 18, wherein adjusting the input bias voltage further comprises:
amplifying the clamping voltage to generate the th voltage when the power supply is at the th supply voltage, and
when the power supply is at a second supply voltage less than the th supply voltage, the clamp voltage is not amplified to generate the th voltage.
20. The method of claim 18 or 19, wherein the amplifier pair is configured as a class ab amplifier.
Technical Field
Exemplary and non-limiting embodiments of the present invention relate generally to power amplifiers and more particularly to automotive audio power amplifiers.
Background
During daily commutes in modern cities, people are often trapped in crowded traffic, especially during peak hours. In order to reduce carbon dioxide emissions and reduce other pollutants when automobiles are in a traffic jam or waiting for a traffic light, most automobile manufacturers have introduced start-stop engine functionality to automobiles. With this start-stop engine function, the vehicle engine will automatically shut off when the vehicle is trapped in a traffic jam, and then restart when the vehicle continues to move forward as the traffic jam clears. When the vehicle engine is restarted, a large inrush (in-rush) current is suddenly drawn from the vehicle battery, resulting in a rapid drop in the battery voltage. After the vehicle engine is restarted, the battery will return to the normal voltage level again. The supply voltage of the in-vehicle entertainment system comes directly from the battery of the car, so the in-vehicle entertainment system will experience the same voltage variations throughout the start-stop process.
Generally, when an automobile engine is in a starting state, a capacitor of an external circuit for establishing a static operating point has a rapid discharge behavior. This will result in the power amplifier of the car radio system not working properly, so that the power amplifier of the car audio system is set to a mute state so that no sound (including transient noise from the speakers) can be heard.
Today, people are constantly pursuing more and more comfortable driving experiences, so that the performance requirements for in-vehicle entertainment systems are much higher than before. Therefore, interruption of the audio output is not acceptable, and such interruption is not desirable even in the startup state. Current onboard sound quality standards do not allow for such interruption behavior either.
To avoid the above problems, well-known external circuit solutions are commonly used, in which step is taken to use a dc/dc regulator to stabilize the battery voltage during start-stop, however, this solution requires several peripherals and bulky LC components, resulting in increased overall cost, circuit board size, and system complexity.
Thus, another solution is proposed which is often employed in automobiles, in which the lowest operating voltage is set to half the supply voltage Vcc (e.g., half the battery voltage , if the battery voltage is 12V, Vcc/2-12V/2-6V) a typical circuit configuration of this solution is shown in fig. 1, which includes a clamp circuit M1, a class ab amplifier M2, and a Common Mode Feedback (CMFB) circuit M3. in the circuit shown in fig. 1, the clamp circuit M1 is set to provide a clamp voltage Vsvr-Vcc/4 as its input bias voltage at an SVR (supply voltage suppression) node to a class ab amplifier M2. the class ab amplifier is a typical amplifier circuit configuration for driving a speaker in an automobile radio system, which typically includes pairs of amplifiers (such as an operational amplifier) and four feedback resistors Rf1, Re 27 and Re coupled between the respective outputs of the pair of amplifiers and inputs of Rf 26, which are typically held at equal resistance values, and thus the amplifier output of the amplifier Rf 27 is held down by a constant, i.e., constant, when the amplifier Rf amplifier load is operating at a constant, the Vcc input voltage of the amplifier load, which is reduced by a constant, i.e., constant, and the amplifier load of the amplifier Rf amplifier load of the amplifier when the amplifier is set to a constant at a constant, which is constant at a constant load of the Vcc input load of the Vcc load of the output of the
However, while the common mode feedback scheme may solve the start-stop problem, it additionally introduces a positive feedback loop, which may greatly affect the stability of the overall audio system, especially when the car is powered up. For example, if the external load is a capacitive load such as 10nF, the circuit may cause undesirable oscillations. In practical applications, external capacitance is unavoidable. For example, if the speaker has a resistance of 2 ohms, oscillation is unavoidable unless the capacitance caused by the speaker is less than 2nF, but such a small capacitance is not practical.
Disclosure of Invention
The proposed power amplifier eliminates the common mode feedback circuit, thereby avoiding the possibility of causing oscillations even when large capacitive loads are connected, and thus making the car audio system more stable.
An th aspect of the invention relates to a class of power amplifier including a clamp circuit (N1) configured to provide a clamp voltage from a power supply, an amplifier pair (N2) having a plurality of -th inputs coupled to the clamp circuit, an output for providing an amplified signal, and a plurality of second inputs, and a bias circuit (N3) coupled between the clamp circuit and the plurality of second inputs of the amplifier pair and configured to adjust an input bias voltage of the amplifier pair such that an output bias voltage of the amplifier pair varies proportionally with variations in the supply voltage.
A second aspect of the invention relates to methods for adjusting a bias voltage of a power amplifier including a clamp circuit, a bias circuit, and an amplifier pair, the method including providing the clamp voltage from a power supply by the clamp circuit, adjusting an input bias voltage of the amplifier pair by the bias circuit so that an output bias voltage of the amplifier pair varies proportionally with variations in the power supply voltage, and providing an amplified signal by the amplifier pair.
A third aspect of the invention relates to a bias circuit comprising th buffers and th buffers, wherein each th buffer has at least inputs and outputs, wherein inputs of the th buffer are coupled to an input node, wherein an output of the th buffer is coupled to a th input of the second buffer through a th resistor, wherein the input node is coupled to a second input of the second buffer, wherein the second resistor is coupled between the output of the second buffer and the th input, and wherein the outputs of the second buffer are respectively coupled to a plurality of bias resistors.
Drawings
Embodiments of the invention, a preferred mode of use, and other objects are best understood by referring to the following description of the embodiments in connection with the accompanying drawings, wherein like reference numbers generally indicate like elements.
Fig. 1 is a schematic diagram illustrating a prior art power amplifier circuit incorporating common mode feedback;
fig. 2 is a block diagram illustrating a power amplifier circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a power amplifier circuit according to an embodiment of the present invention;
fig. 4 shows simulation results of examples of a power amplifier circuit according to an embodiment of the invention, an
Fig. 5 is a flow diagram illustrating a method for adjusting a bias voltage of a power amplifier circuit, according to an embodiment of the invention.
Detailed Description
preferred embodiments will be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the present disclosure have been shown, however, the present disclosure may be embodied in a variety of ways and therefore should not be construed as limited to only the embodiments disclosed herein.
In the following, various embodiments and implementations of the invention and aspects thereof will be described using several alternatives. It should be noted that all the described alternatives can be provided alone or in any possible combination (including also the combination of the individual functions of the various alternatives), according to specific needs and limitations.
Referring initially to fig. 2, a block diagram of a power amplifier circuit is shown in accordance with an embodiment of the present invention. As shown in fig. 2, the proposed power amplifier circuit of the car audio system mainly comprises three modules, namely a clamp circuit N1, an amplifier pair (e.g. class ab amplifier) N2 and a bias circuit N3, wherein the clamp circuit N1 and the amplifier pair N2 are similar to those shown in fig. 1.
Each circuit block N1, N2, N3 will be described in more detail below with reference to fig. 3. Fig. 3 shows a schematic diagram of a power amplifier circuit according to an embodiment of the invention.
As shown in fig. 3, clamp N1 may include two resistors R1 and R2 in series between the power supply (Vcc) and ground in this embodiment, the resistance of resistor R1 may preferably be set to 3 times the resistance of resistor R2, i.e., R1 —
Although two resistors R1 and R2 are shown in fig. 3, it will be understood by those of ordinary skill in the art that the number of voltage dividing resistors connected in series between the power supply and ground is not limited to two, and any number of resistors may be employed as long as they can divide the power supply voltage as needed to obtain the desired divided voltage value.
The amplifier pair N2 is configured as exemplified above with reference to fig. 1 and typically comprises pairs of amplifiers (i.e. the th amplifier AMP + and the second amplifier AMP-) and four feedback resistors Rf1, Rf2, Re1 and Re2, which are typically coupled between the respective outputs and inputs of the pair of amplifiers in embodiments, the resistance value of the resistor Rf1 may preferably be set to 16 times the resistance value of the resistor Re1, i.e. Rf 1-16 Re1, and the resistance value of the Rf2 is preferably set to 20 times the resistance values of the resistors Re1 and Re2, i.e. Rf 2-20 Re 1-20 Re2, but the invention is not limited to any particular number of resistors or their resistance values, the number and resistance values of which may be adjusted accordingly depending on the needs of the actual application and performance requirements.
In practical applications, an input signal, e.g., an audio signal, may be input to the th, i.e., non-inverting, input of the th amplifier AMP + via a capacitor C _ in, which filters out the DC component of the audio signal so that the net signal is input to the non-inverting input of the amplifier AMP +.
In contrast to the amplifier circuit shown in fig. 1, the power amplifier circuit according to an embodiment of the invention shown in fig. 3 further comprises a bias circuit N3.
In embodiments, the bias circuit N3 may include two buffer amplifiers (or simply buffers) B1 and B2, where each of buffers B1 and B2 have at least inputs and outputs.
In this embodiment, buffer amplifier B1 may be configured to amplify, e.g., by a factor of 2, the voltage Vsvr at its input to the SVR node when the power amplifier circuit is operating normally (i.e., the power supply is held at Vcc), and to output the voltage Vsvr at its input directly without amplification when the power supply voltage drops from Vcc to Vcc/2, resulting in a voltage Vsvr at its output.
Further, with this configuration, resistors R7. may be further coupled steps between the output of buffer amplifier B1 and the th input (i.e., inverting input) of buffer amplifier B2, and the voltage at the SVR node may be coupled to the th input of buffer amplifier B2 via buffer amplifier B1 and resistor R7.
feedback resistors R8. may be coupled between the input and the output Vob of the buffer amplifier B2. in the present embodiment, the resistance value of the resistor R7 may preferably be set to 2 times the resistance value of the resistor R8, i.e., R7 — 2R 8.
The output Vob of the buffer amplifier B2 may in turn be coupled to the inverting inputs of the two amplifiers AMP + and AMP-of the amplifier pair N2 through two bias resistors Rb1 and Rb2, respectively, to provide an input bias voltage thereto.
Two series bias resistors Rb1 and Rb2 are connected in parallel with feedback resistors Re1 and Re2 between and the inverting inputs of the amplifier AMP + and AMP-in this embodiment, the resistance value of Rb1 may preferably be set to half of Rf1, i.e., Rf 1-2 Rb1, and the resistance value of Rb2 may preferably be set to half of Rf2, i.e., Rf 2-2
In another embodiments, bias circuit N3 may further include another buffer amplifiers B3 coupled between the SVR node and the second input (i.e., the non-inverting input) of buffer amplifier B2 buffer amplifier B3 is used to pass the voltage at the input, i.e., the voltage Vsvr at the SVR node, to the subsequent circuitry, i.e., buffer amplifier B2 As examples, buffer B3 may be implemented with a unity gain buffer amplifier, e.g., by connecting the output of an operational amplifier and its inverting input from , and coupling a signal source to the non-inverting input.
In an example of the above structure, R1 ═ 3R2, R4 ═ R5, Rf1 ═ 2Rb1 ═ 16Re1, Rf2 ═ 2Rb2 ═ 20Re1 ═ 20Re2, and R7 ═ 2R8 are provided. In this example, when the power amplifier circuit is operating normally, i.e., the power supply voltage is not dropping and is held at Vcc, the voltage Vsvr at the SVR node at this time is Vcc/4; and the input to the amplifier is biased at Vcc/4 due to the inherent characteristics of the amplifiers AMP + and AMP-. Meanwhile, the non-inverting input terminal of the buffer amplifier B2 is Vcc/4, and the inverting input terminal of the buffer amplifier B2 is also Vcc/4 due to the characteristics of the operational amplifier. In the case where the power supply voltage is normal, the buffer amplifier B1 amplifies its input voltage by two times and outputs 2Vsvr, i.e., Vcc/2. Considering the proportional relationship of R7 and R8 resistances, the output Vob of the buffer amplifier B2 will be Vcc/8. Thus, the bias voltages at the AMP + and AMP-outputs are Vcc/4+ (Vcc/4-Vcc/8) × Rf1/Rb1 ═ Vcc/2 and Vcc/4+ (Vcc/4-Vcc/8) × Rf2/Rb2 ═ Vcc/2, respectively. That is, the outputs OUTP and OUTM of the amplifier pair N2 are both biased at Vcc/2 under normal supply voltages.
In this example, the ac gain of the th amplifier AMP + is (Rf1/(Rb1(Re1+ Re2)/(Rb1+ Re1+ Re2))) -10 and the ac gain of the second amplifier AMP-is- (Rf2/(Re1+ Re2)) -10. thus, a total ac gain of 26dB can be obtained.
In the above example, when the power supply voltage drops from Vcc to Vcc '(e.g., Vcc' ═ Vcc/2) upon entering the start-stop process, due to the large capacitance C connected at the SVR nodeSVRTherefore, the voltage Vsvr at the SVR node is still held at Vcc/4, and the non-inverting input of buffer amplifier B2 and its inverting input are also heldAt Vcc/4, at this time, due to the drop in the supply voltage, an internal circuit (not shown) triggers buffer B1 to operate with an amplifier that is switched from a 2 times voltage gain amplifier to a unity gain amplifier so that the output voltage is approximately equal to Vsvr, i.e., Vcc/4. in this case, the voltage across resistor R7 is zero so that no current flows through resistors R7 and R8. with the result that the output Vob of buffer amplifier B2 rises to Vcc/4. correspondingly, the voltage across Rb1 is also zero at this time, and no current flows through Rb1 so that the DC output of amplifier Amplifier AMP + of N2 is also Vcc/4 Vcc'/2. that is, the current output bias voltage of OUTP is still half of the current supply voltage Vcc . similarly, the current output bias voltage of OUTM is also half of the current supply voltage Vcc . thus, the output bias voltage of amplifier to N2 or the entire power amplifier circuit operates in proportion to the entire Vcc so that the entire power amplifier operates correctly.
Fig. 4 shows simulation results illustrating the operation performance of examples of the power amplifier circuit according to the embodiment of the present invention, in which a normal power supply voltage Vcc is set to 12V and drops to 6V when an automobile engine is restarted, it can be seen from fig. 4 that when the power supply voltage jumps from 12V to 6V as shown in fig. 4(a), the bias voltage of the power amplifier circuit is adjusted from 6V to 3V as shown in fig. 4(c), the clamp voltage Vsvr is maintained at around 3V as shown in fig. 4(b) during this process, and the ac gains of the two amplifiers of the power amplifier circuit are equal as shown in fig. 4(c), so that the total ac output of the amplifier circuit is kept stable as shown in fig. 4 (d).
advantages of the power amplifier circuit according to embodiments of the present invention are that the proposed power amplifier circuit eliminates the use of a common mode feedback circuit, and the same feedback to OUTP and OUTM can be obtained by adjusting the voltages of the bias resistor and the feedback resistor.
Another advantage of the power amplifier circuit according to the embodiment of the present invention is that the AMP + and AMP-have 20 times dc gain for the output of the common mode feedback in the conventional circuit shown in fig. 1, and thus the mismatch of the feedback resistors Re1, Rf1, Re2 and Rf2 themselves will also be amplified by 20 times, resulting in a large offset, whereas the power amplifier circuit according to the embodiment of the present invention has only 2 times dc gain from the output Vob of the buffer B2 to the output of the power amplifier circuit through the bias resistor Rb1 and the feedback resistor Rf1 or through Rb2 and Rf2, so that the mismatch of the resistors Rb1 and Rf1 or Rb2 and Rf2 themselves is significantly reduced by the amplification factor, which makes the dc offset significantly reduced compared to the conventional circuit shown in fig. 1.
Fig. 5 is a flow diagram illustrating a method for adjusting a bias voltage of a power amplifier circuit according to an embodiment of the invention. The power amplifier circuit has a structure as shown in fig. 3, and includes a clamp circuit N1, a bias circuit N3, and an amplifier pair N2. As shown in fig. 5, in block 501, a clamp voltage Vsvr obtained from the power supply divided voltage is supplied by a clamp circuit N1. In block 502, the input bias voltage of the amplifier pair N2 is adjusted by the bias circuit N3 according to the change in supply voltage so that the output of the amplifier pair changes proportionally with the change in supply voltage. In block 503, the amplified signal is output by amplifier pair N2.
The description above with reference to the drawings is given by way of illustration only for the purpose of illustrating the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope, and are based on the principles of the invention as described above. Furthermore, all examples mentioned herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to the scope of the invention. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
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