阅读说明：本技术 层、多级元件、多级元件制造方法和驱动多级元件的方法 (Layer, multi-stage element, method for manufacturing multi-stage element, and method for driving multi-stage element ) 是由 成明模 金洪范 朴真善 郑进元 于 2018-10-18 设计创作，主要内容包括：根据本发明一实施例的层可以在导带的低级电子能量范围内呈现第一电子态数,并且在该导带的高于低级电子能量范围的高级电子能量范围内呈现第二电子态数,其中局域态可以存在于该低级电子能量范围内和该高级电子能量范围之间。(A layer according to an embodiment of the invention may exhibit a number of electronic states in a lower electron energy range of the conduction band and a second number of electronic states in an upper electron energy range of the conduction band above the lower electron energy range, where localized states may exist between the lower electron energy range and the upper electron energy range.)

A seed layer of exhibiting a number of electron states in a lower electron energy range of the conduction band and a second number of electron states in an upper electron energy range of the conduction band above the lower electron energy range,

wherein a localized state exists between the low electron energy range and the high electron energy range.

A seed layer of comprising an amorphous region and a plurality of crystalline regions surrounded by the amorphous region, wherein a quantized on state is provided by resonance matching between any of a plurality of energy states of the amorphous region and any of a plurality of second energy states of the crystalline region.

A multi-stage element of types, comprising:

a gate electrode;

a active layer formed on the side of the gate electrode;

a second active layer formed on the side of the active layer;

a source electrode and a drain electrode; and

a barrier layer for separating the th active layer and the second active layer,

wherein the number of active layers in which channels are formed among the active layers including the th active layer and the second active layer is controlled according to the magnitude of a gate voltage applied to the gate electrode.

The manufacturing method of kinds of multi-stage elements includes the following steps:

forming an th active layer over a substrate in a state where the substrate is prepared in a chamber;

forming a barrier layer; and

a second active layer is formed on the first active layer,

wherein at least of the steps of forming the th active layer and the steps of forming the second active layer comprise:

a source gas injection/pressurization step of injecting a metal precursor source gas including a metal precursor into the chamber in a state where an outlet of the chamber is closed, thereby increasing a pressure in the chamber and adsorbing the source gas onto the substrate of the hermetically sealed chamber;

th main purge step of purging the chamber, located after the source gas injection/pressurization step;

a reaction gas injection step of injecting a reaction gas into the chamber after the th main purge step, and

a second main purge step of purging the chamber, located after the reaction gas injection step.

5, a method of driving a multi-stage element, comprising:

, applying gate voltage in gate voltage range to the gate electrode to activate active layer;

a second step of applying a gate voltage in a second gate voltage range to the gate electrode, the gate voltage being higher than the gate voltage in the th gate voltage range, and

applying a gate voltage in a third gate voltage range to the gate electrode, the gate voltage being higher than the gate voltage in the second gate voltage range, thereby activating the th and second active layers.

Technical Field

The invention relates to a layer, a multilevel element manufacturing method and a method of driving a multilevel element.

Background

In recent years, with the development of intelligent devices and artificial intelligence computer technologies, the demand for high-performance devices having high performance and versatility has rapidly increased.

However, due to continued microminiaturization and high integration, binary element fabrication techniques leading to the existing semiconductor industry are expected to reach limits in technology, economy, and principle. In other words, the development method based on scaling down the conventional MOSFET has difficulty in scaling down the technology itself, and the scaling-down based method is considered to have fundamental limitations.

In order to overcome this limitation, research on a multi-stage element has been conducted, the multi-stage element that has been previously researched includes a single-electron transistor (SET) and a Resonant Tunneling Transistor (RTT).

Accordingly, the inventors have invented a layer that exhibits excellent multi-stage characteristics while being formed by an easy and simple process, a multi-stage element including the layer, a multi-stage element manufacturing method, and a method of driving the multi-stage element.

Disclosure of Invention

It is an object of the present invention to provide layers with quantized on-states.

Another objects of the invention are to provide layers with quantized on-states that are energetically higher than the mobility edge.

Yet another objects of the invention are to provide layers with discrete on-states that depend on the energy level of an electron in the conduction band.

It is yet another objects of the present invention to provide layers that are resonance energy matched between the crystalline and amorphous regions.

It is still another objects of the present invention to provide kinds of multi-level devices having multi-level turn-on characteristics, and methods of manufacturing and driving the multi-level devices.

It is yet another object of of the present invention to provide manufacturing methods that can be performed by low temperature processes.

It is a further object of of the present invention to provide manufacturing methods that can be easily controlled for thickness.

However, the object to be achieved by the present invention is not limited to the above object.

A layer according to embodiments of the present invention may exhibit a number of electronic states in a lower electron energy range of the conduction band, a second number of electronic states in a higher electron energy range of the conduction band above the lower electron energy range,

wherein the localized state may exist between the low energy electron energy range and the high energy electron energy range.

According to embodiments, the number of electronic states in the local states in the conduction band may be 0.

According to embodiments, the maximum electron energy value in the low electron energy range may be less than the minimum electron energy value in the high electron energy range.

According to examples, the number of electronic states has a normal distribution with respect to the value of the electron energy at which the number of electronic states in the lower electron energy range is the largest.

According to embodiments, the maximum value of the number of electronic states in the low level of electronic energy may be less than the minimum value of the second number of electronic states in the high level of electronic energy range.

According to embodiments, the on state may exist in both the low electron energy range and the high electron energy range.

According to embodiments, a mobility edge exists in the conduction band, the mobility edge is the lowest energy state that an electron can exist, and the lower-order electron energy range and the higher-order electron energy range may have higher energy values than the mobility edge.

According to embodiments, the curve of the number of electronic states in the low-order electron energy range and the curve of the second number of electronic states in the high-order electron energy range may be discontinuous from each other.

Layers according to embodiments of the present invention may include an amorphous region and a plurality of crystalline regions surrounded by the amorphous region, wherein a quantized on state may be provided by resonance matching between any th energy state of a plurality of th energy states of the amorphous region and any second energy state of a plurality of second energy states of the crystalline region.

According to embodiments, each crystalline region may have nanometer dimensions.

According to embodiments, the crystalline region may exhibit quantum confinement effects.

According to embodiments, the quantum confinement effect of the crystalline region can be exhibited in the three-axis direction.

According to embodiments, the quantized on-state may be provided at a higher electron energy than a mobility edge in the conduction band, which is the lowest energy state in which an electron can exist.

According to embodiments, multiple crystalline regions may be randomly distributed and two-dimensionally arranged in the amorphous region.

According to embodiments, the quantized on-state may exist within a predetermined energy range.

According to embodiments, the localized state may exist in an electron energy range higher than the predetermined electron energy range.

According to embodiments, the conducting state may exist in a higher electron energy range than the electron energy range corresponding to the non-conducting state.

According to embodiments, the number of energy states may be greater than the number of second energy states.

According to embodiments, resonance matching can provide several quantized electronic states in a higher energy range than the mobility edge, in terms of density of energy states (DOS).

According to embodiments, resonance matching can provide at least two discrete electronic states in an energy range higher than the mobility edge in terms of density of energy states (DOS).

According to embodiments, the quantized on-state allows limited carrier motion within a predetermined energy range.

The multi-stage device according to embodiments of the present invention may include a gate electrode, a th active layer formed on the side of the gate electrode, a second active layer formed on the side of the th active layer, a source electrode and a drain electrode, and a blocking layer for separating the th active layer and the second active layer, wherein the number of active layers in which channels are formed, among the active layers including the th active layer and the second active layer, may be controlled according to the magnitude of a gate voltage applied to the gate electrode.

According to embodiments, the distance between the th active layer and the gate electrode may be shorter than the distance between the second active layer and the gate electrode.

According to embodiments, a active layer, a barrier layer, and a second active layer may be deposited in sequence.

According to embodiments, the gate electrode can be divided into a gate voltage range, a second gate voltage range, and a third gate voltage range, wherein the , second, and third gate voltage ranges can occur in order of increasing gate voltage.

According to embodiments, only the th active layer may be activated when a gate voltage within the th gate voltage range is applied to the gate electrode, and the th and second active layers may be activated when a gate voltage within the third gate voltage range is applied to the gate electrode.

According to embodiments, when the gate electrode in the second gate voltage range is applied to the gate electrode, only the th active layer may be activated, and an increase in magnitude of a current flowing through the th active layer due to an increase in the gate voltage in the second gate voltage range may be smaller than an increase in magnitude of a current flowing through the th active layer due to an increase in the gate voltage in the th gate voltage range.

According to embodiments, even when the gate voltage in the second gate voltage range is increased, the amount of current flowing through the th active layer may be constant.

According to embodiments, the th active layer may be in a saturated state in the second gate voltage range.

According to embodiments, the barrier layer includes a th barrier layer provided between the th and second active layers and a third barrier layer provided on the second active layers, wherein the source and drain electrodes may be in contact with the third barrier layer.

According to embodiments, when a gate voltage in the second gate voltage range is applied to the gate electrode, a field applied to the second active layer by the gate electrode may be shielded by a current flowing through the th active layer.

According to embodiments, the source and drain electrodes may be in contact with only of the and second active layers.

According to embodiments, the source and drain electrodes may not be in contact with the th and second active layers.

According to embodiments, the multilevel element may further include a barrier layer between the gate electrode and the active layer, wherein the barrier layer between the gate electrode and the active layer, the active layer, and the barrier layer separating the active layer and the second active layer may form a quantum well.

According to embodiments, at least of the and second active layers can exhibit a number of electronic states in a lower electron energy range of the conduction band and a second number of electronic states in an upper electron energy range of the conduction band above the lower electron energy range, wherein a localized state can exist between the lower electron energy range and the upper electron energy range.

According to examples, the number of electronic states has a normal distribution with respect to the value of the electron energy at which the number of electronic states in the lower electron energy range is the largest.

According to embodiments, at least of the and second active layers can include an amorphous region and a plurality of crystalline regions surrounded by the amorphous region, wherein a quantized on state can be provided by matching between any th energy state of a plurality of th energy states of the amorphous region and any second energy state of a plurality of second energy states of the crystalline region.

According to embodiments, the quantized on-state may allow a limited current to flow between the source electrode and the drain electrode when the gate voltage applied to the gate electrode is within a predetermined voltage range.

A multi-stage component manufacturing method according to embodiments of the present invention may include the steps of forming a th active layer above a substrate in a state where the substrate is prepared in a chamber, forming a barrier layer, and forming a second active layer, wherein at least of the step of forming the th active layer and the step of forming the second active layer include a source gas injection/pressurization step of injecting a metal precursor source gas including a metal precursor into the chamber in a state where an outlet of the chamber is closed, thereby increasing a pressure in the chamber and adsorbing the source gas onto the substrate of the hermetically sealed chamber, a th main purge step of purging the chamber after the source gas injection/pressurization step, a reaction gas injection step of injecting a reaction gas into the chamber after the th main purge step, and a second main purge step of purging the chamber after the reaction gas injection step.

According to embodiments, the source gas injecting/pressurizing step may further include increasing the pressure within the chamber to a predetermined pressure by injecting the source gas and maintaining the predetermined pressure by closing an inlet of the chamber.

According to embodiments, the source gas injection/pressurization step may include at least two sub-injection/pressurization steps and a sub-purge step between the at least two sub-injection/pressurization steps.

According to embodiments, the thickness of the active layer formed by the step of forming the th active layer may be greater than 1.5 nm.

According to embodiments, the method can further include the step of including forming a source electrode and a drain electrode in contact with the second active layer.

According to embodiments, the method can further include forming a barrier layer on the second active layer and forming a source electrode and a drain electrode in contact with the barrier layer on the second active layer.

A method of driving a multi-level cell according to embodiments of the present invention may include a step of applying a gate voltage in a th gate voltage range to a gate electrode to activate a th active layer, a second step of applying a gate voltage in a second gate voltage range to the gate electrode, the gate voltage being higher than a gate voltage in a th gate voltage range, and a third gate voltage range, the gate voltage being higher than a gate voltage in the second gate voltage range, to activate a th active layer and the second active layer.

According to embodiments, in the second step, the active layer may remain in an activated state and the second active layer may be in an inactivated state.

According to embodiments, in the second step, the activation of the second active layer may be shielded by a current flowing through the th active layer.

Layers according to embodiments of the present invention may exhibit quantized energy states in an energy range above the mobility edge.

Layers according to embodiments of the present invention may exhibit discrete local states in the energy range above the mobility edge.

Layers according to embodiments of the present invention may exhibit limited carrier mobility in the energy range above the mobility edge.

Layers according to embodiments of the present invention may exhibit resonance energy matching.

The multi-stage element and the driving method thereof according to embodiments of the present invention can exhibit multi-stage turn-on characteristics.

The multi-level cell and the driving method thereof according to embodiments of the present invention may have at least two turn-on voltages.

The multi-stage device and the driving method thereof according to embodiments of the present invention can exhibit a constant source/drain current even when the gate voltage is swept.

The multi-stage element and the driving method thereof according to embodiments of the present invention may exhibit high stability.

The multilevel element manufacturing method according to embodiments of the present invention may be performed by a low temperature process.

The multilevel element manufacturing method according to embodiments of the present invention can provide an environment in which the thickness can be easily controlled.

The technical effects of the present invention are not limited to the above-described effects, and other effects of the present invention will be clearly understood by those skilled in the art from the following description.

Drawings

Fig. 1 shows embodiments of a multi-stage element according to the invention.

Fig. 2 and 3 show embodiments of a multilevel active layer according to the invention.

Fig. 4 shows embodiments of a multi-stage drive according to the invention.

Fig. 5 shows the shielding effect according to embodiments of the present invention.

Fig. 6-11 illustrate a multi-level mechanism according to embodiments of the invention.

Fig. 11 and 12 show an th modified embodiment of the invention.

Fig. 13 and 14 show a second modified embodiment of the present invention.

Fig. 15 is a flow chart illustrating a method of manufacturing a multilevel element according to embodiments of the invention.

Fig. 16 is a flowchart showing in detail step S120 according to embodiments of the present invention.

Fig. 17 and 18 show in detail step S210 according to embodiments of the present invention.

Fig. 19 shows process conditions of the multi-stage element used in the experimental example of the present invention.

Fig. 20 shows TEM images of the active layer obtained in the experimental example of the present invention.

Fig. 21 shows the I-V characteristics of a multilevel element fabricated according to embodiments of the present invention.

Fig. 22 and 23 show the I-V characteristics of a multi-stage element manufactured according to a modified embodiment of the present invention.

Fig. 24 shows the results of measuring the FET characteristics depending on the thickness of the active layer according to embodiments of the present invention.

Fig. 25 shows the results of testing the reliability of the multilevel elements fabricated according to embodiments of the present invention.

Detailed Description

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the specification, when any element is referred to as being "on" another element, it means that the element may be directly formed on the other element or a third element may be interposed therebetween. In the drawings, the thickness of layers and regions may have been exaggerated in order to clearly illustrate features of the embodiments.

In addition, although the terms "," "second," "third," etc. may be used to describe various elements of various embodiments of the invention, these elements should not be limited by these terms.

In addition, the terms "comprising," "having," and the like, are intended to mean that there are recited features, numbers, steps, elements, components, or combinations thereof, but do not preclude the possibility of there being or additional features, numbers, steps, elements, components, or combinations thereof.

Further, in the following description, a detailed description of related known functions and configurations will be omitted when it may unnecessarily obscure the subject matter of the present invention.

Fig. 1 shows embodiments of a multilevel element according to the invention fig. 2 and 3 show embodiments of a multilevel active layer according to the invention.

A multi-level cell according to embodiments of the present invention does not refer to a conventional cell having binary states (0 and 1), but may refer to a cell having ternary or higher states (0, 1 and 2, or 0, 1, 2 and greater than 2). The conventional cell may have only two states (on and off), whereas a multi-level cell according to embodiments of the present invention may have a third state in addition to "on" and "off states.A multi-level cell according to embodiments of the present invention will be described below with reference to FIG. 1.

Referring to fig. 1, a multi-level cell 100 according to embodiments may include a substrate 110, a gate electrode 120, an insulating layer 130, an active structure 135, and at least of a source electrode 180 and a drain electrode 185.

The substrate 110 is not limited to any particular type, and may include, for example, at least of a silicon substrate, a glass substrate, and a flexible substrate.

The gate electrode 120 serves to receive a gate voltage, and may be made of a conductive material, for example, a metal material.

The insulating layer 130 serves as a dielectric layer and may be made of, for example, at least of a silicon-based dielectric material and a metal oxide-based dielectric material the thickness of the insulating layer 130 may be determined according to the operating range of the applied gate voltage.

The active structure 15 may include at least active layers and at least barrier layers the active layers and barrier layers may be alternately deposited in this case, the number of active layers may be at least two and the barrier layers may be deposited in contact with at least of the two sides of the active layer.

For example, as shown in FIG. 1, when the th active layer 150 and the second active layer 170 are provided, the th barrier layer 140 may be disposed between the insulating layer 130 and the th active layer 150, and the second barrier layer 160 may be disposed between the th active layer 150 and the second active layer 170. in this case, the gate electrode 120, the insulating layer 130, the th barrier layer 140, the th active layer 150, the second barrier layer 160, and the second active layer 170 may be sequentially deposited in the following order.

According to examples, each of the barrier layer 140, the active layer 150, the second barrier layer 160, and the second active layer 170 may have a thickness of a few nanometers.

According to examples, as shown in fig. 2 and 3, at least of the active layer 150 and the second active layer 170 may be composed of a layer including an amorphous region (AM _ R) and a plurality of crystalline regions (NC _ R) surrounded by the amorphous region (AM _ R), that is, in the active layer, the amorphous region (AM _ R) and the crystalline regions (NC _ R) may exist together at .

In this case, each of the crystalline regions (NC _ R) has a nano size, and may have a quantum confinement effect. In particular, the crystallized regions (NC _ R) may have a size of several nanometers, for example, about 3nm, and the average distance between the crystallized regions may be about 2.5 nm. In other words, the crystalline regions (NC _ R) may be spaced apart from each other by an average distance of about 2.5nm, and may have an island shape surrounded by the amorphous regions (AM _ R). Further, the crystallized regions (NC _ R) may be randomly distributed in the two-dimensional plane of the amorphous regions (AM _ R). Therefore, the crystalline region (NC _ R) can exhibit a quantum confinement effect in the three-axis direction. That is, the crystal region (NC _ R) can be displayed not only in the thickness direction but also in the planar direction.

The active layer structure may provide multi-level characteristics, a detailed description of which will be provided below.

According to examples, at least of the active layers 150 and 170 can include a metal oxide, for example, when the active layer includes a metal oxide, the metal oxide can be zinc oxide (ZnO).

At least of the th barrier layer 140 and the second barrier layer 160 can include at least of an organic material, an inorganic material, and an organic-inorganic composite material, the organic material can be 4MP (4-p-hydroxyphenylthiophenol) when the barrier layer includes an organic material, and the organic-inorganic composite material can be 4MP with Al attachment, i.e., Al4MP, when the barrier layer includes an organic-inorganic composite material.

For example, when other layers are formed after the formation of the th active layer 150, the second blocking layer 160 may prevent the th active layer 150 from being unintentionally doped or precursors used for the deposition of another layer from penetrating into the th active layer 150.

According to embodiments, an active layer and a barrier layer adjacent to the active layer may form a superlattice structure with each other.

According to embodiments, the barrier layer may form an interface with the active layer such that the barrier layer may form a quantum well with respect to the active layer.

The source electrode 180 and the drain electrode 185 may be in contact with the uppermost active layer or the uppermost barrier layer. If the uppermost portion of the active structure 135 is the second active layer 170 as shown in fig. 1, the source electrode 180 and the drain electrode 185 may contact the second active layer 170. In this case, the source electrode 180 and the drain electrode 185 may not contact active layers other than the second active layer 170 and the blocking layer. The case where the source electrode 180 and the drain electrode 185 are in contact with the uppermost barrier layer will be described later.

According to examples, when the th active layer 150 is activated, current may flow from the source electrode 180 to the drain electrode 185, electrons from the source electrode 180 may sequentially tunnel through the second active layer 170 and the second barrier layer 160 and then flow along the th active layer 150 electrons passing through the th active layer 150 may sequentially tunnel through the second barrier layer 160 and the second active layer 170 and may then be provided to the drain electrode 185 furthermore, when the second active layer 170 is activated, current may flow from the source electrode 180 to the drain electrode 185 via the second active layer 170.

The multi-stage element according to embodiments of the present invention has been described above with reference to fig. 1to 3, hereinafter, a method of driving the multi-stage element according to embodiments of the present invention will be described with reference to fig. 4 to 5.

Fig. 4 shows embodiments of multilevel driving according to the invention, and fig. 5 shows embodiments of shielding effect according to the invention the method of multilevel driving according to embodiments of the invention can be implemented by the multilevel elements described above with reference to fig. 1-3.

Referring to fig. 4, a multi-level cell according to embodiments of the present invention may have a multi-level turn-on characteristic, in another aspect , a multi-level cell according to embodiments of the present invention may have a plurality of turn-on voltages, for example, a gate voltage applied to the gate electrode 120 may be divided into a -th gate voltage range (R1), a second gate voltage range (R2), and a third gate voltage range (R3), as shown in fig. 4, the second gate voltage range (R2) may have a higher voltage value than the -th gate voltage range (R1), further, the third gate voltage range (R3) may have a higher voltage value than the second gate voltage range (R2), and an IV curve characteristic depending on a driving voltage in each gate voltage range will be described below.

First, the lowest gate voltage in the th gate voltage range (R1) may become the th turn-on voltage when the th turn-on voltage is applied to the gate electrode 120, the th active layer 150 may be activated, i.e., turned on, and thus, current may flow between the source electrode 180 and the drain electrode 185 at this time, the second active layer 170 may be in an inactive state, i.e., an off state, next, the magnitude of current flowing between the source electrode 180 and the drain electrode 185 may increase as the voltage in the th gate voltage range (R1) increases, i.e., as the gate voltage increases in the th gate voltage range (R1), the ratio of current between the source electrode and the drain electrode may increase at the th slope.

For convenience of explanation, the application of the gate voltage in the third gate voltage range (R3) will be described first, and the application of the gate voltage in the second gate voltage range (R2) will be described later, when the gate voltage in the third gate voltage range (R3) higher than the third gate voltage range (R1) and the second gate voltage range (R2) is applied, not only the third active layer 150 may be turned on, but also the second active layer 170 may be turned on, i.e., the lowest gate voltage in the third gate voltage range (R3) may become the second on voltage, and thus, current may flow between the source electrode 180 and the drain electrode 185, unlike the gate voltage range (R1), in the third gate voltage range (R3), both the third active layer 150 and the second active layer 170 may be in an active state, and thus, when the third gate voltage range (R gate voltage range (R1) is applied, a larger amount of current may flow between the source electrode 180 and the drain electrode 180 may increase with the gate current flow rate in the third gate voltage range (R8536), i.e., the gate current may increase with the gate current flow rate increasing between the third gate electrode 185, the gate current flow rate increasing within the third gate current flow rate range (R8536).

When a gate voltage in a second gate voltage range (R2), which is higher than the gate voltage range of the th gate voltage range (R1) and lower than the third gate voltage range (R3), is applied to the gate electrode 120, only the th active layer 150 may be in an activated state, i.e., an on state, at which the magnitude of a current flowing between the source electrode 180 and the drain electrode 185 may be maintained even when the gate electrode in the second gate voltage range (R2) is increased, i.e., as the gate voltage in the th gate voltage range (R1) is increased, the magnitude of a current flowing between the source electrode 180 and the drain electrode 185 may be increased, for example, with a th slope, while as the gate voltage in the second gate voltage range (R2) is increased, the magnitude of a current flowing between the source electrode 180 and the drain electrode 185 may be changed less than a th slope, more specifically, as the gate voltage in the second gate voltage range (R63 2) is increased, the magnitude of a current flowing between the source electrode 180 and the drain electrode 185 may be maintained at a constant magnitude of a gate voltage (R8280) even when the gate voltage range R2 is increased, more specifically, the gate voltage may be said that when the gate voltage in the second gate voltage range R8236, the gate voltage range R8280 is maintained, the gate voltage range.

The selective activation of the active layer depending on the gate voltage range will be described below with reference to fig. 5.

As described above, when the gate electrode in the th gate voltage range (R1) is applied, as shown in fig. 5a, a Gate Field (GF) may be applied to the th active layer 150 so that the th active layer 150 may be turned on.

When a gate voltage within the second gate voltage range (R2) is applied, as shown in fig. 5b, the field induced by the gate voltage is shielded from reaching the second active layer 160 due to the current flowing through the active layer 150 (shielding effect). at this time, the blocking layer delays the gate voltage from reaching the second active layer 170. furthermore, when a gate voltage within the second gate voltage range (R2) is applied, the current between the source electrode 180 and the drain electrode 185 constantly flows due to saturation of the active layer 150 even when the gate voltage increases, in addition , the blocking layers 140 and 160 may delay the gating of the second active layer 170 and maintain a limited current flow through the active layer 150 even when the gate voltage within the second gate voltage range (R2) increases.

When the gate voltage within the third gate voltage range (R3) is applied, as shown in fig. 5c, the gate voltage reaches the second active layer 170 due to field penetration (field penetration), so that the second active layer 170 may be turned on.

In the description of the shadowing, the occurrence of the shadowing in the second gate voltage range (R2) has been described above, it being understood that the shadowing may also occur in the gate voltage range (R1).

In summary, when a gate voltage within a gate voltage range (R1) of is applied to the gate electrode 120, only the th active layer 150 may be activated and the second active layer 170 may not be activated, secondly, when a gate voltage within a second gate voltage range (R2) higher than the th gate voltage range (R1) is applied, the th active layer 150 may remain in an activated state but a current flowing through the th active layer 150 may reach a saturated state, further, the second active layer 170 may still be in an inactivated state, thirdly, when a gate voltage within a third gate voltage range (R3) higher than the second gate voltage range (R2) is applied, the th active layer 150 and the second active layer 170 may both be activated.

Thus, a multi-level cell according to embodiments of the present invention can have multiple turn-on voltages, i.e., a multi-level cell according to embodiments of the present invention can exhibit multi-level turn-on characteristics because it can have a second gate voltage range that is not present in conventional cells, i.e., a gate voltage range that does not affect the magnitude of the current even if the gate voltage is increased.

According to embodiments, the thickness of the active layer may be within a range where Field Effect Transistor (FET) characteristics occur, for example, when the active layer includes zinc oxide, it may have a thickness greater than 1.5nm, if the thickness of the zinc oxide is less than 1.5nm, the zinc oxide may lose FET characteristics, further, the thickness of the active layer may be 20nm or less, if the thickness of the active layer is greater than 20nm, the magnitude of current flowing through the th active layer 150 will increase, which increases the shielding effect of the th active layer 150, which prevents the gate voltage from penetrating into the second active layer 170 by Field penetration, in this case, an extremely high gate voltage is required to turn on the second active layer 170, which is disadvantageous in terms of power consumption, furthermore, the gate insulating film 130 should be thicker to withstand a high gate voltage, such a thick thickness does not meet another trend of transistor's reduction, , th active layer 150 is smaller or smaller, i.e., the active layer 150 may be able to turn on in a smaller range of gate voltage, which is advantageous in terms of power consumption, i.e., the gate voltage may be in a smaller range of , which may also correspond to the miniaturization of the gate voltage.

The characteristics of the multilevel element according to embodiments of the present invention have been described above with reference to fig. 4 and 5, the multilevel scheme according to embodiments of the present invention will be explained below with reference to fig. 6 to 10.

Fig. 6 to 10 show a multilevel mechanism according to embodiments of the present invention, in particular, fig. 6 shows resonance energy matching (resonance energy matching) according to embodiments of the present invention, fig. 7 shows density of states (DOS) according to embodiments of the present invention, fig. 8 shows density of states (DOS) of a crystalline layer, an amorphous layer and an active layer according to embodiments of the present invention, fig. 9 shows a wave function according to embodiments of the present invention, and fig. 10 shows a multilevel element according to embodiments of the present invention with respect to an energy band (energy band).

As described above with reference to FIG. 4, the multilevel element according to embodiments of the present invention may have a second gate voltage range (R2) in which an increase in gate voltage has no influence on current, since the multilevel element may be implemented by the second gate voltage range (R2), a multilevel scheme will be explained based on the th active layer 150 and the second active layer 170 generating the second gate voltage range (R2). for convenience, explanation will be made based on the th active layer 150, but needless to say, the technical idea of the present invention may also be applied to other active layers, such as the second active layer 170.

As described above, the active layer 150 according to embodiments of the present invention may be composed of a layer including an amorphous region (AM _ R) and a plurality of crystalline regions (NC _ R) surrounded by the amorphous region (AM _ R).

Referring to fig. 6, the th active layer 150 may have a large number of local states in the amorphous region (AM _ R). unlike this, the th active layer 150 may have discrete local states less than the local states of the amorphous region (AM _ R). in this case, there may be a resonance energy match between a specific energy state (AM _ E) among the local energy states of the amorphous region (AM _ R) and a specific energy state (NC _ E) among the local energy states of the crystalline region (NC _ R).

The hybridization resulting from this resonant energy matching can provide a quantified on-state. The quantized on-state may present a finite current at the same time as the on-state. The quantized on-state will now be described in more detail with reference to fig. 7 and 8 a.

Fig. 7 and 8a show density of states (DOS) according to embodiments of the invention for reference, the results of DOS simulations can be obtained by computing the formed active layer using the Vienna ab initio simulation (VASP) program by PBE (per-Burke-Ernzerhof) exchange correlation functional and the PAW (projection affix plus plane wave) pseudomorphism.

DOS in fig. 7 and 8a represents a change in the number of electron states due to an increase in electron energy, the th active layer 150 may have a valence band and a conduction band, as shown in fig. 7.

The valence balance can be divided by the mobility edge into an extended state (non-localized state) and a localized state. In addition, the conduction band can also be divided into an extended state and a localized state by the mobility edge. Here, the definition of the mobility edge will be described later with reference to fig. 8 c.

As shown in fig. 7 and 8a, the active layer 150 according to embodiments of the present invention may exhibit a th number of electronic states in a lower electron energy range (about 2.8eV to 2.9eV) of the conduction band and a second number of electronic states in a higher electron energy range (about 3.2eV or higher) of the conduction band higher than the lower electron energy range.

In other words, the maximum electron energy value (about 2.9eV) in the low electron energy range may be smaller than the minimum electron energy value (about 3.2eV) in the high electron energy range here, the maximum value of the th electron state number in the low electron energy range may be smaller than the minimum value of the second electron state number in the high electron energy range furthermore, as shown in FIG. 8a, the th electron state number may have a normal distribution with respect to the electron energy value in the low electron energy range in which the electron state number is the maximum.

According to embodiments, the lower and higher electron energy ranges (i.e., mobility edge quantization) may be provided at higher energies than the mobility edge in the conduction band-this may mean that the energy levels of the local states in the amorphous region (AM _ R) and the crystalline region of the th active layer 150 match each other above the mobility edge-thus, the th active layer 150 may assume on-states within the lower and higher electron energy ranges-at this time, the on-state within the lower electron energy range with the th number of electron states above the mobility edge may be defined as a quantized extended state.

Furthermore, there may be local states (i.e., a number of electronic states of 0) between the low-level electron energy range and the high-level electron energy range. This may mean that the crystalline region (NC _ R) of the active layer has no energy state between the low electron energy range and the high electron energy range. Therefore, the resonance energy (NC _ R) of the crystalline region and the resonance energy (AM _ R) of the amorphous region do not match each other between the low electron energy range and the high electron energy range.

According to embodiments, as described above, the low-level electron energy range may be provided by resonance energy matching between the crystalline region (NC _ R) and the amorphous region (AM _ R) of the active layer 150 at this time, the amorphous region (NC _ R) has a quantum confinement effect in the three-axis direction, and thus a curve defined by the low-level electron energy range and the th electronic state number may have a very limited area.

Unlike this, a conventional active layer including only crystalline regions or a conventional active layer including only amorphous regions cannot exhibit the low-level energy range above the mobility edge according to embodiments of the present invention.

In particular, with reference to fig. 8b, it can only be seen that in an active layer comprising only crystalline regions, a conduction tail is formed at the band edge, providing a continuous single expansion state in the conduction band. That is, it can be seen that there are no discrete energy levels in the conduction band.

Referring to fig. 8c, it can be seen that in the active layer including only the amorphous region, the conduction band is divided into an extended state and a local state by the mobility edge. However, it can be seen that the extended states in the conduction band are single states that exist continuously.

Theoretically, the amorphous region has several localized states that interfere with electron motion due to Anderson localization (Anderson localization). According to anderson localization, the conduction band is divided into localized and non-localized states according to electron energy. The local state may have a non-conducting state and the non-local state may have a conducting state. At this time, the criterion for separating the conduction band into local and non-local states may be defined as a mobility edge. If electron energy above the mobility edge is provided, the wave function can be expanded, thereby enabling charge transfer. In contrast, if the supplied electron energy is below the mobility edge, the wave function will be isolated, making charge transfer impossible.

In other words, it can be seen that an active layer comprising only amorphous regions has only a single continuous non-local state above the mobility edge of the conduction band, and therefore there are no discrete energy levels in the conduction band.

However, the active layer 150 according to embodiments of the present invention can exhibit a quantized on-state through resonance energy matching between the crystalline region (NC _ R) and the amorphous region (AM _ R). The quantized on-state can be confirmed by the presence of the th number of electronic states in a low-level energy range on DOS.

According to embodiments, the quantized on-state has a limited number of electronic states, and thus can provide the second gate voltage range (R2) as described above, in other words, the low-level energy range has a limited number of carriers that exist above the mobility edge and are discontinuous from the high-level energy range, and thus the amount of current flowing through the active layer 150 is limited even when the gate voltage within the second gate voltage range (R2) is increased, and thus, the th turn-on voltage caused by the th gate voltage range (R1) and the second turn-on voltage caused by the third gate voltage range (R3) can be clearly distinguished, and thus, the error occurrence rate can be reduced even if the operating margin of the gate voltage is widened.

Fig. 9 shows embodiments of wave functions according to the invention.

Referring to fig. 9a, the density of states in the active layer according to embodiments of the present invention can be divided into state 1 below the mobility edge of the conduction band, state 2 in the low-level energy range, and state 3 in the high-level energy level.

Fig. 9b to 9d show the results of the isosurface simulation of the wave function according to the divided state shown in fig. 9a, the wave function simulation being performed according to the density function theory. Fig. 9b shows the wave function for state 1. It can be seen that the wave functions are in a local state that does not overlap with other wave functions. In contrast, as shown in fig. 9c, the wave function of state 2 partially overlaps along the crystalline and amorphous regions. This indicates that state 2 has an on state. Furthermore, as shown in fig. 9d, the wave function of state 3 is distributed throughout the active layer. It is expected that the local states between state 2 and state 3 will have a wave function iso-surface as shown in fig. 9 b.

As described above with reference to fig. 9, from the perspective of the wave function according to each state, it can be determined that state 2 has a quantized on-state.

Fig. 10 shows a multi-stage element of an energy band according to embodiments of the present invention.

Referring to fig. 10a, in the multilevel element 100 according to embodiments of the present invention, the th barrier layer 140, the th active layer 150, and the second barrier layer 160 may form a quantum well.

The quantized expansion state as shown in fig. 10a may refer to an energy level providing a quantized energy state, which is generated by resonance energy matching between the crystalline region (NC _ R) and the amorphous region (AM _ R) as described with reference to fig. 6, fig. 7, and fig. 8a, the conduction band edge and the valence band edge of the th barrier 140 and the second barrier 160 may be measured by Ultraviolet Photoelectron Spectroscopy (UPS) and deep ultraviolet light (DUV).

Referring to fig. 10b, a gate voltage corresponding to the th gate voltage range (R1) is applied to the gate electrode 120, and a current may flow between the source electrode 180 and the drain electrode 185 as described above, the quantized on-state may be provided by resonance energy matching between the crystalline region (NC _ R) and the amorphous region (AM _ R) of the th active layer (150). in other words, as described above with reference to fig. 7 and 8a, the th number of electronic states in a lower energy range above the mobility side is provided, so that the th active layer 150 may be activated, and thus, a current may flow between the source electrode 180 and the drain electrode 185.

Referring to fig. 10c, when a gate voltage corresponding to the second gate voltage range (R2) is applied to the gate electrode 120, only a limited number of electrons may pass through the active layer 150 of the in other words, within the second gate middle voltage range (R2), energy between the low level energy range and the high level energy level as described above with reference to fig. 7 may be provided.

Referring to fig. 10d, when a gate electrode corresponding to the third gate voltage range R3 is applied to the gate electrode 120, the second active layer 170 may be activated. Accordingly, a current flowing through the active layer 170 may be generated by the source electrode 180 and the drain electrode 185.

In summary, as shown in FIG. 4, the multilevel cell according to embodiments of the present invention has a second gate voltage range within which the magnitude of the current does not change even though the gate voltage is swept, in other words, the second gate voltage range can be clearly distinguished from the and third gate voltage ranges, which means that the multilevel turn-on characteristic is provided by the second gate voltage range.

The mechanism of the second gate voltage range has been described above with reference to fig. 6 to 10. In other words, as shown in fig. 7 and 8a, the active layer has a quantized expansion state. In particular, the active layer has a quantized expansion state above the mobility edge. Since the active layer has a "quantized" expansion state, it can have a finite number of carriers within a particular gate voltage range.

In other words, the current flowing through the active layer is substantially unchanged in the second gate voltage range. This may mean that in the second gate voltage range, a current of a maximum amount of current may flow through the active layer due to the already quantized spreading state.

In addition, the magnitude of the current flowing through the th active layer is substantially constant over the second gate voltage range, and thus, the magnitude of the screening effect caused by the th active layer is also substantially constant, thus, the energy of the screened gate field passing through the th active layer increases when a third gate voltage range higher than the second gate voltage range is applied because the amount of screening that blocks the gate field from the th active layer directly to the second active layer is limited due to current saturation of the th active layer.

As described above, a multilevel element according to embodiments of the present invention can provide a multilevel conduction characteristic in which it has a quantized conduction state above the mobility edge.

Further, as described above, due to the layer characteristics of the active layer, a unique phenomenon, i.e., a quantized on-state, may be exhibited. In other words, a specific energy state among the local energy states (AM _ R) of the amorphous region of the active layer may be resonance energy-matched with a specific energy state among the local energy states (NC _ R) of the crystalline region. Due to the hybridization caused by the resonance energy matching, a quantized on-state can be provided.

However, the fact that can exhibit quantized on-states through resonance energy matching is only examples, and it goes without saying that quantized on-states can be exhibited by other methods.

The multi-stage mechanism according to embodiments of the present invention has been described above with reference to fig. 6 to 10, a th variant embodiment of the present invention will be explained below with reference to fig. 11 and 12.

Fig. 11 and 12 show an th modified embodiment of the present invention in the description of the th modified embodiment, a description of contents overlapping with those described above will be omitted.

Referring to fig. 11, the multilevel element according to the th modified embodiment of the present invention may further include a third barrier layer 172 on the second active layer 170 in which case the source and drain electrodes 180 and 185 may contact the third barrier layer 172, in other words, the source and drain electrodes 180 and 185 may not contact the th barrier layer 140, the th active layer 150, the second barrier layer 160, and the second active layer 170, according to the above-described embodiment, the source and drain electrodes 180 and 185 contact the second active layer 170, but in the modified embodiment, the source and drain electrodes 180 and 185 may contact the third barrier layer 172.

As shown in fig. 12, in the th modified embodiment, the source electrode 180 and the drain electrode 185 are in contact with the third barrier layer 172, and thus the th to fourth gate voltage ranges (R1 to R4) can be provided, in other words, the second active layer 170 can also provide a quantum well having a quantized on-state through the second barrier layer 160 and the third barrier layer 172, and thus, even when the gate voltage within the fourth gate voltage range (R4) is increased, the current flowing between the source electrode 180 and the drain electrode 185 can be maintained at a constant level.

An th modified embodiment of the present invention has been described above with reference to fig. 11 to 12, and a second modified embodiment of the present invention will be described below with reference to fig. 13 and 14.

Fig. 13 and 14 show a second modified embodiment of the present invention, in the description of the second modified embodiment, a description of contents overlapping with those of the th modified embodiment will be omitted.

Referring to fig. 13, a third active layer 174 may be further provided on the third barrier layer 172, and in addition, the source electrode 180 and the drain electrode 185 may contact the third active layer 174, in other words, the source electrode 180 and the drain electrode 185 may not contact the th barrier layer 140, the th active layer 150, the second barrier layer 160, the second active layer 170, and the third barrier layer 172, and thus, unlike the variant embodiment, in the second variant embodiment, the source electrode 180 and the drain electrode 185 may contact the third active layer 174.

As shown in fig. 14, in the second modified embodiment, the third active layer 174 is provided, and thus th to fifth gate voltage ranges (R1 to R5) may be provided, in other words, in the second and fourth gate voltage ranges (R2 and R4), current saturation by quantized on-state may occur, and in the fifth gate voltage range (R5), current may increase due to contact between the third active layer 174 and the source and drain electrodes 180 and 185.

Embodiments and modified embodiments of the present invention have been described above, and a method of manufacturing a multilevel element according to embodiments of the present invention will be described below with reference to fig. 15 to 18.

Fig. 15 is a flowchart showing a method of manufacturing a multilevel element according to embodiments of the present invention, and fig. 16 to 18 show step S210 according to embodiments of the present invention in detail.

Referring to fig. 15, the multilevel element manufacturing method according to embodiments of the present invention may include at least of the step of forming a th barrier layer (S110), the step of forming a th active layer (S120), the step of forming a second barrier layer (S130), and the step of forming a second active layer (S140).

Step S110

Step S110 is a preparation step, and may include the steps of: preparing a substrate; forming a gate electrode on the substrate; and forming a gate insulating layer on the gate electrode.

For example, when Al4MP is deposited by the molecular layer deposition method, the molecular layer deposition method may include a TMA (trimethyl aluminum) precursor injection (discharging) step, a purging (pumping) step, a 4MP precursor injection step, and a purging step.

As a result, the th barrier layer 140 may be deposited.

Step S120

In step S120, an th active layer 150 may be deposited step S120 will be described in detail with reference to fig. 16.

Fig. 16 is a flowchart illustrating step S120 in detail according to embodiments of the invention.

Referring to fig. 16, the method of forming the active layer according to embodiments of the present invention may include at least of a source gas injection/pressurization step (S210), a th main purge step (S220), a reaction gas injection step (S230), and a second main purge step (S240), each of which will be described in detail below.

Step S210

For the source gas quantitative injection/pressurization step (S210), a source gas may be prepared. The kind of source gas to be prepared may vary depending on the type of layer to be deposited. For example, when the layer to be deposited is a metal oxide layer, a metal precursor source gas corresponding thereto may be prepared. For example, when the layer to be deposited is a zinc oxide (ZnO) layer, the source gas may include DEZ (diethyl zinc).

The source gas may be injected into the chamber in a state where the chamber outlet is closed. Thus, as the source gas is introduced into the chamber, the pressure within the chamber may increase. In other words, the pressure in the chamber is increased by the injection of the source gas, and thus, the source gas may be adsorbed onto the substrate in the pressurized atmosphere. Further, the increased pressure within the chamber may be maintained for a predetermined time. Therefore, the efficiency of adsorption onto the substrate can be improved.

At this time, the increased pressure in step S210 may be higher than 0.03Torr, preferably 0.1Torr or more, more preferably 0.3Torr or more. Further, step S210 may be performed at a temperature of 80 ℃ to 250 ℃.

Step S220

In the th main purge step (S220), an inert gas may be used, which may be, for example, argon (Ar) or nitrogen (N2).

Step S230

In the reaction gas injection step (S230), the reaction gas may react with the source gas to form a layer to be deposited. For example, when the source gas comprises DEZ, the reactant gas may comprise H₂O。

Step S240

After the reaction gas injection step, a second main purge step (S240) may be further performed .

The steps S210 to S240 according to embodiments of the present invention have been described above, and the injection/pressurization of the step S210 will be described in detail below.

Injecting/pressurizing of step S210

The source gas injection/pressurization step (step S210) may be performed in a pressurized atmosphere. In other words, the source gas injection/pressurization step may be performed in a high-pressure atmosphere, and may be simply referred to as "pressurization step".

Although the source gas injection/pressurization step (step S210) will be described in detail for the sake of brevity, it should be understood that the injection/pressurization may be performed in the reaction gas injection step (step S230).

According to examples, the injection/pressurization step may be performed in a state where the chamber loaded with the substrate is closed, for example, the exhaust valve of the chamber is closed, and in this state, the metal precursor source gas may be injected into the chamber (sub-injection/pressurization step), thereby introducing a high pressure into the chamber, and the introduced high pressure may be maintained (sub-exposure step). after maintaining the high pressure for periods of time, the metal precursor source gas may be adsorbed to the surface of the substrate in a high pressure atmosphere.

In other words, the injection/pressurization step may include at least of the sub-injection/pressurization step, the sub-exposure step, and the sub-purge step.

As shown in fig. 17, the pressure in the sub-exposure step can be maintained at a constant level even when the number of sub-exposure steps is increased. In contrast, as shown in fig. 18, the pressure in the sub-exposure step may be increased as the number of sub-exposure steps increases. For reference, the Y-axis in fig. 17 represents pressure and the X-axis represents process steps.

According to embodiments, step S210 can be performed at a temperature of 80 ℃ to 250 ℃.

In addition, the substeps of step S210 may be performed at the same temperature. In particular, these substeps may be carried out at low temperatures. As used herein, the term "low temperature" means 250 ℃ or less, preferably 80 ℃ to 250 ℃.

The th active layer 150 may be deposited through the above steps S210 to S240, at which time, the thickness of the deposited layer may be controlled according to the number of repetitions of the steps S210 to S240, for example, when the layer to be deposited is a zinc oxide layer, the steps S210 to S240 may be repeated such that the thickness of the layer exceeds 1.5nm, and furthermore, when the layer to be deposited is a zinc oxide layer, the steps S210 to S240 may be repeated such that the thickness of the layer is 20nm or less.

The active layer formed according to steps S210 to S240 may exhibit DOS simulation results as shown in fig. 7 and 8 a. In other words, the active layer may exhibit a quantized on-state. More specifically, it may exhibit a quantized on-state at energies above the mobility edge. As described above, the results of this DOS simulation can be calculated on the formed active layer by PBE (per-Burke-Ernzerhof) exchange correlation functional and PAW (projection affix plus plane wave) pseudomorphism using VASP (vienna de novo calculation simulation) program.

Step S130

Referring again to fig. 15, the second barrier layer 160 may be deposited on the th active layer 150 step S130 corresponds to step S110 described above, and thus a detailed description thereof will be omitted.

Step S140

On the second barrier layer 160, a second active layer 170 may be deposited. Here, step S140 corresponds to step S120 described above, and thus a detailed description thereof will be omitted.

On the second active layer 170, a source electrode 180 and a drain electrode 185 may be deposited, and as a result, embodiments of multilevel elements according to the present invention may be fabricated.

Meanwhile, needless to say, the modified embodiment of the present invention described above with reference to fig. 11 and 13 may also be performed according to the number of depositions of the active layer and the number of depositions of the barrier layer.

In addition, step S140 may be omitted, and the source electrode 180 and the drain electrode 185 may be formed on the second barrier layer 160 formed in step S130 such that they are in contact with the second barrier layer 160.

The multistage element manufacturing method according to the embodiment and the modified embodiment of the present invention has been described above with reference to fig. 15 to 18. Experimental examples of the embodiments and the modified embodiments of the present invention will be described below with reference to fig. 19 to 24.

Fig. 19 shows process conditions of the multi-level element used in experimental examples of the present invention, in particular, fig. 19 shows process conditions of forming an active layer according to embodiments of the present invention, fig. 20 shows TEM images of the active layer obtained in experimental examples of the present invention, and fig. 21 shows I-V characteristics of the multi-level element manufactured according to embodiments of the present invention.

Experimental examples

To manufacture the multilevel elements according to experimental examples, a silicon wafer with a thickness of 300nm was prepared, on which an aluminium gate electrode with a thickness of 70nm was deposited₂O₃). The alumina is deposited by an atomic layer deposition process. For depositing alumina, TMA precursor source gas injection step, purge step, H are performed in sequence₂An O injection step and a purge step. The thickness of the alumina varies according to the number of active layers to be deposited. The thickness of the alumina increases as the number of active layers increases.

To this end, TMA source gas was injected at a temperature of 20 ℃ for 2 seconds, argon purge gas was injected for 20 seconds, 4MP as a reaction gas was injected at a temperature of 75 ℃ for 20 seconds, and argon purge gas was injected for 200 seconds, as a result of which th barrier layer having a thickness of about 9nm was deposited.

Next, according to step S120 (steps S210 to S240), a th active layer is deposited on the th barrier layer, to this end, as shown in fig. 19, DEZ is injected by performing sub-injection/pressurization four times in step S210, specifically, DEZ is injected into a chamber whose chamber outlet is closed in the th sub-injection/pressurization step, so that the pressure in the chamber is increased to 1.0Torr next, the chamber inlet is also closed, in which state DEZ is adsorbed onto the substrate by exposing the substrate to DEZ for 3 seconds at a pressure of 1.0Torr (sub-exposure step), next, sub-purging is performed for 15 seconds next, in the second sub-injection/pressurization step, DEZ is injected into a chamber whose chamber outlet is closed, so that the pressure in the chamber is increased to 1.0Torr next, the chamber inlet is also closed, in which state DEZ is adsorbed onto the substrate for 3 seconds by exposing the substrate to a pressure of 1.0Torr to repeat the sub-injection/pressurization step and the sub-injection step for four times.

Next, according to step S220, th main purge step is performed for 15 seconds.

In step S230, H is implanted by performing four sub-implantations/pressurizations and sub-exposure₂And O. In this step, the exposure time is longer than the DEZ injection time because of the reactive gas H₂O is more easily accumulated (aggregated) than the source gas DEZ.

Next, according to step S240, purging is performed for 25 seconds.

The process temperature in steps S210 to S240 is about 110 ℃.

Steps S210 to S240 are repeated to deposit a zinc oxide active layer having a thickness of about 2.5 nm.

Next, according to steps S130 and S140, a second barrier layer and a second active layer are deposited. The process condition of step S130 corresponds to the process condition of step S110, and the process condition of step S140 corresponds to the process condition of step S120, and thus a detailed description thereof will be omitted.

Next, the source aluminum electrode and the drain aluminum electrode were formed to a thickness of 70 nm.

As a result, experimental examples of the multi-stage element according to the present invention were manufactured.

The active layer of the multilevel element manufactured according to this experimental example was imaged by TEM. The TEM image is shown in fig. 20, where as can be seen, the active layer includes a plurality of crystalline regions and an amorphous region surrounding the plurality of crystalline regions. It was confirmed that each of the crystalline regions had a nano size, particularly a size of about 3 nm. Further, it is shown that the distance between adjacent crystalline regions is about 2.5 nm. Furthermore, it is shown that the crystalline regions are randomly distributed in a two-dimensional plane (see fig. 2).

In this experimental example, the active layer was formed at a low temperature of about 110 ℃. That is, since the active layer including the crystalline region and the amorphous region may be formed at a low temperature, the manufacturing method of the experimental example may not be limited by the process temperature.

As a result of measuring the I-V curve of the multi-stage device manufactured according to the experimental example, it was confirmed that the multi-stage device manufactured according to the experimental example had the th to third gate voltage ranges (R1 to R3) described above with reference to fig. 4.

It is confirmed that the th gate voltage range is 0.28V to 1V, that is, the th active layer is activated at 0.28V it is found that the current magnitude is constant (about 3.9nA) when the second gate voltage range is 1V to 2V, that is, the voltage is between 1V and 2V it is believed that this is due to the resonance energy matching between the energy state of the amorphous region and the energy state of the crystalline region as described above, that is, even though the magnitude of the voltage is changed, the magnitude of the current appears constant due to the quantized on-state, it is confirmed that the third gate voltage range is 2V or more, that is, it is confirmed that the gate field passing through the th active layer activates even the second active layer at a voltage of 2V or more, in this case, it is desirable that the magnitude of the saturation current in the second gate voltage range can be controlled according to the thickness of the th active layer.

Furthermore, the multilevel element manufactured according to the experimental example was theoretically modeled. Next, the I-V curves of the multilevel elements manufactured according to the experimental examples were compared with the I-V curves of the modeled elements. As a result, as shown in fig. 21b, it was confirmed that the values of the experimental example and the values of the modeling element were well matched.

Fig. 22 and 23 show the I-V characteristics of a multi-stage element manufactured according to a modified embodiment of the present invention.

Fig. 22 shows the I-V characteristics of a multilevel element according to a modified embodiment of of the present invention in a modified embodiment of , a third barrier layer is additionally deposited on the second barrier layer, such that the third barrier layer is additionally deposited under the process conditions described above with respect to step S110.

As shown in fig. 22, it was confirmed that the multi-stage element according to the th modified embodiment had the th to fourth gate voltage ranges (R1 to R4) as described above with reference to fig. 12.

It is confirmed that th gate voltage ranges from 0.28V to 3V, that is, the th active layer is activated at 0.28V, it is confirmed that the second gate voltage ranges from 3V to 8V, that is, a voltage between 3V and 8V, the magnitude of current is constant (about 0.021 μ a), it is believed that this is caused due to the resonance energy matching between the energy state of the amorphous region and the energy state of the crystalline region as described above, that is, even if the magnitude of voltage varies, the magnitude of current appears constant due to the quantized on-state, it is confirmed that the third gate voltage ranges from 8V to 15V, that is, it is confirmed that the gate electric field passing through the th active layer activates even the second active layer at a voltage of 8V or higher, furthermore, it is confirmed that the fourth gate voltage ranges from 15V or higher, it is found that the magnitude of current in the fourth gate voltage ranges is about 0.134 μ a.

Fig. 23 shows the I-V characteristics of a multistage element according to a second modified embodiment of the present invention. In a second variant embodiment, an active barrier layer is additionally deposited, so that a third active layer is additionally deposited under the process conditions as described above with respect to step S120. Specifically, the third active layer was additionally deposited under the process conditions as described in the above experimental example. The thickness of the third active layer is about 2.5 nm.

As shown in fig. 23, it was confirmed that the multi-stage element according to the second modified embodiment had the th gate voltage range (R1), the second gate voltage range (R2), the third gate voltage range (R3), the fourth gate voltage range (R4), and the fifth gate voltage range (R5) as described above with reference to fig. 14.

It is confirmed that th gate voltage ranges from 0.28V to 3V, that is, the th active layer is activated at 0.28V, it is confirmed that the second gate voltage ranges from 3V to 8V, that is, a voltage between 3V and 8V, the magnitude of current is constant (about 0.021 μ a), it is believed that this is due to the resonance energy matching between the energy state of the amorphous region and the energy state of the crystalline region as described above, that is, even if the magnitude of voltage varies, the magnitude of current appears constant due to the quantized on-state, it is confirmed that the third gate voltage ranges from 8V to 15V, that is, it is confirmed that the gate field passing through the th active layer activates even the second active layer at a voltage of 8V or higher, furthermore, it is confirmed that the fourth gate voltage ranges from 15V to 25V.

Looking at the I-V curves of the modified embodiments, it can be seen that in the multilevel element manufacturing method according to embodiments of the present invention, the number of multilevel states can be easily controlled to 3, 4.

Further, when comparing the th modified embodiment with the second modified embodiment, it is confirmed that the magnitude of current in the final gate voltage range is constant or increased depending on whether the source electrode and the drain electrode are brought into contact with the barrier layer or whether these electrodes are brought into contact with the active layer.

Fig. 24 shows the results of measuring the FET characteristics depending on the thickness of the active layer according to embodiments of the present invention, in particular, fig. 24 shows the results of measuring the FET characteristics depending on the thickness of the active layer deposited under the process conditions described above with reference to fig. 24.

In order to measure the FET characteristics, transistors each including a substrate, a gate electrode, a gate insulating layer, an active layer including zinc oxide, and source and drain electrodes were manufactured.

Specifically, transistors having zinc oxide active layer thicknesses of 1.5nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm, respectively, were fabricated while increasing the number of repetitions of the active layer deposition step described above with reference to fig. 19.

Referring to fig. 24, it can be seen that when the thickness of the metal oxide layer is 1.5nm, a Field Effect Transistor (FET) characteristic does not occur. Therefore, in view of FET characteristics, it is preferable that the thickness of the metal oxide layer is greater than 1.5 nm. When the thickness of the metal oxide layer is greater than 1.5nm, it can be seen that stable FET characteristics occur. That is, when the thickness of the metal oxide layer is greater than 1.5nm, it can be seen that on/off ratio characteristics, mobility characteristics, threshold voltage, and SS value occur.

Thus, when the active layer includes a metal oxide, such as zinc oxide, the thickness of the active layer may preferably be greater than 1.5nm to this end, steps S210 to S240 may be repeated a predetermined number of times.

Fig. 25 shows the results of testing the reliability of the multilevel elements fabricated according to embodiments of the present invention.

Referring to fig. 25, it can be seen that the I-V curve of the multilevel elements fabricated according to examples of the present invention was maintained even after 180 days, in particular, it can be seen that the I-V characteristics were well maintained in the second gate voltage range, i.e., the current saturation range, indicating that the superlattice structure composed of the active layer and the barrier layer provides excellent stability.

Although the present invention has been described in detail above with reference to the exemplary embodiments thereof, the scope of the present invention is not limited to these embodiments, and should be construed based on the appended claims. Further, it will be understood by those of ordinary skill in the art that various modifications and changes may be made without departing from the scope of the present invention.