阅读说明：本技术 具有表面安装裸片支撑结构的半导体装置组合件 (Semiconductor device assembly with surface mount die support structure ) 是由 B·P·沃兹 B·L·麦克莱恩 于 2018-04-25 设计创作，主要内容包括：本发明提供一种半导体装置组合件。所述组合件包含第一封装元件及安置于所述第一封装元件上方的第二封装元件。所述组合件进一步包含所述第一及第二封装元件之间的多个裸片支撑结构,其中所述多个裸片支撑结构中的每一者具有第一高度、表面安装到所述第一封装元件的下部分及与所述第二封装元件接触的上部分。所述组合件进一步包含所述第一及第二封装元件之间的多个互连件,其中所述多个互连件中的每一者包含具有第二高度的导电柱、导电垫及在所述导电柱与所述导电垫之间具有焊料接头厚度的接合材料。所述第一高度约等于所述焊料接头厚度及所述第二高度的总和。(The invention provides a semiconductor device assembly. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface mounted to the first package element, and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bonding material having a solder joint thickness between the conductive pillar and the conductive pad. The first height is approximately equal to a sum of the solder joint thickness and the second height.)

1. A semiconductor device assembly, comprising:

a first package element;

a second package element disposed over the first package element;

a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface mounted to the first package element, and an upper portion in contact with the second package element; and

a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bonding material having a solder joint thickness between the conductive pillar and the conductive pad,

wherein the first height is approximately equal to a sum of the solder joint thickness and the second height.

2. The semiconductor device assembly of claim 1, wherein the plurality of die support structures includes a die support structure disposed about a perimeter of the semiconductor device assembly.

3. The semiconductor device assembly of claim 1, wherein the plurality of die support structures includes a die support structure disposed about a middle region of the semiconductor device assembly.

4. The semiconductor device assembly of claim 1, wherein each of the plurality of die support structures is surface mounted to one or more mounting pads on the first package element.

5. The semiconductor device assembly of claim 1, wherein at least one of the plurality of die support structures includes discrete circuit elements electrically connected to other circuit elements in the first package element.

6. The semiconductor device assembly of claim 1, wherein each of the plurality of die support structures is electrically isolated from other circuit elements of the semiconductor device assembly.

7. The semiconductor device assembly of claim 1, wherein the first die comprises a logic die, and wherein the second die comprises a memory die.

8. The semiconductor device assembly of claim 1, wherein the first die comprises a support substrate, and wherein the second die comprises a logic die.

9. A semiconductor device assembly, comprising:

a first package element;

a second package element disposed over the first package element;

a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface mounted to the first package element, and an upper portion in contact with the second package element; and

a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects comprises a first conductive element on the first package element, a second conductive element on the second package element, and a bonding material having a solder joint thickness between the first and second conductive elements,

wherein the first height is approximately equal to the solder joint thickness.

10. The semiconductor device assembly of claim 9, wherein the plurality of die support structures includes a die support structure disposed about a perimeter of the semiconductor device assembly.

11. The semiconductor device assembly of claim 9, wherein the plurality of die support structures includes a die support structure disposed about a middle region of the semiconductor device assembly.

12. The semiconductor device assembly of claim 9, wherein each of the plurality of die support structures is surface mounted to one or more mounting pads on the first package element.

13. The semiconductor device assembly of claim 9, wherein at least one of the plurality of die support structures includes discrete circuit elements electrically connected to other circuit elements in the first package element.

14. The semiconductor device assembly of claim 9, wherein each of the plurality of die support structures is electrically isolated from other circuit elements of the semiconductor device assembly.

15. The semiconductor device assembly of claim 9, wherein the first die comprises a logic die, and wherein the second die comprises a memory die.

16. The semiconductor device assembly of claim 9, wherein the first die comprises a support substrate, and wherein the second die comprises a logic die.

17. A method of fabricating a semiconductor device assembly, comprising the steps of:

disposing a second package element over a first package element, the first package element including a plurality of surface mount die support structures and a plurality of conductive pads, the second package element including a plurality of conductive elements, wherein each of the plurality of conductive elements is separated from a corresponding one of the plurality of conductive pads by a bonding material;

reflowing the bonding material; and

moving at least one of the first package element and the second package element toward each other such that each of the plurality of die support elements contacts the second package element.

18. The method of claim 17, further comprising the step of:

measuring the movement of the first and second package elements toward each other to determine when the plurality of die support elements have contacted the second package element.

19. The method of claim 17, further comprising the step of:

curing the bonding material after the die support element contacts the second package element.

20. The method of claim 17, wherein the plurality of conductive elements includes conductive posts extending from the second package element.

Technical Field

The disclosed embodiments relate to semiconductor device assemblies having surface mount die support structures. In several embodiments, the present techniques relate to surface mount die support structures configured to mechanically support interconnects positioned between stacked package elements.

Background

Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and enclosed in a plastic protective cover or a metal heat sink. The chip includes functional components, such as memory cells, processor circuits, and imager devices, and bond pads electrically connected to the functional components. The bond pads may be electrically connected to terminals external to the protective cover to allow the die to be connected to higher-order circuitry. Within some packages, semiconductor dies can be stacked on top of each other and electrically connected to each other by individual interconnects placed between adjacent dies. In these packages, each interconnect may include a conductive material (e.g., solder) and a pair of contacts on opposing surfaces of adjacent dies. For example, a metal solder may be placed between the contacts and reflowed to form a conductive joint.

One challenge with conventional solder joints is that they can be prone to breaking during assembly of the die. For example, the solder joints may be damaged if excessive force is applied during bonding of adjacent dies. This can result in a high electrical resistance of the open or crossover joint, or alternatively can result in an increase in joint diameter until it mechanically contacts one or more adjacent solder joints, creating an electrical short. Thus, there is a need for a more mechanically robust semiconductor device assembly.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor device assembly having interconnects and a die support structure in accordance with embodiments of the present technique.

Figures 2A-2C are enlarged cross-sectional views of a semiconductor device assembly showing interconnects and surface mount die support structures configured in accordance with embodiments of the present technique.

Figures 3A and 3B are cross-sectional views illustrating a semiconductor device assembly at various stages in a method of manufacturing, in accordance with selected embodiments of the present technique.

Fig. 4A and 4B are cross-sectional views illustrating a semiconductor device assembly at various stages in a method of manufacturing, in accordance with selected embodiments of the present technique.

Figure 5 is a flow chart illustrating a method of manufacturing a semiconductor device assembly, in accordance with one embodiment of the present technique.

Figure 6 is a schematic diagram of a system including a semiconductor device assembly configured in accordance with embodiments of the present technique.

Detailed Description

In the following description, numerous specific details are discussed to provide a thorough and thorough description of embodiments of the present technology. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with semiconductor devices are not shown or described in detail to avoid obscuring aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.

As discussed above, semiconductor devices continue to be designed with an increasing demand for increased mechanical robustness. Accordingly, several embodiments of semiconductor device assemblies in accordance with the present techniques may include die support structures that may provide increased mechanical robustness to stacked semiconductor dies of the assembly.

Several embodiments of the present technology relate to semiconductor device assemblies, semiconductor packages, systems including semiconductor devices, and methods of manufacturing and operating semiconductor devices. In one embodiment, a semiconductor device assembly includes a first package element and a second package element disposed above the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface mounted to the first package element, and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bonding material having a solder joint thickness between the conductive pillar and the conductive pad. The first height may be approximately equal to a sum of the solder joint thickness and the second height. The interconnect can optionally omit the conductive post such that the first height can be about equal to the solder joint thickness.

Embodiments of a semiconductor device assembly having a surface mount die support structure are described below. In various embodiments, a surface mount die support structure may be configured to mechanically support interconnects positioned between stacked dies in a semiconductor device assembly or between a die and a substrate or interposer of an overlying stacked die. The die support structure may also be optionally configured to provide electrical interconnections between adjacent package elements (e.g., between adjacent dies or between a die and an adjacent substrate or interposer), or thermal paths for conducting heat through the stacked dies. The term "semiconductor device assembly" may refer to an assembly of one or more semiconductor devices, semiconductor device packages, and/or substrates (e.g., an interposer, support, or other suitable substrate). The semiconductor device assemblies may be fabricated, for example, in discrete packages, in strip or matrix form, and/or in wafer panel form. The term "semiconductor device" generally refers to a solid state device comprising a semiconductor material. A semiconductor device may include, for example, a semiconductor substrate, a wafer, a panel, or a die singulated from a wafer or substrate. Throughout this disclosure, a semiconductor device is generally described in the context of a semiconductor die; however, the semiconductor device is not limited to a semiconductor die.

The term "semiconductor device package" may refer to an arrangement having one or more semiconductor devices incorporated into a common package. A semiconductor package may include a housing or casing that partially or fully encapsulates at least one semiconductor device. The semiconductor device package may also include an interposer substrate carrying one or more semiconductor devices and attached to or otherwise incorporated into the housing.

As used herein, the terms "vertical," "lateral," "up," and "down" may refer to the relative directions or positions of the components in the oriented semiconductor device assembly views shown in the figures. For example, "upper" or "uppermost" may refer to a member that is positioned closer to the top of the page than another member. However, these terms should be broadly construed to include semiconductor devices and semiconductor device assemblies having other orientations, such as upside down or tilted orientations where top/bottom, above/below, up/below and left/right may be interchanged depending on the orientation.

Fig. 1 is a cross-sectional view of a semiconductor device assembly 100 ("assembly 100") having first and second die support structures 102a and 102b (collectively, "die support structures 102"), configured in accordance with embodiments of the present technique. The assembly 100 includes a first package element 104a (e.g., a substrate, interposer, or semiconductor die), a second package element 104b (e.g., a substrate, interposer, or semiconductor die) (collectively, "package elements 104"), and an array of individual interconnects 106 extending vertically between first and second sides 108a and 108b of the package element 104a and 104b, respectively. The interconnects 106 may each include, for example, a first conductive member (e.g., conductive pad 110) on the first side 108a of the first package element 104a, a second conductive member (e.g., conductive post 112) on the second side 108b of the second package element 104b, and a bonding material 114 that bonds the conductive post 112 to the conductive pad 110.

The die support structures 102 are positioned in peripheral regions 116 of the package elements 104 on opposite sides of the array of interconnects 106. The die support structures 102 may each include a structural element 120 having a lower portion surface mounted to the first side 108a of the first package element 104a and an upper portion in contact with the second side 108b of the second package element 104 b. The structural element 120 may be a discrete circuit element (e.g., a capacitor, a resistor, an inductor, a transistor, or the like) surface mounted to one or more mounting pads 118 on the first package element 104a to provide electrical connection to other circuit elements in the first package element 104 a. In another embodiment, the structural element 120 may be a bulk material or a dummy structure that is electrically isolated from other circuit elements of the package element 104. In various embodiments described in more detail below, the die support structure 102 is configured to mechanically support the package element 104 and prevent or at least inhibit warpage of the package element 104, such as during device fabrication.

Indeed, the assembly 100 may include a greater number of interconnects 106 and/or die support structures 102 than shown in the illustrated embodiment. For example, the assembly 100 may include tens, hundreds, thousands, or more interconnects 106 arranged between package elements 104. Additionally, in various embodiments, the die support structures 102 can be positioned interstitially between individual interconnects 106 and/or groups of interconnects 106 (e.g., between groups of 5, 20, 100, or more interconnects within an array). For example, in some embodiments, the die support structures 102c (shown in hidden lines) may be positioned between the intermediate regions 124 near the center of the package element 104. In other embodiments, the die support structure 102 may be positioned at various other locations between the package elements 104.

As further shown in fig. 1, each of the package elements 104 includes a semiconductor substrate 126 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) and a conductive element (e.g., a through silicon via, a through mold via, or other conductive member connecting the front and back sides of the package substrate or interposer) 128 extending from the first side 108a of the package element 104 through the substrate 126 to the second side 108 b. The conductive elements 128 are coupled to corresponding interconnects 106. In some embodiments, the conductive elements 128 may be coupled to substrate pads 130 or other conductive members positioned on either side of the semiconductor substrate 126.

Each substrate 126 may include an integrated circuit 132 (shown schematically) coupled to one or more of substrate pads 130 and/or conductive elements 128. The integrated circuit 132 may include, for example, memory circuits (e.g., Dynamic Random Access Memory (DRAM)), controller circuits (e.g., DRAM controller), logic circuits, and/or other circuits. In some embodiments, the assembly 100 may include other structures and means, such as an underfill material (not shown) deposited or otherwise formed around and/or between the package elements 104. In the embodiment illustrated in fig. 1, the assembly 100 includes two package elements 104. In practice, however, the assembly 100 may include a different number of package elements (e.g., two dies over a substrate, three dies over an interposer, four dies, eight dies, sixteen dies, or more). For example, in another embodiment, the assembly 100 may include a third package element 104c (e.g., a semiconductor die shown in hidden lines) on the second package element 104 b. In some embodiments, the assembly 100 may include a housing (not shown) (e.g., a thermally conductive housing) that encloses the packaging element 104 within an envelope. In these and other embodiments, the assembly 100 may include a support substrate (e.g., the package element 104a) (e.g., an interposer and/or a printed circuit board) configured to operably couple the other package elements 104b and 104c to external circuitry (not shown). The semiconductor die may be similarly spaced apart from such a support substrate or interposer and supported by a die support structure 102 surface mounted on the support substrate or interposer in a manner similar to that illustrated in fig. 1.

Figure 2A is an enlarged cross-sectional view showing a number of interconnects 106 and die support structures 102A configured in accordance with embodiments of the present technique. Referring to fig. 2A, the die support structure 102A includes a structural element 120 having a lower portion 120a surface mounted to the first side 108a of the first package element 104a and an upper portion 120b in contact with the second side 108b of the second package element 104 b. The structural element 120 may be surface mounted to one or more mounting pads 118 on the first package element 104a using a bonding material 122 (e.g., solder). The conductive pads 110 of the interconnects 106 may be coupled to the first redistribution structure 265a formed on the first side 108a of the first package element 104a or form a portion of the first redistribution structure 265a formed on the first side 108a of the first package element 104 a. The conductive pillars 112 may be coupled to the second redistribution structure 265b formed on the second side of the second package element 104b or form a portion of the second redistribution structure 265b formed on the second side of the second package element 104 b. Each of the redistribution structures 265 may include various conductive members 233 and a passivation material 236 (e.g., an oxide material) configured to provide electrical isolation between the conductive members 233. The conductive members 233 can include, for example, individual metal traces and/or pads coupled to one or more of the interconnects 106, substrate pads 130 (fig. 1), conductive elements 128, and the like.

Fig. 2B is a further enlarged cross-sectional view showing one of the interconnects 106 in even more detail, in accordance with an aspect of the present technique. The conductive pillars 112 of the interconnect 106 include ends that are attached to the conductive pads 110 by a bonding material 114. The interconnect 106 may also include a first potential epitaxial material 255 (e.g., nickel-based intermetallic and/or gold) formed over the end of the conductive pillar 112, and a second potential epitaxial material 253 (e.g., nickel-based intermetallic and/or gold) formed over the conductive pad 110. The epitaxial material may facilitate bonding and/or prevent or at least inhibit electromigration of the copper or other metal used to form the conductive pillars 112 and conductive pads 110. The bonding material 114 bridges the gap g between the conductive post 112 and the conductive pad 110₁(also known to those skilled in the art as solder joint thickness). Solder joint thickness g₁A first protrusion height d from the second side 108b of the second package element 104b at least in part by the conductive pillars 112₁And (4) specifying.

Figure 2C is a further enlarged cross-sectional view showing the die support structure 102A of figure 2A in even more detail. The structural element 120 has a second height d₂Extending above the mounting pad 118 by the second height d₂Approximately defining the spacing between the first and second package elements 104. In this regard, the second height d₂Approximately equal to the solder joint thickness g₁With individual interconnections 106First height d of conductive post 112₁The sum of (a) and (b).

In accordance with one aspect of the present technique, providing a device assembly 100 having a die support structure 102 configured to mechanically support a package element 104 simplifies and improves yield in manufacturing the device assembly 100. In this regard, one challenge in forming interconnects between package elements is that the package elements may have an inherent amount of warpage (e.g., die warpage) that may create tensile and/or compressive forces on the interconnects between the package elements. In the absence of a die support structure, these forces can damage the interconnects during assembly of the device, pull the interconnects apart (e.g., tensile forces) and cause an open circuit, or over compress the interconnects (e.g., compressive forces) and cause bonding material from adjacent interconnects to meet and create a short circuit. By providing the die support structures 102 around the peripheral region 116 of the package element (e.g., and optionally in the intermediate region 124), a thermal compression bonding operation may be used to force the package elements 104 into parallel planar alignment by compressing the package elements 104 together until the upper portions 120b of the structural elements 120 of each die support structure 102 contact the second side 108b of the second package element 104 b. Solder joint thickness g of interconnects 106 with die support structure 102 ensuring parallel planar alignment of package elements 104₁May be formed (e.g., by forming the first height d of the conductive pillars 112 of the interconnect 106₁Is selected to be greater than the second height d of the structural element 120 of the die support structure 102₂Small desired amount of solder joint thickness g₁) Accurately compressed to within the desired range. In each package element in the stack that is not only added to the uppermost package element of the stack, but that may otherwise be subject to warpage during unintended reflow of its solder connections, the compressive bonding operation may counteract any inherent warpage (e.g., die warpage) in the package element 104 by forcing the package elements into parallel planar alignment.

In accordance with another aspect of the present technique, the mechanical strength of the die support structure 102 may allow the thermal compression bonding operation to utilize force feedback as a control mechanism for operation, rather than z-dimensional offset, which may further simplify and improve the quality of the bonding operation. For exampleDuring the thermal compression bonding operation, upon reflowing the bonding material in the die support structure 102 and the interconnects 106, a force may be applied to the stack of two or more package elements such that the upper portions 120b of the structural elements 120 of the die support structure 102 are in contact with the second side 108b of the second package element 104b, and thus a measured increase in resistance to the force is determined. The measured increase in resistance to the applied compressive force may be used to determine the solder joint thickness g between the conductive pillar 112 and the conductive pad 110₁Thus having (e.g., due to height d of conductive pillars 112)₁Height d of structural element 120 from die support structure 102₂A predetermined difference therebetween) to a known range. As will be readily appreciated by those skilled in the art, measuring the resistance to compressive force in this bonding operation is a much simpler engineering challenge than maintaining z-dimensional movement across the bonding profile.

For example, fig. 3A and 3B are cross-sectional views illustrating a semiconductor device assembly 100 at various stages in a method of manufacturing, in accordance with selected embodiments of the present technique. In fig. 3A, the assembly 100 is illustrated at the beginning of a thermal compression bonding operation, wherein heating has caused the bonding material 114 in the interconnects 106 to reflow and electrically connect the first and second potential epitaxial materials 255 and 253 of the conductive pillars 112 and conductive pads 110, respectively. Prior to applying the compressive force, the upper portion 120b of the structural element 120 of the die support structure 102 is not in contact with the second side 108b of the second package element 104b and the gap g bridged by the bonding material 114 of the interconnect 106₁(e.g., solder joint thickness) is still greater than the desired final amount.

In fig. 3B, the assembly 100 is illustrated at the completion of a thermal compression bonding operation, where the compressive force and applied heat have caused the upper portion 120B of the structural element 120 of the die support structure 102 to contact the second side 108B of the second package element 104B such that the gap g bridged by the bonding material 114 of the interconnects 106₁(e.g., solder joint thickness) is within a desired range. After cooling, the bonding material 114 solidifies and secures the package elements 104a and 104b in the parallel-plane alignment (e.g., overcoming any inherent warpage) that the compression operation has forced.

Although it is said in FIGS. 1 to 3BIn the illustrated embodiment, the interconnects 106 are illustrated as including posts protruding from one of the package elements 104 (e.g., such that the solder joint thickness g₁ Structural element 120 height d, which may be characterized as approximately equal to the die support structure₂Height d of conductive column₁The difference between) but in other embodiments the interconnects between package elements can have any of a number of different structures, including structures that omit conductive pillars. For example, fig. 4A and 4B illustrate an embodiment in which the interconnects between a semiconductor die and a support substrate (e.g., or between two semiconductor dies) are formed from simple solder bumps on conductive pads (e.g., the posts of the previous embodiments are omitted). In this arrangement, the solder joint thickness of the interconnect may be approximately equal to the height of the die support structure.

Turning to fig. 4A, the semiconductor device assembly 400 is illustrated at the beginning of a thermal compression bonding operation in which heat has caused the solder bumps 413 and 414 in the interconnects 406 to reflow and electrically connect the upper and lower conductive pads 412 and 410, respectively. After the compressive force is applied, the upper portion 420b of the structural element 420 of the die support structure 402 is not in contact with the second side 408b of the upper semiconductor die 404b and the gap g bridged by the bonding materials 413 and 414 of the interconnect 406₂(e.g., solder joint thickness) is still greater than the desired final amount.

In fig. 4B, the assembly 400 is illustrated at the completion of the thermal compression bonding operation, where the compressive force has caused the upper portion 420B of the structural element 420 of the die support structure 402 to contact the second side 408B of the upper semiconductor die 404B such that the gap g bridged by the combined bonding material 415 of the interconnects 406₂(e.g., solder joint thickness) is within a desired range. After cooling, the bonding material 415 solidifies and fixes the upper and lower semiconductor dies 404b, 404a (e.g., or interposer or semiconductor die) in a parallel planar alignment (e.g., overcoming any inherent warpage) that the compression operation has forced. As can be seen with reference to fig. 4B, the height d of the structural elements 420 of the die support structure 402₃Approximately equal to the distance between the upper semiconductor die 404b and the lower support substrate 404a, which in this embodiment where the dies are interconnected by solder bump bonds is also approximately equal to solderMaterial joint thickness g₂。

In accordance with one aspect of the present technique, the inclusion of a die support structure on a wafer or panel allows wafer or panel level assembly of a stack of dies without experiencing a reduction in yield caused by die warpage defects in conventional wafer or panel level assembly operations. In this regard, the arrangement of die support structures on a wafer or panel may be selected to balance the need for warpage mitigation with the amount of area (real estate) dedicated to the die support structures. In one embodiment, loss of usable die area due to inclusion of the die support structure may be mitigated by utilizing an active die support structure in place of other circuit elements (e.g., by utilizing surface mount capacitors as die support elements that would otherwise consume surface area elsewhere in the semiconductor package, such as on a support substrate proximate the die stack) rather than using a dummy (e.g., electrically isolated or inactive) die support structure that does not provide an electrical function in the circuitry of the die. Those skilled in the art will readily appreciate that using discrete circuit elements as the die support structure will determine the number of mounting pads required to surface mount the die support structure (e.g., two mounting pads for a two-terminal element, three mounting pads for a three-terminal element, etc.).

In accordance with another aspect of the present technique, one benefit of using a die support structure 102 that is larger than the interconnects 106 (e.g., has a width that is larger than the interconnects 106) is that the die support structure 102 can provide improved mechanical support against compressive forces (e.g., the die support structure 102 is more mechanically robust and can better withstand compressive forces during thermal compression bonding operations).

Fig. 5 is a flow chart illustrating a method for fabricating a semiconductor device in accordance with one aspect of the present technique. The method includes providing a first package element (e.g., a support substrate, an interposer, or a semiconductor die) including a plurality of surface mount die supports and a plurality of conductive pads (block 510) and disposing a second package element (e.g., a support substrate, an interposer, or a semiconductor die) over the first package element (block 520). The second package element includes a plurality of conductive elements, each separated from a corresponding one of the plurality of conductive pads by a bonding material. The method further includes reflowing the bonding material (block 530) and applying a force to compress the first package element and the package element die together such that each of the die support structures contacts the second package element (block 540). When the force is applied, the method further includes measuring relative movement of the first and second package elements to determine when the die support structure has been brought into contact with the second package element (block 550).

Any of the die support structures and/or semiconductor device assemblies described above with reference to fig. 1-5 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is the system 690 shown schematically in fig. 6. The system 690 may include a semiconductor device assembly 600, a power supply 692, a driver 694, a processor 696, and/or other subsystems or components 698. The semiconductor device assembly 600 may include components substantially similar to those of the semiconductor device assembly described above, and may thus include a die support structure for mechanically supporting interconnects positioned between stacked semiconductor dies of the assembly. The resulting system 690 may perform any of a variety of functions, such as memory storage, data processing, and/or other suitable functions. Thus, representative systems 690 may include, without limitation, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, or other machines and appliances. The components of system 690 may be housed in a single unit or distributed (e.g., over a communication network) across multiple interconnected units. The components of system 690 may also include remote devices and any of a variety of computer-readable media.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the invention. Moreover, while advantages associated with particular embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the present technology. Accordingly, the disclosure and related techniques may encompass other embodiments not explicitly shown or described herein.