阅读说明：本技术 覆盖管理方法、覆盖管理系统及计算系统 (Coverage management method, coverage management system and computing system ) 是由 林资程 汪青蓉 左克伟 王咏生 彭旸尹 于 2019-06-27 设计创作，主要内容包括：本发明提供一种覆盖管理方法、覆盖管理系统及计算系统,阐述用于使用机器学习来管理半导体制造中的垂直对齐或覆盖的技术。通过所公开的技术来评估及管理扇出型晶片级封装工艺中内连特征的对齐。使用大数据及神经网络系统来使覆盖误差源因子与覆盖计量类别相关。所述覆盖误差源因子包括工具相关覆盖源因子、晶片或管芯相关覆盖源因子、以及处理上下文相关覆盖误差源因子。(Techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning are described. The disclosed techniques evaluate and manage the alignment of interconnect features in a fan-out wafer level packaging process. A big data and neural network system is used to correlate overlay error source factors to overlay metrology categories. The overlay error source factors include tool-dependent overlay source factors, wafer or die-dependent overlay source factors, and process context-dependent overlay error source factors.)

1. A method of coverage management, comprising:

determining a tool position relative to a wafer processing tool that forms a first feature on a first wafer;

determining an item location of a first portion of the first wafer corresponding to the first feature;

determining a coverage metric relative to the first feature;

generating a data set including the tool location, the project location, and the coverage metric; and

generating a function by machine learning based on the dataset, the function relating one or more of the tool positions or the item positions on a first side of the function to the coverage metric on a second side of the function.

2. The method of claim 1, wherein the tool position comprises one or more of a wafer stage position, a stepper position, a photomask key position, or an exposure position.

3. The method of claim 1, wherein the item position comprises one or more of a wafer offset or a wafer rotation of the first wafer positioned on a wafer stage.

4. The method of claim 1, further comprising:

determining a context in which to form the first feature on the first wafer; and

generating the data set including the context.

5. The method of claim 1, further comprising generating an estimated alignment metric for a second wafer based on the function.

6. The method of claim 5, further comprising evaluating the function by comparing the estimated alignment metric of the second wafer to a measured alignment metric of the second wafer.

7. The method of claim 5, further comprising generating alignment correction data relative to the second wafer based on the function, the alignment correction data specifying an adjustment to at least one of the tool position or the item position.

8. An overlay management system comprising:

a wafer processing tool configured to form features on a wafer;

a metrology tool configured to measure overlay alignment of the features on the wafer;

an overlay modeling tool configured to generate an estimated overlay alignment metric for the feature based on one or more of an alignment parameter of the wafer processing tool or an alignment parameter of the wafer; and

a process control tool configured to adjust one or more of the alignment parameters of the wafer processing tool or the alignment parameters of the wafer based on the estimated overlay alignment metrology.

9. The overlay management system of claim 8, wherein the overlay modeling tool generates a function that relates one or more of the alignment parameters of the wafer processing tool or the alignment parameters of the wafer to an overlay metrology of the feature.

10. A computing system, comprising:

a processor; and

a storage unit having stored thereon executable instructions that, when executed by the processor, configure the processor to perform acts comprising:

receiving data relative to a tool position of a wafer processing tool that forms a first feature on a first wafer;

receiving data of an item location relative to a location of the first wafer on a wafer-holding tool that formed the first feature on the first wafer;

receiving data relative to a context in which the first feature was formed on the first wafer; and

generating data for adjusting one or more of the tool location or the project location based on applying at least one of the data for the tool location, the data for the project location, and the data for the context into a regression model function that correlates at least one of the data for the tool location, the data for the project location, and the data for the context to an overlay metrology of the first feature on the first wafer.

Technical Field

Embodiments of the present invention relate to semiconductor technology, and more particularly, to an overlay management method, an overlay management system and a computing system.

Background

As semiconductor technology evolves, semiconductor dies are becoming smaller and smaller, while more and more functionality is being integrated into a single die. Accordingly, there is a need to include an increasing number of input/output (I/O) pads in integrated circuit ("IC") packages along with smaller area die surfaces. Fan-out wafer level packaging ("WLP") is a packaging technology that holds promise for such challenging scenarios. In fan-out WLP, the die are cut from the original front-end wafer, after which the die are positioned on a carrier wafer to be packaged with connection wiring and I/O pads. In a fan-out WLP process, it is an advantage that the I/O pads associated with the die can be rerouted to a larger area than the surface of the die itself. Thus, the number of I/O pads that are populated with a die may be increased.

Fan-out WLP packages may be used to fill one die, multiple dies side-by-side, or multiple dies in a package-on-package ("POP") vertical configuration. The POP configuration in fan-out WLP is achieved by vertically connecting the interconnect features (e.g., vias) of multiple dies.

Overlay metrology processes are used in various semiconductor manufacturing processes to monitor and control vertical alignment. Overlay metrology generally indicates how accurately the alignment of a first patterned layer or features thereon is with respect to a second patterned layer disposed at a different vertical level, e.g., vertical alignment, than the first patterned layer. Overlay error refers to a misalignment between a first portion on a first patterned layer and a second portion on a second patterned layer. An overlay error metric (e.g., a measurement) may be measured based on an offset between the first portion and the second portion or between an actual position of the first portion and a target position of the first portion. The target location may be determined during wafer processing based on advanced process control ("APC").

In fan-out WLP, the die that are tested as good are positioned onto a carrier wafer. Multi-layer interconnect features are formed that connect the die to associated I/O pads and within each layer of interconnect features itself. The interconnects are formed by a wafer level process in which photoresist and photolithography processes are used similarly to in the front-end wafer fabrication process. Therefore, it is desirable to manage vertical alignment between or among the interconnect elements in successive layers.

Disclosure of Invention

The embodiment of the invention provides a coverage management method, which comprises the following steps: determining a tool position relative to a wafer processing tool that forms a first feature on a first wafer; determining an item location of a first portion of the first wafer corresponding to the first feature; determining a coverage metric relative to the first feature; generating a data set including the tool location, the project location, and the coverage metric; and generating a function by machine learning based on the dataset, the function relating one or more of the tool position or the item position on a first side of the function to the coverage metric on a second side of the function.

An embodiment of the present invention provides a coverage management system, including: a wafer processing tool configured to form features on a wafer; a metrology tool configured to measure overlay alignment of the features on the wafer; an overlay modeling tool configured to generate an estimated overlay alignment metric for the feature based on one or more of an alignment parameter of the wafer processing tool or an alignment parameter of the wafer; and a process control tool configured to adjust one or more of the alignment parameters of the wafer processing tool or the alignment parameters of the wafer based on the estimated overlay alignment metrology.

An embodiment of the present invention provides a computing system, including: a processor; and a storage unit having stored thereon executable instructions that, when executed by the processor, configure the processor to perform acts comprising: receiving data relative to a tool position of a wafer processing tool that forms a first feature on a first wafer; receiving data of an item location relative to a location of the first wafer on a wafer-holding tool that formed the first feature on the first wafer; receiving data relative to a context in which the first feature was formed on the first wafer; and generating data for adjusting one or more of the tool location or the project location based on applying at least one of the data for the tool location, the data for the project location, and the data for the context into a regression model function that correlates at least one of the data for the tool location, the data for the project location, and the data for the context to an overlay metrology of the first feature on the first wafer.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. In the drawings, the same reference numbers identify similar elements or acts unless context dictates otherwise. The dimensions and relative positioning of elements in the figures are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is an exemplary system for managing overlay alignment;

fig. 2 is an exemplary error source data set;

FIG. 3 is an exemplary overlay error data set;

FIG. 4 is an exemplary neural network system;

FIG. 5 is an exemplary operation of a neural network system;

FIG. 6 is an exemplary process of overlay alignment management;

FIG. 7 is an exemplary carrier wafer with die positioned thereon in a fan-out wafer level packaging process;

FIG. 8 is an exemplary overlay metrology on the wafer shown in FIG. 7;

the reference numbers illustrate:

100: an overlay management system/system;

110: a wafer in-situ fabrication system;

112: wafer processing tool set/lithography tool set/toolset;

114: a process log;

116: a metrology tool set;

120: inputting a data set;

122: overlay error data;

124: error source data/overlay source data;

126: other data;

130: a big data unit;

140: a neural network unit/machine learning unit;

142: an alignment control unit;

144: a verification unit/verification module;

150: output data set/alignment control output data;

152: error prediction data;

154: corrective adjustment data;

210: a subset of tool alignment error source factors/tool alignment subset;

212: previous tool alignment data;

214: wafer stage position data/wafer stage position/tool alignment factor;

216: step position data/step position/tool alignment factor;

218: photomask key position data/photomask key positions/tool alignment factors;

220: exposure position data/exposure position/tool alignment factor;

250: a subset of wafer/die alignment error source factors/wafer/die alignment subset;

252: wafer offset data;

254: wafer rotation data;

256: die offset data;

258: die rotation data;

280: a subset of context error source factors/a subset of context error sources;

282: focal depth data;

284: exposure duration data;

286: step speed data;

288: irradiating the setting data;

290: illumination source/illumination source data;

292: enhance global alignment position/EGA position data;

294: field position data;

296: metering position data/metering position;

310: overlay metrology location data;

320: x-axis overlay error data;

330: y-axis overlay error data;

340: overlay rotation (angle) data;

410: a processing unit;

420: a storage unit;

430: a neural network application;

432: a training set generation module;

434: a machine learning module;

436: a verification module;

438: a prediction module;

440: a communication unit;

450: an interface unit;

460: other components;

500: an operating structure;

510: operating;

520: machine learning operations/machine learning processes;

530: performing a prediction operation;

600: an operation process;

610. 620, 630, 640, 650, 660, 670: operating;

700: carrier wafer/carrier wafer;

702: a target wafer position;

710. 710A: a die;

712. 712A: a target location;

720: a portion of a wafer;

722. 724: an alignment mark;

730: a wafer stage;

810: metrology data of the interconnect features;

x, Y, Z: a shaft.

Detailed Description

Techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning are set forth. For example, the alignment of interconnect features in a fan-out WLP process is evaluated and managed by the disclosed techniques.

In an embodiment, a big data and neural network system is used to correlate overlay error source factors to overlay metrology classes. The overlay error source factors include tool-dependent overlay source factors, wafer or die-dependent overlay source factors, and process context-dependent overlay error source factors. The tool-related overlay source factor includes, but is not limited to, a light source position, a photomask position, a lens position, a scan direction, a stepper position at exposure, or a wafer stage position. The wafer or die related overlay error source factors include, but are not limited to, a positional shift or rotation of the wafer, a positional shift or rotation of the die on the wafer, a shape characteristic of the wafer (e.g., a size deviation or a thickness deviation), a shape characteristic of the die (e.g., a shape deviation or a thickness deviation). The process context overlay error source factors include, but are not limited to, global alignment regions (e.g., regions on the wafer processed under global alignment control), global alignment positions (i.e., measurement positions on the wafer used to determine global alignment adjustments in enhanced global alignment ("EGA") control), field alignment positions (e.g., positions on the wafer processed under site-by-site or field-by-field alignment control), tool characteristics (such as wafer stage shape), exposure field positions (e.g., vertical position of the photomask, which translates to exposure size, depth of focus, exposure duration), stepper tool stepping speed, illumination source (white, green, ivory, or yellow light), other illumination settings, or metrology positions used to measure layer overlay. Coverage metering information is also obtained. For example, the categories of overlay errors include the size of the overlay error (e.g., on the x-axis and y-axis), the rotational offset between features, or the location of the overlay error (e.g., relative to the wafer or relative to the die). Those coverage metering data are collected and fed into machine learning.

A neural network type machine learning technique is used to correlate overlay error source factors with overlay error metrics. A regression model function is obtained as a result of the machine learning. The data is continuously updated and enhanced to continuously train the machine learning process and thus the regression model function. The regression model function may be used to predict or estimate overlay metrology values on interconnect layers formed in a fan-out WLP packaging process. Corrective adjustments to the tool alignment settings and/or wafer alignment settings may be obtained based on the regression model function.

The regression model function may be verified in various ways. For example, the estimated overlay metrology value of the reference wafer may be compared to the actual metrology value. The reference wafer may be a newly processed wafer or a previously processed wafer. Overlay error source data and actual metrology data for a reference wafer are determined or retrieved from a database. The overlay error source data for the reference wafer is applied to a regression model function to estimate the overlay metrology value. The estimated overlay metrology value is compared to the actual metrology data to determine if the estimate is sufficiently accurate. A threshold is used for the comparison. The threshold may be determined based on overlay tolerance requirements of features or layers of a wafer processing program. For example, in a fan-out WLP, a threshold of about 0.1 μm may be selected to determine whether the estimated overlay metrology values satisfy the actual metrology data for the interconnect features over the die packaged in the fan-out WLP.

The regression model function may also be verified with respect to the estimated corrective adjustment. For example, estimated corrective adjustments to tool alignment or wafer/die alignment may be made through a newly processed reference wafer. Overlay metrology is performed on the reference wafer to determine if overlay error is reduced or eliminated as estimated by the regression model function. The threshold value may be used again.

Using the disclosed techniques, the effective capacity of a metrology tool is increased due to Artificial Intelligence (AI) based coverage metrology. In an embodiment, the effective capacity of the physical metrology tool is increased by a factor of about 40. For example, using the disclosed virtual overlay metering techniques, the processing capacity of the overlay metering team has increased from 292 WLP/day to about 11400 WLP/day. Overlay metrology measurement accuracy improves to a level of less than 0.1 μm. The processing cycle covering the associated quality control is substantially reduced from about 4 hours to substantially real time. Thus, the overall process cycle time for fan-out WLP has also improved, for example, a cycle time of 0.1 days.

Since the estimated coverage values are also compared to the actual coverage values in cross-validation of artificial intelligence functions, the disclosed techniques may avoid the problem of model overfitting.

In the disclosure herein, the disclosed techniques are illustrated using a stepper-machine related coverage metrology process as an illustrative example, which is not intended to limit the scope of the present invention. The disclosed techniques may also be used to predict overlay metrology with respect to other bumping alignment tools, such as die-to-die shift metrology or ball mount template alignment metrology. Furthermore, the disclosed virtual overlay metrology techniques may also be applied with respect to front-end semiconductor process alignment tools or processes.

The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and configurations are set forth below to simplify the present description. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms such as "under.," (below), "(lower)," (above), "(upper)," or the like, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail in order to avoid unnecessarily obscuring the description of the embodiments of the invention.

Unless the context requires otherwise, throughout the description and the following claims, the word "comprise" and variations such as "comprises" and "comprising" should be interpreted in an open, inclusive sense, i.e., "including but not limited to".

The use of ordinal terms such as first, second and third, does not necessarily imply a ranked order of significance, but may merely distinguish between multiple instances of an action or structure.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise.

Fig. 1 is an exemplary coverage management system 100. As shown in FIG. 1, the system 100 includes an in-situ wafer fabrication system 110, an input data set 120, a big data unit 130, a neural network unit 140, and an output data set 150. The in-situ wafer fabrication system 110 includes a wafer processing toolset 112 (e.g., a lithography toolset 112), a process log 114, and a metrology toolset 116. The input data set 120 includes overlay error data 122, error source data 124, and other data 126. The other data 126 may be historical data regarding the wafer processing, including historical overlay error data and historical error source data in addition to or in addition to the wafer processing data obtained and maintained by the process log 114, as well as other data regarding the wafer processing. The neural network unit 140 may include the alignment control unit 142 and the verification unit 144 or work together with the alignment control unit 142 and the verification unit 144. The output data set 150 includes error prediction data 152 and corrective adjustment data 154, as well as other output data.

In operation, wafer handling toolset 112 is configured to process a wafer (e.g., a carrier wafer with dies positioned thereon) in an exemplary fan-out WLP process to form interconnect layers over the dies. The wafer processing toolset 112 may be a lithography tool and include, for example, a stepper tool (e.g., a step and repeat camera), a wafer stage or chuck, and a gantry tool, among other suitable tools. The stepper passes light through the photomask, thereby forming an image of the photomask pattern. The image is focused and reduced by a lens and projected onto the photoresist-coated surface of the wafer. The stepper operates in a step-and-repeat fashion, where a pattern on a photomask is repeatedly exposed in a grid across the surface of the wafer. The stepper moves the wafer through the wafer stage as a step from one projection (shot) location to another. The stepping movement of the wafer can be performed back and forth and side to side by the grid under the lens of the stepper. In fan-out WLP, a gantry picks up the dies and positions the dies onto designated grid points or areas on a carrier wafer. In some cases, more than one gantry tool is used to position the die onto the carrier wafer.

The process logs 114 are configured to monitor, measure, determine, and record wafer processing parameters associated with the toolset 112 and wafers positioned on the toolset 112 during processing. Some or all of the wafer processing parameter data is identified as contributing factors to or correlated with overlay errors and is incorporated into the error source data 124.

After lithography toolset 112 processes a wafer for a layer or features on the layer, metrology toolset 116 is configured to measure the wafer to determine if overlay errors exist on the wafer relative to the layer or features on the layer. The metrology data also includes details of overlay errors. The overlay error metric details are classified as a location of the overlay error on the wafer or one die, an offset size of the overlay error in the x-axis and/or y-axis, or a rotation angle of the overlay. Some of the measurements of the metrology toolset 116 are incorporated into the overlay error data 122. Zero-overlay error scenario (zero-overlay error scorrelatively) is also useful and can be collected as part of the overlay error data 122 for the purpose of modeling the correlation between the error source factors and the overlay error categories.

The big data unit 130 is configured to collect the overlay error data 122, the error source data 124, and other data 126 and combine or reconcile the various data sets for further analysis. For example, the big data unit 130 links together different data categories of overlay error data 122, overlay source data 124, and other data 126 in various ways, relative to a wafer level, a location on a wafer level, a structure on a wafer level, multiple vertical structures designed to vertically overlap, or in other suitable linking methods. In the description herein, "feature" on a wafer is used to refer to any portion of the wafer that links overlay error data 122 with error source data 124. For example, the features on the wafer may be interconnect structures. The overlay error data 122 entries are overlay errors for the interconnect structure, and the linked error source data 124 entries are wafer processing parameters recorded with respect to forming the interconnect structure.

The big data unit 130 also tunes the collected data with respect to measurement scale, units of measurement, time scale, tolerance thresholds, etc. so that each data entry can be used in the same analysis process. The big data unit 130 also enhances the collected data with respect to data entry misses and data entry interpolations. Other data processing, tuning, or combining techniques may also be present and included within the big data unit 130.

The other data 126 may be historical data related to overlay error data or error source data relative to previously processed wafers. Such historical data is processed within the big data unit 130 in the same or similar manner as the overlay error data 122 and the error source data 124.

The neural network unit 140 (or the machine learning unit 140) is an artificial intelligence machine learning unit configured to perform a supervised learning process using the data provided by the big data unit 130 to infer a regression model function that relates the overlay error source factors to the overlay error categories. The "supervised" component of machine learning may be set to be relatively relaxed. For example, rather than specifying factors as an "input" class (e.g., error source factors) and an "output" class (e.g., overlay error classes), the neural network unit 140 allows the neural network engine to function "blindly" in order to maximize the advantage of machine learning in the handling of data. Furthermore, the neural network unit 140 may be configured to perform a plurality of different supervised learning tasks, wherein different groups of factors are classified as "input" or "output". For example, overlay error metric locations in the overlay error data 122 may be classified as outputs in some learning tasks or as inputs in other learning tasks. Different learning tasks may produce different regression model functions that relate "input" factors to "output" factors.

In performing "supervised learning," the neural network unit 140 may also distinguish between "systematic" and "random" error source factors. "systematic" error source factors refer to factors that tend to repeat the same data value or pattern in the same or similar circumstances. "random" error source factors refer to factors that tend to have random data values in the same or similar circumstances, or factors in which data values cannot be controlled by the system 100. For example, the die positioning offset may be a systematic factor caused by a particular gantry tool. Stepper position offset may also be a systematic factor for a particular stepper machine. For another example, die thickness variation or die size variation may be random factors that occur randomly or cannot be controlled in a fan-out type WLP process.

Where one or more regression model functions are inferred through a supervised machine learning process, the regression model functions are used by the neural network unit 140 to estimate or predict the overlay metrology on the wafer. In an embodiment, a back propagation network is used to determine a regression model function that relates input factors to output factors. For example, in computing the regression model function, the input factors are "processed" by the "neurons" to contribute to the output, and a back propagation algorithm is used to determine the weight of the degree of contribution of each of the "neurons".

The alignment control unit 142 is configured to use the regression model function or overlay estimation/prediction results to control overlay alignment in wafer processing (e.g., wafer processing of interconnects on fan-out WLP). Specifically, the alignment control unit 142 may apply process log information for the wafer processing operation as an input to a regression model function to generate the alignment control output data 150. The alignment control output data may then be used to control or adjust wafer processing. For example, the alignment control output data 150 includes, among other things, error prediction data 152 and corrective adjustment data 154. The error prediction data 152 indicates a predicted/estimated coverage metric in one or more of the wafer positions. The corrective adjustment data 154 indicates changes to one or more of the error source factors in the error source data 124 to eliminate the estimated/predicted coverage error.

In an embodiment, the alignment control unit 142 is part of the neural network unit 140. In other embodiments, the alignment control unit 142 is a separate unit from the neural network unit 140 and includes mechanisms to automatically adjust or cause adjustment of one or more of the wafer processing tool settings or the wafer position to eliminate overlay errors.

The verification module 144 of the neural network unit 140 is configured to verify the regression model function based on metrology data obtained from the associated reference wafer. The reference wafer may be a previously processed wafer from which overlay error data and error source data are readily available. The reference wafer may also be a new wafer that is subjected to wafer processing operations and is used, inter alia, for verification purposes. For example, the estimated overlay metrology (e.g., the location and magnitude of the estimated overlay error) for the reference wafer is compared to the actual metrology measurement for the reference wafer. A threshold may be used to evaluate whether the coverage metric estimate/prediction is sufficiently accurate or satisfies the actual metric measurement. The comparison results may be used to further or continuously train and/or learn the corresponding regression model function. For example, the training data set formed from the data actually measured for overlay error source factors and overlay errors is constantly updated to reflect the latest state of the tool and process. In an embodiment, a regression model function is trained using a fixed number of data entries in a training dataset. The newly measured data entry will replace the oldest data entry to maintain the fixed number. Similarly, corrective adjustment data is essentially a prediction of an overlay-free error made for a reference wafer processed based on the corrective adjustment data. The actual metrology data for the reference wafer can be used to evaluate whether the corrective adjustment data is effective to eliminate overlay errors. Again, a threshold may be used in the evaluation. The threshold value may be selected based on the design of the wafer or the wafer processing process. For a fan-out WLP process, the threshold may be selected, for example, based on the size of the interconnect features.

Fig. 2 illustrates exemplary error source data 124. Error source data 124 includes a subset 210 of tool alignment error source factors, a subset 250 of wafer/die alignment error source factors, and a subset 280 of contextual error source factors. The tool alignment subset 210 includes data regarding tool alignment parameters or settings that affect overlay alignment. In an embodiment, tool alignment subset 210 includes prior tool alignment data 212, wafer stage position data 214, step position data 216, photomask key position data 218, exposure position data 220, or other suitable tool alignment parameter data. The wafer/die alignment subset 250 includes data regarding the location of the wafer on the wafer carrier or die on the wafer (in the case of fan-out WLP) that affects overlay alignment. In an embodiment, wafer/die alignment subset 250 includes wafer offset data 252, wafer rotation data 254, die offset data 256, die rotation data 258, or other wafer/die alignment data. The subset of contextual error sources 280 includes contextual information about the overlay metrology measurement. With the included context information, different wafer types and different wafer processing parameters may be identified and considered in the neural network processing. In an embodiment, the regression model function is determined or trained separately for different wafer types and/or different wafer processing parameters. For example, a different training data set formed from overlay error source factors and overlay errors is maintained for each wafer type and/or each wafer processing parameter set. The different training data sets are updated separately to maintain a fixed number of data entries in each training data set. In an embodiment, the contextual error source subset 280 includes depth of focus data 282, exposure duration data 284, step speed data 286, illumination setting data 288, illumination source 290, enhanced global alignment ("EGA") position 292, field position data 294, metrology position data 296, or other suitable contextual data.

The previous tool alignment data 212 is the alignment position of the wafer processing toolset 112 used for a previous wafer undergoing the same wafer processing process as the current wafer (e.g., the wafer of the current data entry). The previous tool alignment data 212 is measured with respect to the same feature or process step as the current wafer and is measured on the same scale as the current wafer. That is, the previous tool alignment data 212 is comparable to the current data entry. For example, in the case where the tool alignment data of the current wafer includes wafer stage position data 214, step position data 216, photomask key position data 218, and exposure position data 220, the previous tool alignment data 212 includes all the same data classes of the previous wafer.

Wafer stage position data 214 may be measured by the position of an actuator used to anchor the wafer stage. For example, the wafer stage may include three actuators for anchoring an x-axis position, a y-axis position, and a z-axis position of the wafer stage. The positions of the x-axis actuator, the y-axis actuator, and the z-axis actuator are recorded and logged to indicate the wafer stage position.

The step position data 216 is the position of the stepper.

The photomask key position data 218 indicates the position of the photomask anchored by the photomask key.

The exposure position data 220 indicates a position or region on the wafer exposed to the irradiation light.

Wafer stage position 214, step position 216, photomask key position 218, or exposure position 220 may be represented as positions on the x-axis in a lateral plane, the y-axis, and/or the z-axis in a vertical plane. In some embodiments, wafer stage position 214, step position 216, photomask key positions 218, or exposure positions 220 may each be represented as a positional error relative to a corresponding target position. In the measurement of the position error, x-axis offset, y-axis offset, and z-axis offset, and rotation error (angle) may be used.

It should be noted that for each of the tool alignment factors 214, 216, 218, and 220, one or more of the three different data types may be recorded and logged. The first type is position data measured by a measuring device (e.g., a laser device), which is referred to as a "measured position". The second type is the position determined by an enhanced global alignment ("EGA") system of advanced process control ("APC") prior to applying EGA adjustments, which is referred to as the "pre-alignment position" or "pre-EGA position. The third type is the position determined after applying the EGA adjustment, which is referred to as the "post-alignment position" or "post-EGA position". It should be appreciated that each of the three location data types may deviate from the actual location of the toolset 112. Such deviations in the toolset location determination may contribute to overlay errors. It is not necessary to use all three types of toolsets to align the position data in the operation of the neural network element 140. The neural network unit 140 may choose to use some types of data in some regression models and other types of data in other regression models. Furthermore, all three types of data need not be included in error source data 124. In some operating scenarios, no EGA is performed, and the pre-EGA position data type and the post-EGA position data type are not available. In some other cases, the measured position data type is not available or contained in error source data 124.

These three types of tool alignment data (e.g., measured position, pre-EGA position, post-EGA position) may be correlated with one another. For example, the post-EGA position is obtained based on the pre-EGA position. However, additional or different factors may be introduced in obtaining each of the three types, which may contribute to possible bias. For example, EGA may be affected by the EGA measurement points (referred to as "EGA locations") selected on the wafer to determine the EGA adjustment. Thus, by including one or more of the three types of location data in the tool alignment subset 210, the neural network unit 140 may implement a regression model function that more effectively reflects or accounts for the correlation between the tool alignment factors and the coverage metric categories.

Other ways to determine tool alignment may also exist and are encompassed by the present invention.

In the wafer/die alignment subset 250, wafer offset data 252 indicates the amount of offset of the wafer on the wafer carrier. Wafer offset includes x-axis offset and y-axis offset. In an embodiment, the wafer offset is determined by wafer alignment marks included on the wafer, or other suitable mechanism.

The wafer rotation data 254 indicates a rotation angle of the wafer on the wafer stage. In an embodiment, wafer rotation is determined by wafer alignment marks, or other suitable mechanism.

Die offset data 256 indicates the amount of die offset on the carrier wafer. Die offsets include x-axis offsets and y-axis offsets. In an embodiment, the die offset is determined by die alignment marks included on the die, or other suitable mechanism.

Die rotation data 258 indicates the rotation angle of the die on the carrier wafer. In an embodiment, the die rotation is determined by die alignment marks, or other suitable mechanism.

Similar to the tool alignment subset 210, the categories of data in the wafer/die alignment subset 250 may also include three data types, for example, measured position, pre-EGA position, and post-EGA position. It should be noted that the EGA system for die alignment may be different from the EGA system for wafer alignment.

The measured position, pre-EGA position, post-EGA position are provided as examples of data types for the alignment position data category. These examples are not intended to limit the scope of the present invention. For the category of alignment position data, there may also be other data types, all of which are included in the present invention. For example, there may also be field alignment of the wafer or die, and tool/wafer/die locations before and after the field alignment operation may be used in error source data 124.

The depth of focus data 282, exposure duration data 284, illumination setting data 288, illumination source data 290 are self-descriptive. The step speed data 286 indicates the moving speed of the stepper. These data are essentially parameters in the process recipe and are used to identify the context of overlay metrology and overlay error, if any. By incorporating such context data, the regression model function generated by the neural network unit 140 may be further enhanced, for example, by eliminating the complexity caused by various context factors. That is, a regression model function may be trained or determined for each of the context variables.

The EGA position data 292 indicates a plurality of position points on the wafer/die that are identified for EGA alignment purposes. The various features on the wafer typically include varying shapes and contours. Thus, selection of an EGA location (e.g., a feature on an EGA location) results in varying EGA assessments and adjustments.

The field position data 294 indicates the size of the wafer/die area illuminated in the lithography process. In an embodiment, the field position data 294 is measured by the size of the photomask opening and the distance between the photomask and the wafer surface.

The metrology position 296 indicates the position on the wafer or on the die where the overlay metrology is measured. As described herein, the metrology position on the wafer may serve as one or more of an error source factor or a coverage error category. As a source factor of error, metrology measurement locations on the wafer affect whether overlay errors are present or detectable.

It should be understood that the exemplary error source data categories listed in fig. 2 are merely examples and do not limit the scope of the invention. Other factors that contribute to the occurrence and/or magnitude of overlay error may also be used and included in error source data 124, all of which are included in the present disclosure.

Fig. 3 illustrates exemplary overlay error data 122. As shown in fig. 3, the overlay error data 122 includes four overlay error categories, namely overlay metrology position data 310, x-axis overlay error data 320 and y-axis overlay error data 330, and overlay rotation (angle) data 340. Overlay metrology position data 310 indicates where overlay errors are present/detected on the wafer or on the die. The x-axis overlay error data 320 and the y-axis overlay error data 330 indicate the magnitude of the overlay error on the x-axis or the y-axis, respectively. Overlay rotation (angle) data 340 indicates overlay error in which the actual metrology of the feature is angularly offset from the target metrology.

Various methods may be used to define overlay error. In an embodiment, the overlay error is determined based on an actual metric and a target metric of the feature. In another embodiment, the overlay error is determined based on the alignment between the upper and lower features. Other methods to determine overlay alignment accuracy or overlay error may also exist and are included in the present invention.

Fig. 4 illustrates an exemplary neural network element 140. Referring to fig. 4, the neural network unit 140 includes: a processing unit 410, e.g., a computer processor, or processing capacity allocated to the neural network unit 140 in a virtual machine application; a storage unit 420 on which the neural network application 430 is stored; a communication unit 440 configured to communicate with other computers or machines linked to the neural network unit 140 in a decentralized computing environment; an interface unit 450 configured for input, output, and user interaction; and other components 460.

The neural network application 430 includes: executable instructions that, when executed by the processing unit 410, configure the processing unit 410 to implement a training set generation module 432; a machine learning module 434 including a verification module 436; and a prediction module 438. In embodiments, executable instructions dedicated to implementing training set generation module 432, machine learning module 434, and prediction module 438 are stored on storage unit 420 in a separate dedicated space of storage unit 420 or in a separable/parseable manner so that executable instructions for these modules are readily identified by parsing or indexing.

One or more of the components of the neural network unit 140 may be implemented in a decentralized computing environment by physical means (e.g., server computers) or by virtual means. For example, multiple host servers may be linked to a wafer processing site/operation. The host servers may function together in a decentralized computing scheme to support one or more virtual layers in which the neural network unit 140 and/or the big data unit 130 reside. The virtualization layer may be any virtualization level, such as full virtualization, Operating System (OS) level virtualization, application level virtualization, or some other level of partial virtualization.

Furthermore, the components of the neural network unit 140 need not reside in the same virtualization hierarchy. Some of the components of the neural network unit 140 may be implemented by a physical layer, and some may be implemented by various levels of virtual layers, which are all included in the present invention.

Fig. 5 illustrates an operational structure 500 of the neural network application 430. The training set generation module 432 is configured to receive data from the big data unit 130 and generate a training data set in operation 510. For example, error source data 124 and overlay error data 122 are received and processed to generate a training data set to train machine learning operation 520. The training data set is constantly updated by adding new data entries and removing old data entries. In an embodiment of operation 510, the training set generation module 432 processes the received data set through a pre-training process to optimize the data set for purposes of the machine learning process 520.

In an embodiment, in machine learning operation 520, the machine learning module 434 uses the training data set to conduct a supervised training process. In particular, supervised training defines data objects in a training dataset that are classified as input and data objects that are classified as output, and pairs input data objects with corresponding output data objects. Pairs of input and output data entries are then analyzed by training connections between or among neurons to generate regression model functions. In an embodiment, the overlay source factor is classified as an input ("x") and the overlay metrology error is classified as an output ("y"). The resulting regression model functions each link one or more of the error source factors to one overlay error class, e.g., overlay metrology position, x-axis overlay error, y-axis overlay error, and overlay rotation.

In a prediction operation 530, the prediction module 438 uses the generated regression model function to predict or estimate the overlay metrology on the wafer undergoing the wafer processing operation. Specifically, wafer processing parameters are obtained as inputs from the process log 114 and applied to a regression model function to produce overlay metrology information as outputs. The prediction module 438 may also predict corrective adjustments to wafer processing parameters (e.g., to one or more of the tool alignment settings and/or wafer/die alignment factors) to eliminate or mitigate estimated/predicted overlay errors.

As shown in fig. 5, the prediction of overlay error may be made for the entire wafer. Within the wafer, the overlay errors may follow a consistent pattern, or may vary between/among different fields on the wafer. Wafer processing settings may be adjusted to specifically correct overlay errors on individual fields on a wafer using stepper devices used in wafer processing. However, there are the following cases: overlay errors on two or more fields on a wafer cannot be individually corrected and correlated to each other under wafer processing operations. A decision-making operation can be performed to determine an overall corrective adjustment of the wafer processing operation to balance between/among the two or more fields for overlay alignment.

The results of the prediction operation 530 are output to the alignment control unit 142 to control the wafer processing operation accordingly. For example, the error prediction data 152 may be used to manually adjust wafer processing parameter settings to avoid or mitigate overlay error problems. The corrective adjustment data 154 can be readily used by an operator or machine to automatically adjust wafer processing parameter settings to avoid or mitigate overlay alignment problems. The adjusted processing parameters and associated coverage metric data are again fed into the neural network unit 140 to further train or refine the regression model function, as the adjusted processing parameters together with the associated coverage metric data represent new data entries. That is, the machine learning process in the neural network unit 140 may be configured as a dynamic process that continuously updates the regression model function that relates the error source factors to the coverage error categories.

The verification module 436 is configured to evaluate whether the generated regression model function accurately represents a correlation between the error source factors and the coverage error categories. For example, the predicted overlay metrology value may be compared to the actual metrology measurement value. A threshold may be used to determine whether the estimated/predicted coverage metric satisfies the actual coverage metric data. For example, in a fan-out type WLP wafer processing operation, a threshold of 0.1 μm may be used to determine whether the estimated overlay error meets the actual overlay metrology.

Fig. 6 is a flow chart of an exemplary operational procedure 600. In exemplary operation 610, the process log 114 determines a tool position relative to a wafer processing tool (e.g., a stepper) that forms the interconnected features on the wafer. The tool position may be one or more of a measured position, a pre-registration position, or a post-registration position.

In an exemplary operation 620, the process log 114 determines a location of a portion of the wafer corresponding to a feature on the wafer, which location is referred to as an "item location" for illustrative purposes. The item position may be one or more of a measured position, a pre-alignment position, or a post-alignment position.

Fig. 7 shows a carrier wafer 700 as an example, with a plurality of dies 710 positioned on the wafer 700. The process log may determine the entry location of a portion 720 (shown as a dashed circle) of wafer 700 corresponding to the interconnect feature. As shown in fig. 7, as an illustrative example, in a fan-out WLP process, portion 720 includes die 710A locations on wafer 700. The item location of portion 720 may be measured in a variety of ways. For example, the item positions of portion 720 may include an x-axis wafer offset and/or a y-axis wafer offset, which is indicated as a misalignment between alignment marks 722 on wafer 700 and alignment marks 724 on wafer stage 730. The item position may also include a rotation between the wafer 700 and a target wafer position 702 (shown as a dashed circle) on a wafer stage 730.

In addition, the item positions may also include an x-axis tube offset and/or a y-axis tube offset. As shown as an illustrative example in fig. 7, the dies 710 positioned on the lower portion of the carrier wafer 700 each include an alignment offset relative to the target location 712. Such alignment offsets may be systematically caused by problematic gantry tools dedicated to picking up the die 710 and positioning the die 710 on the lower portion of the wafer 700. As illustratively shown with respect to portion 720, the corresponding die 710A may also include a rotational error relative to the target location 712A.

The wafer alignment position and the die alignment position may be determined together by the process log 114.

In an exemplary operation 630, the metrology toolset 116 determines a coverage metrology with respect to the intra-link features. Fig. 8 shows an illustrative example of an overlay metrology measurement of a wafer 700. As shown in fig. 8, overlay alignment metrology on different portions of the wafer 700 may be different and may not be uniform. Metrology data 810 for the intra-connected features on portion 720 is identified as being associated with tool location information and project location information. That is, those data may be linked together by the inter-connection feature.

In an exemplary operation 640, the training set generation module 432 generates a data set comprising tool position data, project position data, and overlay metrology data relative to the in-connection features on the portion 720 of the wafer 700.

In exemplary operation 650, the machine learning module 434 generates the regression model function through machine learning trained using the training data set. In an embodiment, the machine learning module 434 uses the training data set to set the parameters of a regression function that links input data (e.g., wafer alignment data and die alignment data) with output data (e.g., overlay metrology data). The training may be repeated and updated continuously as new data sets are added to the training data sets to replace older data sets. The new data set will reflect the updated state of the fabrication process in which the overlay metrology error was generated. It should be appreciated that the generated dataset may be one of many dataset entries used to train the machine learning process. The regression model function may already exist in the machine learning module 434 and may be continuously trained and/or enhanced with a new training data set. The regression model may also be newly created by the machine learning module 434.

In an exemplary operation 660, the prediction module 438 estimates the coverage metric on the second wafer based on the trained regression model function. For example, the tool position, project position relative to the second wafer may be applied to the regression model function to estimate the overlay metrology.

In an exemplary operation 670, the verification module 436 evaluates the regression model function by comparing the estimated metrology to the metrology actually measured on the second wafer.

The techniques are described with a fan-out WLP process as an example. It should be appreciated that the techniques are similarly applicable to front end wafer processing operations and other back end wafer processing operations.

The invention may be further understood by reference to the following examples:

in a method embodiment, a tool position of a wafer processing tool is determined. The wafer processing tool is used to form a first feature on a first wafer. An item location for a first portion of the first wafer is determined. The first portion corresponds to the first feature. An overlay gauge relative to the first feature is determined. Generating a data set including the tool location, the project location, and the coverage metric. Generating a function that relates one or more of the tool position or the project position on a first side of the function to the overlay metrology on a second side of the function. The function is generated by machine learning using the data set.

In a related embodiment, the tool position includes one or more of a wafer stage position, a stepper position, a photomask key position, or an exposure position.

In a related embodiment, the item position includes one or more of a wafer offset or a wafer rotation of the first wafer positioned on a wafer stage.

In a related embodiment, the item location further includes one or more of a die offset or a die rotation of a die positioned on the first portion of the first wafer.

In a related embodiment, the tool position includes one or more of a measured position, a pre-alignment position, and a post-alignment position.

In a related embodiment, the item position includes one or more of a measured position, a pre-alignment position, and a post-alignment position.

In a related embodiment, the method further comprises: determining a context in which to form the first feature on the first wafer; and generating the data set including the context.

In related embodiments, the context includes one or more of: a measurement location on the first wafer that enhances a global alignment operation, an exposure field relative to which the first feature is formed, and a metrology location on the first wafer at which the overlay metrology is measured.

In a related embodiment, the method further comprises: determining a previous tool position relative to the wafer processing tool that formed the first feature on the previous first wafer; and generating the data set including the previous tool positions.

In a related embodiment, the machine learning is performed by a neural network system.

In a related embodiment, the method further includes generating an estimated alignment metric for the second wafer based on the function.

In a related embodiment, the method further includes evaluating the function by comparing the estimated alignment gauge of the second wafer to a measured alignment gauge of the second wafer.

In a related embodiment, the method further includes generating alignment correction data relative to the second wafer based on the function, the alignment correction data specifying an adjustment to at least one of the tool position or the project position.

In another embodiment, a system comprises: a wafer processing tool configured to form features on a wafer; a metrology tool configured to measure overlay alignment of the features on the wafer; an overlay modeling tool configured to generate an estimated overlay alignment metric for the feature based on one or more of an alignment parameter of the wafer processing tool or an alignment parameter of the wafer; and a process control tool configured to adjust one or more of the alignment parameters of the wafer processing tool or the alignment parameters of the wafer based on the estimated overlay alignment metrology.

In a related embodiment, the overlay modeling tool generates a function that relates one or more of the alignment parameters of the wafer processing tool or the alignment parameters of the wafer to an overlay metrology of the feature.

In a related embodiment, the system further comprises a big data unit configured to combine the alignment parameters of the wafer processing tool, the alignment parameters of the wafer, and overlay metrology measurements of the features on the wafer into a data set.

A computing system includes a processor and a memory unit having executable instructions stored thereon. When executed by the processor, the executable instructions configure the processor to perform various acts including: receiving data relative to a tool position of a wafer processing tool that forms a first feature on a first wafer; receiving data of an item location relative to a location of the first wafer on a wafer-holding tool that formed the first feature on the first wafer; receiving data relative to a context in which the first feature was formed on the first wafer; and generating data for adjusting one or more of the tool location or the project location based on applying at least one of the data for the tool location, the data for the project location, and the data for the context into a regression model function that correlates at least one of the data for the tool location, the data for the project location, and the data for the context to an overlay metrology of the first feature on the first wafer.

In a related embodiment, the data for tool position includes one or more of an x-axis tool offset, a y-axis tool offset, and a tool rotation.

In a related embodiment, the data for the item location includes one or more of an x-axis wafer offset, a y-axis wafer offset, a wafer rotation, an x-axis die offset, a y-axis die offset, or a die rotation.

In a related embodiment, one or more of the data for the tool position or the data for the project position includes measured data, pre-alignment data, and post-alignment data.

The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the application data sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications and publications to provide yet other embodiments.

These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.