阅读说明：本技术 一种高压n沟道HEMT器件 (High-voltage n-channel HEMT device ) 是由 罗谦 姜玄青 文厚东 孟思远 于 2019-10-08 设计创作，主要内容包括：一种高压n沟道HEMT器件,属于半导体功率器件技术领域。鉴于在HEMT这类异质结器件上制备超结有较高的工艺难度,本发明针对n沟道HEMT器件提出了一种表面超结结构,通过在器件漂移区表面制备梳指状的p型半导体条块,并将该p型半导体条块与栅极进行电学连接,可在关断条件下实现漂移区沟道大范围耗尽,该耗尽区可耐受较高电压,从而器件击穿特性得以增强。另一方面,由于与栅极连接的梳指状p型表面耐压结构仅覆盖小部分漂移区面积,当器件导通时,与其关联的寄生电阻和寄生电容也相对较小,这使得器件具有相对较好的直流导通特性和高频特性。(A high-voltage n-channel HEMT device belongs to the technical field of semiconductor power devices. In view of the high process difficulty of preparing a super junction on a heterojunction device such as an HEMT, the invention provides a surface super junction structure for an n-channel HEMT device, and by preparing comb-finger-shaped p-type semiconductor strips on the surface of a drift region of the device and electrically connecting the p-type semiconductor strips with a grid, the wide-range depletion of the channel of the drift region can be realized under the condition of turn-off, and the depletion region can bear high voltage, so that the breakdown characteristic of the device is enhanced. On the other hand, since the comb finger-shaped p-type surface voltage-resistant structure connected with the gate electrode only covers a small part of the drift region area, when the device is turned on, the parasitic resistance and parasitic capacitance associated with the device are relatively small, so that the device has relatively good direct current turn-on characteristics and high-frequency characteristics.)

1. A high-voltage n-channel HEMT device, comprising: the transistor comprises a substrate (1), a buffer layer (2) arranged on the upper surface of the substrate (1), a barrier layer (3) arranged on the upper surface of the buffer layer (2), and a grid electrode (4), a source electrode (5) and a drain electrode (6) arranged on the upper surface of the barrier layer (3); the buffer layer (2) and the barrier layer (3) form a heterojunction at their contact interface, with a two-dimensional conductive channel (9) at said heterojunction interface; the source electrode (5) and the drain electrode (6) are respectively arranged on two sides of the barrier layer (3) and are in ohmic contact with the two-dimensional conductive channel (9); the grid (4) is arranged on the barrier layer (3) between the source electrode (5) and the drain electrode (6) and forms Schottky contact with the barrier layer (3); it is characterized in that the preparation method is characterized in that,

the barrier layer (3) between the grid electrode (4) and the drain electrode (6) is provided with a surface voltage-resistant structure, the surface voltage-resistant structure comprises a plurality of p-type semiconductor blocks (7) which are arranged in a comb finger shape, wherein each p-type semiconductor block (7) extends along the grid leakage direction; the p-type semiconductor blocks (7) arranged in a comb-finger shape are electrically connected with the grid electrode (4) and are not contacted with the drain electrode (6).

2. The high-voltage n-channel HEMT device of claim 1, wherein at least between adjacent p-type semiconductor blocks (7) is filled with an insulating medium (8).

3. The high-voltage n-channel HEMT device of claim 2, wherein said insulating dielectric (8) is separate from said drain (6).

4. The high-voltage n-channel HEMT device of claim 2, wherein the insulating dielectric (8) disposed between adjacent p-type semiconductor blocks (7) extends toward the drain (6) and completely fills the gap between the p-type semiconductor blocks (7) and the drain (6), i.e., the insulating dielectric (8) surrounds the p-type semiconductor blocks (7) on the side of the p-type semiconductor blocks (7) closer to the drain, and the insulating dielectric (8) contacts the drain (6).

5. The high-voltage n-channel HEMT device as claimed in any one of claims 1 to 4, wherein the surface voltage-resistant structure is used alone or in combination with a voltage-resistant structure such as a field plate.

Technical Field

The invention belongs to the technical field of semiconductor power devices, and particularly relates to an n-channel HEMT device with a comb finger-shaped p-type surface voltage-resistant structure connected with a grid.

Background

In the field of radio frequency and power integrated circuits, along with the continuous improvement of the integration level of the circuit, the circuit has higher and higher requirements on various characteristics of devices. Under the condition that the performance of the traditional silicon device almost reaches the theoretical limit, a new device with the performances of high frequency, high speed, high power, low noise, low power consumption and the like needs to be developed urgently to meet the requirements of high-speed large-capacity computers and large-capacity remote communication, and the semiconductor heterojunction device is developed accordingly. Among them, a High Electron Mobility Transistor (HEMT) has been widely noticed by those skilled in the art due to its advantages of ultra High speed, low power consumption, and the like (especially at low temperature).

The basic structure of the HEMT is a modulation-doped heterojunction, and taking an n-channel HEMT device as an example, the basic HEMT device structure is shown in fig. 1 and sequentially comprises the following components from bottom to top: the buffer layer is formed on the substrate. A Buffer layer (Buffer) is epitaxially grown on a Substrate (Substrate), and then a Barrier layer (Barrier) is grown on the Buffer layer, the Barrier layer can be doped or not according to specific situations, a Source electrode (Source), a Gate electrode (Gate) and a Drain electrode (Drain) are distributed on the Barrier layer, the Source electrode and the Drain electrode are generally in ohmic contact with a two-dimensional conductive channel by an alloying method, and the Gate electrode and the Barrier layer form schottky contact. Two-dimensional electron gas (2-DEG) exists in a triangular potential well formed by a heterojunction interface formed by the contact of the buffer layer and the barrier layer, and the electron gas is far away from the surface state, and the centers of impurities in the barrier layer and the barrier layer are separated in space and are not influenced by the scattering of ionized impurities, so that the mobility is high, the depth and the width of the triangular potential well can be controlled through gate voltage, and the concentration of the two-dimensional electron gas can be changed to achieve the aim of controlling the HEMT current. In addition, how to increase the breakdown voltage of the device is one of the research focuses in the field. Because the HEMT device is in an operating state, the electric field peak formed at the edge of the gate and the drain can reduce the breakdown voltage of the device, thereby limiting the maximum output power of the device. Therefore, in order to apply the HEMT device as a power device, research on the high-voltage HEMT device is significant. In view of this, various voltage-resistant structures have been developed, of which a field plate structure is the most common one. However, the field plate structure has high requirements on process precision, and the breakdown voltage improvement on the HEMT is limited, which limits the practical application of the field plate structure. In addition, it is not rare that researchers consider using a super junction structure in LDMOS to introduce a similar super junction in HEMT. However, since the HEMT is a heterojunction epitaxial device, there are more limitations on the process than the conventional Si-based device, which causes that the conventional super junction structure for the HEMT is actually a multi-layer epitaxial structure, the process difficulty is high, and the voltage withstand improvement effect is limited. In view of this situation, it is necessary to develop a novel super junction-like voltage withstanding structure suitable for HEMTs.

Disclosure of Invention

Aiming at the defects of high process difficulty, limited breakdown voltage promotion and the like of the voltage-resistant structure provided for the HEMT device in the prior art, the invention provides an n-channel HEMT device with a comb-finger-shaped p-type surface voltage-resistant structure connected with a grid.

In order to strengthen the withstand voltage characteristic of an n-channel HEMT device, the invention provides the following technical scheme:

a high-voltage n-channel HEMT device, comprising: the transistor comprises a substrate 1, a buffer layer 2 arranged on the upper surface of the substrate 1, a barrier layer 3 arranged on the upper surface of the buffer layer 2, and a gate 4, a source 5 and a drain 6 arranged on the upper surface of the barrier layer 3; the buffer layer 2 and the barrier layer 3 form a heterojunction at their contact interface, having a two-dimensional conductive channel 9 at the heterojunction interface; the source electrode 5 and the drain electrode 6 are respectively arranged on two sides of the barrier layer 3 and are in ohmic contact with the two-dimensional conductive channel 9; the gate 4 is disposed on the barrier layer 3 between the source 5 and the drain 6 and forms a schottky contact with the barrier layer 3; it is characterized in that the preparation method is characterized in that,

the barrier layer 3 between the gate electrode 4 and the drain electrode 6 has a surface voltage-resistant structure thereon, the surface voltage-resistant structure including a plurality of p-type semiconductor blocks 7 arranged in a comb finger shape, wherein each p-type semiconductor block 7 extends in a gate-drain direction; the p-type semiconductor blocks 7 arranged in a comb-finger shape are electrically connected to the gate electrode 4 without contacting the drain electrode 6.

Further, an insulating medium 8 is filled at least between adjacent p-type semiconductor blocks 7.

Further, the insulating dielectric 8 is in contact with or isolated from the drain 6.

In one embodiment, the two ends of the insulating dielectric 8 disposed between adjacent p-type semiconductor blocks 7 are flush with the p-type semiconductor blocks 7, i.e., the ends of the p-type semiconductor blocks 7 and the insulating dielectric 8 are flush with each other in the direction in which the p-type semiconductor blocks 7 are arranged.

In one embodiment, the insulating dielectric 8 disposed between adjacent p-type semiconductor blocks 7 may communicate with each other in the arrangement direction of the p-type semiconductor blocks 7 to semi-surround the p-type semiconductor blocks 7, and the insulating dielectric 8 is isolated from the drain electrode 6.

In one embodiment, the insulating dielectric 8 disposed between adjacent p-type semiconductor blocks 7 may extend in the direction of the drain 6 and completely fill the gap between the p-type semiconductor blocks 7 and the drain 6, i.e., the insulating dielectric 8 may communicate with each other in the direction of arrangement of the p-type semiconductor blocks 7 and semi-surround the p-type semiconductor blocks 7, and the insulating dielectric 8 may contact the drain 6.

Further, the surface voltage-resistant structure can be used in combination with a voltage-resistant structure such as a field plate.

The working principle of the invention is as follows:

due to the fact that the p-type surface voltage-resistant structure which is connected with the grid electrode and distributed in a comb-finger shape is added between the grid electrode and the drain electrode, the energy band of the barrier layer can be raised by the p-type semiconductor block, the triangular potential well at the heterojunction interface is lifted, and two-dimensional electron gas in the channel is exhausted or partially exhausted.

When the device is turned off, the comb-finger-shaped p-type semiconductor body in contact with the gate is gradually depleted when the positive voltage on the drain increases, and the fixed negative charges in the depletion region deplete the two-dimensional electron gas in the two-dimensional conduction channel. In this process, the two-dimensional electron gas under each p-type semiconductor block will be depleted first. As the positive drain voltage is further increased, the two-dimensional electron gas under the comb-finger gap region of the comb-finger p-type surface voltage-resistant structure connected to the gate electrode is gradually depleted.

If all semiconductor structures in the drift region are completely depleted when the drain voltage is sufficiently high, it is necessary that the total amount of positive fixed charges generated by ionization is equal to the total amount of negative fixed charges. According to this principle, the doping concentration of the comb-finger p-type surface voltage-resistant structure can be appropriately set so that the comb-finger p-type semiconductor bulk connected to the gate electrode is depleted simultaneously with the two-dimensional electron gas under the comb-finger gap region. Thus, the surface voltage-resistant structure between the source and the drain of the HEMT device and the extension region below the surface voltage-resistant structure form a larger depletion region which can bear higher positive voltage, and the direct result is that the voltage resistance of the device is improved.

When the device is conducted, the two-dimensional electron gas below the comb finger gap area of the comb finger-shaped p-type surface voltage-resistant structure connected with the grid electrode through the metal wire is not influenced by the p-type semiconductor blocks, has higher electron concentration and is a good conduction path, and the conduction resistance of the device is ensured not to be remarkably degraded due to the adoption of the voltage-resistant structure. In addition, when the device is designed, the comb finger-shaped p-type surface voltage-resistant structure connected with the grid electrode only covers a small part of the area of the drift region, so that parasitic capacitance introduced by the surface voltage-resistant structure is relatively small. The device based on the voltage-resistant structure has smaller on-resistance and additional capacitance, which makes it have better high-frequency characteristics.

The invention has the beneficial effects that:

the HEMT device provided by the invention realizes smaller on-resistance and withstand voltage structure parasitic capacitance while ensuring high breakdown voltage, and is suitable for the application field with higher requirements on output power and working frequency.

Drawings

Fig. 1 is a schematic perspective view of a conventional n-channel HEMT device.

FIG. 2 is one embodiment of the present invention showing an n-channel HEMT device structure with a comb finger p-type surface voltage withstanding structure connected to the gate.

FIG. 3 is a second embodiment of an n-channel HEMT device structure with a comb finger p-type surface voltage withstanding structure connected to the gate.

Fig. 4 is a top view of a second embodiment of an n-channel HEMT device structure having a comb finger p-type surface voltage withstanding structure in conjunction with a gate.

Fig. 5 is a third embodiment of an n-channel HEMT device structure of the present invention having a comb-finger p-type surface voltage withstanding structure connected to a gate.

Fig. 6 is a top view of a third embodiment of an n-channel HEMT device structure of the present invention having a comb finger p-type surface voltage withstanding structure connected to a gate.

FIG. 7 is a fourth embodiment of the present invention providing an n-channel HEMT device structure with a comb finger p-type surface voltage withstanding structure connected to the gate.

FIG. 8 is a top view of a fourth embodiment of an n-channel HEMT device structure with a comb finger p-type surface voltage withstanding structure connected to a gate in accordance with the present invention.

Fig. 9 is a schematic perspective view of a depletion region formed below a plurality of p-type semiconductor blocks distributed in a comb-finger shape in an n-channel HEMT device having a comb-finger-shaped p-type surface withstand voltage structure connected to a gate electrode according to the present invention.

Fig. 10 is a schematic view of a three-dimensional structure in which depletion regions under a plurality of p-type semiconductor blocks distributed in a comb-finger shape extend to regions under gaps of the plurality of p-type semiconductor blocks and finally a large sheet of depletion with an approximately rectangular shape is formed in an n-channel HEMT device with a comb-finger-shaped p-type surface voltage-resistant structure connected with a gate electrode.

FIG. 11 is a schematic perspective view of the GaN buffer layer formed on the upper surface of the substrate according to the present invention.

Fig. 12 is a schematic perspective view of a structure of growing an AlGaN barrier layer on the upper surface of the GaN buffer layer and forming a two-dimensional conductive channel according to the present invention.

Fig. 13 is a schematic perspective view of a source and a drain formed on an upper surface of an AlGaN barrier layer to form ohmic contact with a two-dimensional conductive channel according to the present invention.

Fig. 14 is a schematic perspective view of a gate electrode formed on an upper surface of an AlGaN barrier layer to form a schottky contact with the AlGaN barrier layer according to the present invention.

Fig. 15 is a schematic perspective view of the AlGaN barrier layer provided in the present invention, in which the upper surface of the AlGaN barrier layer between the gate and the drain is covered with a p-type GaN layer electrically connected to the gate with a gap kept therebetween.

FIG. 16 is a schematic perspective view of a plurality of p-type GaN blocks formed by etching a p-type GaN layer according to the invention.

FIG. 17 is a schematic diagram of a three-dimensional structure of the present invention with a thin insulating dielectric deposited on the side close to the gate and connected to the gate above the comb-finger p-type surface voltage-resistant structure connected to the gate.

Fig. 18 is a schematic perspective view of a metal field plate deposited over a gate and a thin insulating dielectric according to the present invention.

In the figure: reference numeral 1 denotes a substrate, 2 denotes a buffer layer, 3 denotes a barrier layer, 4 denotes a gate, 5 denotes a source, 6 denotes a drain, 7 denotes a p-type semiconductor block, 8 denotes an insulating medium, 9 denotes a two-dimensional conductive channel, 10 denotes a GaN buffer layer, 11 denotes an AlGaN barrier layer, and 12 denotes a p-type GaN block.

Detailed Description

So that those skilled in the art can better understand the principle and the scheme of the present invention, the following detailed description is given with reference to the accompanying drawings and specific embodiments. The teachings of the present invention are not limited to any particular embodiment nor represent the best embodiment, and general alternatives known to those skilled in the art are also encompassed within the scope of the present invention.