阅读说明：本技术 存储器装置及其制造方法 (Memory device and method of manufacturing the same ) 是由 江法伸 林杏莲 于 2018-11-15 设计创作，主要内容包括：一些实施例涉及一种存储器装置及其制造方法。所述存储器装置包括可编程金属化单元随机存取存储器(PMCRAM)单元。所述可编程金属化单元包括设置在底部电极之上的介电层,所述介电层包含中心区。导电桥能够在介电层内形成以及被消除,且导电桥控制在介电层的中心区内。在介电层之上设置有金属层。在底部电极与介电层之间设置有热散逸层。(Some embodiments relate to a memory device and a method of manufacturing the same. The memory device includes a programmable metallization cell random access memory (pmcrram) cell. The programmable metallization cell includes a dielectric layer disposed over a bottom electrode, the dielectric layer including a central region. The conductive bridge can be formed and eliminated within the dielectric layer with the conductive bridge being controlled within a central region of the dielectric layer. A metal layer is disposed over the dielectric layer. A heat dissipation layer is disposed between the bottom electrode and the dielectric layer.)

1. A memory device, comprising:

a bottom electrode;

a dielectric layer disposed over the bottom electrode;

a top electrode disposed over the dielectric layer, wherein a conductive bridge is selectively formable within the dielectric layer to couple the bottom electrode to the top electrode; and

a heat dissipation layer disposed between the bottom electrode and the dielectric layer.

2. The memory device of claim 1, wherein the heat dissipation layer is comprised of a material having a thermal conductivity greater than 100W/m-K.

3. The memory device of claim 1, wherein the memory device is configured to switch between a high resistance state and a low resistance state;

wherein when in the high-resistance state, a conductive pillar is disposed within a central region of the dielectric layer, the conductive pillar having a bottom surface in contact with an upper surface of the heat dissipation layer and having a top surface spaced apart from the top electrode by an upper portion of the dielectric layer; and is

Wherein when in the low resistance state, the conductive post remains disposed within the central region of the dielectric layer and a conductive bridge is formed extending through the upper portion of the dielectric layer to connect the top surface of the conductive post with the top electrode.

4. The memory device of claim 1, further comprising:

an interconnection line provided below the bottom electrode;

a sidewall spacer disposed around the top electrode and the dielectric layer, wherein the sidewall spacer comprises a first pair of outer sidewalls defined by outermost sidewalls of the top electrode; and is

Wherein the heat dissipation layer comprises a middle region located over the interconnect line and a peripheral region located under the first pair of outer sidewalls of the sidewall spacer, wherein a top surface of the middle region is located below a bottom surface of the peripheral region.

5. The memory device of claim 1, wherein the dielectric layer comprises a first pair of outer sidewalls and a second pair of outer sidewalls, wherein a width between the second pair of outer sidewalls is less than a width between the first pair of outer sidewalls.

6. A memory device, comprising:

a programmable metallization cell disposed over the interconnect line, wherein the programmable metallization cell comprises a metal ion reservoir disposed between a top electrode and a bottom electrode, wherein an electrolyte is disposed between the metal ion reservoir and the bottom electrode, wherein a heat dissipation layer is disposed between the bottom electrode and the electrolyte; and is

Wherein the electrolyte comprises a conductive bridge region over the interconnect line, wherein the conductive bridge region is defined between a top surface of the heat dissipation layer and a bottom surface of the metal ion reservoir, wherein a conductive bridge is capable of being formed and eliminated within the conductive bridge region.

7. The memory device of claim 6, further comprising:

a sidewall spacer disposed around the top electrode, the metal ion reservoir, and the electrolyte, wherein the sidewall spacer comprises a pair of outer sidewalls defined by an outermost sidewall of the top electrode and an outermost sidewall of the metal ion reservoir; and is

Wherein the heat dissipation layer includes a middle region located above the interconnect line and a peripheral region located below the pair of outer sidewalls of the sidewall spacer, wherein a top surface of the middle region is located below a bottom surface of the peripheral region.

8. The memory device of claim 6, further comprising:

a sidewall spacer disposed around the top electrode, the metal ion reservoir, and the electrolyte, wherein the sidewall spacer comprises a pair of outer sidewalls defined by an outermost sidewall of the top electrode and an outermost sidewall of the metal ion reservoir; and is

Wherein a bottom surface of the heat dissipation layer is defined by substantially flush horizontal lines.

9. The memory device of claim 6, wherein the programmable metallization cell is configured to switch between two states, the two states comprising:

a high resistance state in which a conductive structure is formed within the conductive bridge region of the electrolyte, wherein a bottom surface of the conductive structure contacts a top surface of the heat dissipation layer with a first width, wherein a top surface of the conductive structure is spaced below a top surface of the electrolyte with a second width, wherein the first width is greater than the second width, and wherein the bottom electrode is electrically isolated from the metal ion reservoir; and

a low resistance state in which the conductive bridge is formed within the conductive bridge region of the electrolyte, wherein the conductive bridge electrically couples the bottom electrode with the metal ion reservoir.

10. The memory device of claim 6, further comprising:

a substrate disposed below the programmable metallization cell, wherein the interconnect line is located above the substrate;

a first dielectric layer disposed over the substrate, wherein a portion of the bottom electrode is within the first dielectric layer;

a sidewall spacer disposed around the top electrode, the metal ion reservoir, and the electrolyte;

an interlayer dielectric layer disposed over the sidewall spacer; and

a top electrode via disposed over the top electrode, wherein a sidewall of the top electrode via is within a sidewall of the top electrode.

11. A method of manufacturing a memory device, comprising:

forming a bottom electrode over an interconnect line formed over a substrate;

forming a heat dissipation layer over the bottom electrode;

forming a dielectric layer over the heat dissipation layer;

forming a metal layer over the dielectric layer;

forming a top electrode over the metal layer;

forming a masking layer over the top electrode, wherein the masking layer covers a central region of the top electrode, wherein the masking layer exposes a sacrificial portion of the top electrode;

performing a first etch process to partially remove the bottom electrode, the heat dissipation layer, the dielectric layer, the metal layer, and the top electrode under the sacrificial portion of the top electrode; and

sidewall spacers are formed around the top electrode, around the metal layer, and around a portion of the dielectric layer.

12. The method of claim 11, further comprising:

forming a first interlayer dielectric layer over the sidewall spacers;

forming a top electrode via over the top electrode;

forming a second interlayer dielectric layer on the first interlayer dielectric layer;

forming a first conductive via over the top electrode via; and

a first conductive wire is formed over the first conductive via, wherein the first conductive wire extends beyond a sidewall of the first conductive via.

Technical Field

Embodiments of the present disclosure relate to a memory device and a method of manufacturing the same.

Background

Many modern electronic devices include electronic memory. The electronic memory may be a volatile memory (volatile memory) or a non-volatile memory (non-volatile memory). Non-volatile memory is able to retain its stored data without power, while volatile memory loses its stored data when power is removed. Programmable Metallization Cell (PMC) Random Access Memory (RAM), which may also be referred to as Conductive Bridging RAM (CBRAM), nanobridge (nanobridge), or electrolytic memory (electrolytic memory), is one promising candidate for next generation non-volatile electronic memories due to advantages over current electronic memories. Pmcmrams generally have better performance and reliability than current non-volatile memories (e.g., flash random access memories). Pmcmrams generally have better performance and density and have lower power consumption than current volatile memories, such as dynamic random-access memories (DRAMs) and static random-access memories (SRAMs).

Disclosure of Invention

An embodiment of the present invention discloses a memory device, comprising: a bottom electrode; a dielectric layer disposed over the bottom electrode; a top electrode disposed over the dielectric layer, wherein a conductive bridge is selectively formable within the dielectric layer to couple the bottom electrode to the top electrode; and a heat dissipation layer disposed between the bottom electrode and the dielectric layer.

An embodiment of the present invention discloses a memory device, comprising: a programmable metallization cell disposed over the interconnect line, wherein the programmable metallization cell comprises a metal ion reservoir disposed between a top electrode and a bottom electrode, wherein an electrolyte is disposed between the metal ion reservoir and the bottom electrode, wherein a heat dissipation layer is disposed between the bottom electrode and the electrolyte; and wherein the electrolyte comprises a conductive bridge region over the interconnect line, wherein the conductive bridge region is defined between a top surface of the heat dissipation layer and a bottom surface of the metal ion reservoir, wherein a conductive bridge is capable of being formed and eliminated within the conductive bridge region.

One embodiment of the present invention discloses a method for manufacturing a memory device, comprising: forming a bottom electrode over an interconnect line formed over a substrate; forming a heat dissipation layer over the bottom electrode; forming a dielectric layer over the heat dissipation layer; forming a metal layer over the dielectric layer; forming a top electrode over the metal layer; forming a masking layer over the top electrode, wherein the masking layer covers a central region of the top electrode, wherein the masking layer exposes a sacrificial portion of the top electrode; performing a first etch process to partially remove the bottom electrode, the heat dissipation layer, the dielectric layer, the metal layer, and the top electrode under the sacrificial portion of the top electrode; and forming sidewall spacers around the top electrode, around the metal layer, and around a portion of the dielectric layer.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1, 2, 3A, and 3B illustrate cross-sectional views of some embodiments of memory devices including programmable metallization cells according to the present disclosure.

Fig. 3C shows a graph that sets forth Current-Voltage (IV) characteristics of a number of different devices and highlights some examples of performance of a memory device that includes programmable metallization cells, in accordance with the present disclosure.

Fig. 4 illustrates a cross-sectional view of some embodiments of a memory device including an embedded memory region including two programmable metallization cells and a logic region in accordance with the present disclosure.

Figure 5A illustrates a cross-sectional view of some embodiments of a memory device including two programmable metallization cells.

Fig. 5B shows a top view of the memory device shown in fig. 5A, indicated by the cut lines in fig. 5A.

Fig. 6-10 illustrate cross-sectional and/or top views of some embodiments of a method of forming a memory device including an embedded memory region and a logic region according to the present disclosure.

Figure 11 illustrates a method in flow chart format according to some embodiments of a method of forming a memory device including programmable metallization cells in accordance with the present disclosure.

Description of the reference numerals

100. 200: PMDRAM device

101: interlayer dielectric

102: bottom interconnected vias

104. 110: dielectric layer

106: bottom electrode

107: zone(s)

108: heat dissipation layer

110 a: a first pair of outer side walls

110 b: second pair of outer side walls

112: metal layer

114: top electrode

116: sidewall spacer

118: interlayer dielectric layer

119: programmable metallization cell

120: top electrode via

122: a first conductive via

124: upper/first conductive wiring

126: a second interlayer dielectric layer

202: film stack

300 a: PMCRAM device/first State

300 b: second state

302: conductive substrate

304: conductive bridge

306: the first section

308: second section

310 a: IV Curve/first IV Curve

310 b: IV Curve/second IV Curve

310 c: IV curve

312 a: IV Curve/fourth IV Curve

312 b: IV Curve/fifth IV Curve

312 c: IV curve/sixth IV curve

400. 500 a: memory device

401 a: embedded memory region

401 b: logical area

402: bottom interconnected vias

404: second conductive via

406: second conductive wiring

408: inclined side wall

504: interconnection structure

506: substrate

508: shallow trench isolation region

510. 512: access transistor/transistor

514. 516: access gate electrode/word line gate electrode

518. 520, the method comprises the following steps: access gate dielectric/word line gate dielectric

522: access sidewall spacer/wordline sidewall spacer

524: source/drain region

526. 528, 530: IMD layer

532: bottom metallization layer/metallization layer

534. 536: metallization layer

538. 540 and 542: metal wire

544: contact element

546: through hole

550. 552: dielectric protective layer

600. 700, 800, 900, 1000: section view

602: bottom electrode film

604: heat dissipation film

702: dielectric film

704: metal film

706: top electrode film

708: shielding layer

710: sacrificial part

712: central zone

802: etching agent

1100: method of producing a composite material

1102. 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118: movement of

θ: non-zero/first non-zero angle

Phi: second non-zero angle

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to describe one element or feature's relationship to another (other) element or feature for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

The programmable metallization cell generally includes an electrolyte arranged between a top electrode and a bottom electrode. When a set voltage is applied across the top and bottom electrodes, a conductive bridge (conductive bridge) is formed within the electrolyte. When a reset voltage is applied across the top and bottom electrodes, the conductive bridges are eliminated within the electrolyte. In ideal conditions, the conductive bridge is formed near the center of the programmable metallization cell.

During the fabrication of programmable metallization cells, high heat can accumulate near the top surface of the bottom electrode due to the formation and deletion of conductive bridges when set and reset voltages are applied. The high heat may cause various problems such as large variations in set/reset voltages due to unstable formation of conductive bridges within the electrolyte. For example, in some embodiments the conductive bridge will be formed along the right-hand edge or the left-hand edge of the electrolyte, rather than at the center of the electrolyte. In addition, the size and shape of the conductive bridges may change, causing large variations in the set/reset voltages.

In some embodiments of the present disclosure, a heat dissipation layer may be provided between the electrolyte and the bottom electrode in order to more consistently form the conductive bridge in terms of shape and/or position. The heat dissipation layer dissipates heat that would otherwise accumulate at the top surface of the bottom electrode. This limits large variations in the set/reset voltages and causes the conductive bridges to form in a relatively uniform shape in a fixed central region in the electrolyte. The improved performance increases device stability, endurance, and read/write times.

Referring to fig. 1, a cross-sectional view of a pmcrram device 100 according to some embodiments is provided.

Pmdram device 100 includes a programmable metallization cell 119. The programmable metallization cell 119 includes a bottom electrode 106 and a top electrode 114, with a dielectric layer 110 (also referred to as an electrolyte in some embodiments) disposed between the top electrode 114 and the bottom electrode 106. A metal layer 112 (also referred to as a metal ion reservoir in some embodiments) is disposed over the dielectric layer 110. In some cases, the metal layer 112 may be considered to be part of the top electrode 114.

The programmable metallization cell 119 is typically disposed over an inter-level dielectric (ILD) 101 having a dielectric layer 104 disposed thereon. The bottom interconnect vias 102 connect the bottom electrodes 106 to the underlying metal layers and/or active devices of the device. A top electrode via 120 is disposed over the top electrode 114 and connects the top electrode 114 to an upper metal layer (e.g., upper conductive wiring 124). Thus, programmable metallization cell 119 may reside within interlayer dielectric (ILD) layer 118 with second ILD layer 126 disposed above ILD layer 118. A first conductive via 122 is disposed over the top electrode via 120. The first conductive wiring 124 extends beyond the sidewall of the first conductive via 122 and is connected to a bit line (not shown).

In some embodiments, the dielectric layer 110 has a first pair of outer sidewalls 110a, the first pair of outer sidewalls 110a being aligned with the outer sidewalls of the bottom electrode 106. Sidewall spacers 116 surround the outer sidewalls of the top electrode 114, the outer sidewalls of the metal layer 112, and the second pair of outer sidewalls 110b of the dielectric layer 110. The first pair of outer side walls 110a has a width greater than the width of the second pair of outer side walls 110 b. The bottom surface of sidewall spacer 116 contacts the top surface of dielectric layer 110. The outer sidewalls of the top electrode via 120 are located inward of the outer sidewalls of the top electrode 114. In some embodiments, the first conductive via 122 and the first conductive wire 124 may be composed of, for example, copper or aluminum. The outer sidewalls of the bottom electrode 106 are aligned with a first pair of outer sidewalls 110a of the dielectric layer 110. The outer sidewalls of the top electrode 114 and the outer sidewalls of the metal layer 112 are aligned with the second pair of outer sidewalls 110b of the dielectric layer 110. In some embodiments, the first pair of outer sidewalls 110a and the second pair of outer sidewalls 110b are defined from a cross-sectional view. For example, if the programmable metallization cell 119 is circular/elliptical when viewed from above, the first pair of outer sidewalls 110a is a single continuous sidewall when viewed from above, so the first "pair" of outer sidewalls 110a refers to the nature of this single continuous sidewall when depicted in cross-section. Additionally, if the programmable metallization cell 119 is circular or elliptical when viewed from above, any length associated with the cross-sectional view of the layer including the programmable metallization cell 119 corresponds to the diameter of the circle or the length defined between two vertices on the major axis (major axis) of the ellipse, respectively.

During operation, the programmable metallization cell 119 relies on a redox reaction (redox reaction) to form and dissolve a conductive bridge in the region 107 between the top electrode 114 and the bottom electrode 106. The presence of a conductive bridge in region 107 between top electrode 114 and bottom electrode 106 results in a low resistance state, while the absence of a conductive bridge in region 107 results in a high resistance state. Thus, programmable metallization cell 119 may be switched between a high resistance state and a low resistance state by applying an appropriate bias to programmable metallization cell 119 to create or dissolve a conductive bridge in region 107.

To facilitate such switching, one of the top or bottom electrodes is electrochemically inert while the other is electrochemically active. For example, in some embodiments, the bottom electrode 106 may be relatively inert and may be made of titanium nitride (TiN), tantalum nitride (TaN), tantalum, titanium, platinum, nickel, hafnium, zirconium, or tungsten, etc.; and/or top electrode 114 (and/or metal layer 112) may be electrochemically active and may be made of silver, copper, aluminum, or tellurium, among others. In other embodiments, the composition of the top and bottom electrodes may be flipped relative to that described above such that the bottom electrode is electrochemically active and the top electrode is inert. In some embodiments, the dielectric layer 110 may represent a thin film of a solid electrolyte, which is a solid material with highly mobile ions. For example, in some embodiments, the dielectric layer 110 may be formed of hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Alumina (Al)₂O₃) Amorphous silicon (a-Si) or silicon nitride (Si)₃N₄) And the like.

To improve performance by making the location and shape of the conductive bridges more repeatable, a heat dissipation layer 108 is disposed over the bottom electrode 106. The outer sidewalls of the heat dissipation layer 108 may be aligned with a first pair of outer sidewalls 110a of the dielectric layer 110 and with the outer sidewalls of the bottom electrode 106. The heat dissipation layer 108 is composed of a material having a thermal conductivity greater than 100W/m-K and is disposed between the interface between the dielectric layer 110 and the bottom electrode 106. In some embodiments, the heat dissipation layer 108 may be composed of aluminum nitride (AlN), silicon carbide (SiC), beryllium oxide (BeO), or Boron Nitride (BN). The presence of the heat dissipation layer 108 between the dielectric layer 110 and the bottom electrode 106 prevents heat from accumulating at the interface. By preventing such heat buildup, the heat dissipation layer 108 limits large variations in the set/reset voltages and makes the location and/or shape of the conductive bridges more repeatable and/or uniform within the dielectric layer 110. Thus, the heat dissipation layer 108 increases the stability, endurance, and read/write times of the programmable metallization cell 119.

Fig. 2 illustrates a cross-sectional view of some additional embodiments of a pmcmram device 200.

The pmcmram device 200 includes an ILD101 and a dielectric layer 104 disposed over the ILD 101. A bottom interconnect via 102 is disposed within ILD 101. A programmable metallization cell 119 is disposed over the bottom interconnect via 102. The programmable metallization cell 119 includes: a bottom electrode 106 disposed within the dielectric layer 104; a heat dissipation layer 108 disposed over the bottom electrode 106; and a dielectric layer 110 disposed over the heat dissipation layer 108. The programmable metallization cell 119 further comprises: a metal layer 112 disposed over the dielectric layer 110; a top electrode 114 disposed over the metal layer 112; and sidewall spacers 116 disposed around top electrode 114, metal layer 112, and dielectric layer 110.

A top electrode via 120 is disposed over the top electrode 114. ILD layer 118 is formed around programmable metallization cell 119. A second ILD layer 126 is disposed over ILD layer 118. A first conductive via 122 is disposed over the top electrode via 120. A first conductive wire 124 is disposed over the first conductive via 122. The sidewall spacer 116 includes a pair of outer sidewalls defined by the outermost sidewalls of the top electrode 114 and the outermost sidewalls of the metal layer 112. The programmable metallization cell 119 contains a film stack (film stack)202, the film stack 202 comprising: bottom electrode 106, heat dissipation layer 108, dielectric layer 110, metal layer 112, and top electrode 114. The film stack 202 includes a middle region located above the bottom interconnect via 102 and a peripheral region located below the pair of outer sidewalls of the sidewall spacer 116. The bottom surface of the middle region of the film stack 202 is located below the bottom surface of the peripheral region of the film stack 202. The heat dissipation layer 108 includes a central region located above the bottom interconnect via 102 and a peripheral region located below the pair of outer sidewalls of the sidewall spacer 116. In some embodiments, the top surface of the central region of the heat dissipation layer 108 is located below the bottom surface of the peripheral region of the heat dissipation layer 108.

In some embodiments, the heat dissipation layer 108 is formed to have a thickness in a range between approximately 1 and 31 angstroms (angstroms). At one endIn some embodiments, the bottom electrode 106 is formed of a material having a thermal conductivity of less than 100W/m-K. In some embodiments, the bottom electrode 106 may be composed of, for example, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), platinum (Pt), nickel (Ni), hafnium (Hf), or zirconium (Zr). In some embodiments, the dielectric layer 110 may be formed of, for example, hafnium oxide (HfO)₂) Zirconium dioxide (ZrO)₂) Alumina, amorphous silicon (a-Si) or silicon nitride. In some embodiments, metal layer 112 may be comprised of, for example, silver, copper, aluminum, or tellurium.

In some embodiments, the bottom electrode 106 is formed to have a thickness in a range between approximately 100 and 300 angstroms and to have a length in a range between approximately 15nm (nanometers) and 550 nm. In some embodiments, the heat dissipation layer 108 is formed to have a thickness in a range between about 15 angstroms and 75 angstroms and to have a length in a range between about 15nm and 550 nm. In some embodiments, the heat dissipation layer 108 is formed to have a thickness in a range between about 15 angstroms and 75 angstroms and to have a length in a range between about 15nm and 550 nm. In some embodiments, dielectric layer 110 is formed to have a thickness in a range between approximately 5 angstroms and 75 angstroms and to have a length in a range between approximately 15nm and 550 nm. In some embodiments, metal layer 112 is formed to have a thickness in a range between approximately 250 angstroms and 450 angstroms and to have a length in a range between approximately 15nm and 550 nm. In some embodiments, the top electrode 114 is formed to have a thickness in a range between approximately 100 and 350 angstroms and to have a length in a range between approximately 15nm and 550 nm.

Fig. 3A illustrates a cross-sectional view of some additional embodiments of a pmcmram device 300 a.

Pmcmram device 300a includes ILD101 and dielectric layer 104 disposed over ILD 101. A bottom interconnect via 102 is disposed within ILD 101. A programmable metallization cell 119 is disposed over the bottom interconnect via 102. The programmable metallization cell 119 includes: a bottom electrode 106 disposed within the dielectric layer 104; a heat dissipation layer 108 disposed over the bottom electrode 106; a dielectric layer 110 disposed over the heat dissipation layer 108. The programmable metallization cell 119 further comprises: a metal layer 112 disposed over the dielectric layer 110; a top electrode 114 disposed over the metal layer 112; sidewall spacers 116 are disposed around the top electrode 114, the metal layer 112, and the dielectric layer 110.

FIG. 3A illustrates one embodiment of a first state 300a of the programmable metallization cell 119. Programmable metallization cell 119 is in a high resistance state with conductive base 302 (referred to as a conductive pillar in some embodiments) formed within dielectric layer 110 and heat dissipation layer 108. In some embodiments, the high resistance state is achieved after performing an optimized reset state on programmable metallization cell 119. The bottom surface of the conductive substrate 302 contacts the top surface of the bottom electrode 106. In some embodiments, the conductive base 302 is located within the outermost sidewall of the bottom interconnect via 102. The bottom surface of the conductive substrate 302 includes a first width and the top surface of the conductive substrate 302 includes a second width. The first width is greater than the second width. The sidewalls of the conductive base 302 are angled at a non-zero angle θ with respect to a line perpendicular to the top surface of the heat dissipation layer 108. The top surface of the conductive substrate 302 is below the bottom surface of the metal layer 112. In this high resistance state, the bottom electrode 106 is electrically isolated from the metal layer 112.

Fig. 3B illustrates one embodiment of a second state 300B of the programmable metallization cell 119. Programmable metallization cell 119 is in a low resistance state (also referred to as the set state in some embodiments), with conductive bridge 304 formed within dielectric layer 110 and heat dissipation layer 108. The bottom surface of conductive bridge 304 contacts the top surface of bottom electrode 106. In some embodiments, conductive bridge 304 is located within the outermost sidewall of bottom interconnect via 102. The bottom surface of conductive bridge 304 includes a first width and the top surface of conductive bridge 304 includes a second width. The first width is greater than the second width. The sidewalls of the conductive bridges 304 are angled at a non-zero angle with respect to a line perpendicular to the top surface of the heat dissipation layer 108. The top surface of conductive bridge 304 contacts the bottom surface of metal layer 112. In this low resistance state, bottom electrode 106 is electrically coupled to metal layer 112.

Fig. 3C shows a series of IV curves for an embodiment of a memory device including programmable metallization cells, such as previously shown and described in fig. 1. These IV curves reflect various numbers of set and reset operations performed on the programmable metallization cells. In the set and reset operations, for example, a voltage is applied across the bottom electrode 106 and the metal layer 112, and the amount of current on the metallization cells varies as the applied voltage varies, which determines the extent to which the conductive bridge 304 is present. Thus, in a set operation, an applied (e.g., positive) voltage will form the conductive bridge 304 in the dielectric layer 110, while in a reset operation, an applied (e.g., negative) voltage will remove at least a portion of the conductive bridge 304 from the dielectric layer 110 (or vice versa). Thus, the programmable metallization cell exhibits a typical bi-stable I-V curve that shows bipolar switching of the cell.

More specifically, in fig. 3C, IV curves 310a, 310b, and 310C relate to some embodiments according to the present disclosure in which the programmable metallization cell includes a heat dissipation layer. These curves 310a, 310b, 310c show how the IV curves change in time as more set and reset operations are applied to the cell. Thus, the first IV curve 310a may be implemented, for example, up to 100 set and reset operations; the second IV curve 310b is generally implemented after 100 set and reset operations and before 10,000 set and reset operations; and the third IV curve is typically achieved after more than 10,000 set and reset operations have been performed on the cell.

Other IV curves 312a, 312b, and 312c represent different numbers of set and reset operations applied to a second programmable metallization cell that does not include a heat dissipation layer. Thus, the fourth IV curve 312a may be implemented, for example, up to 100 set and reset operations of this second programmable metallization cell; the fifth IV curve 312b is generally implemented after 100 set and reset operations and before 10,000 set and reset operations; and a sixth IV curve 312c is typically achieved after more than 10,000 set and reset operations have been performed by the second programmable metallization cell. In some cases, this second metallization cell may fail, for example, after 100 set/reset operations.

As can be seen by comparing curves 310 a-310 c and 312 a-312 c, this second programmable metallization cell ( curves 312a, 312b, 312c) without a heat dissipation layer suffers from reduced endurance due to the shifting and/or random formation of conductive bridges within the dielectric layer of the second programmable metallization cell. After a large number of set and reset operations, the reduced endurance requires, for example, applying a larger absolute voltage to the second programmable metallization cell for the set and reset operations. Thus, after the number of set and reset operations described above, the programmable metallization cell of the present disclosure including the heat dissipation layer has less set and reset voltage variation than the set and reset voltage variation of the second programmable metallization cell. Thus, heat dissipation layer 108 of programmable metallization cell 119 increases the endurance of the pmcmram device while reducing set and reset voltage variations.

In some embodiments, conductive bridge 304 includes two segments. In some embodiments, the first section 306 comprises the same physical shape and features as the conductive base (302, fig. 3A). The bottom surface of the second section 308 directly contacts the top surface of the first section 306. The bottom surface of the second section 308 has the same width as the width of the top surface of the first section 306. The width of the top surface of the second section 308 is less than the width of the bottom surface of the second section 308. The sidewalls of the first section 306 are angled at a first non-zero angle θ with respect to a line perpendicular to the top surface of the heat dissipation layer 108. The sidewalls of the second section 308 are angled at a second non-zero angle Φ with respect to a line perpendicular to the top surface of the heat dissipation layer 108. The first non-zero angle θ is an angle different from the second non-zero angle Φ. In some embodiments, the first non-zero angle θ is greater than the second non-zero angle Φ. In some embodiments, the second non-zero angle Φ is in a range of 1 degree and 60 degrees. In some embodiments, the first non-zero angle θ is in the range of 1 degree and 60 degrees.

In some embodiments, programmable metallization cell 119 transitions between a high resistance state (fig. 3A) and a low resistance state (fig. 3B). The switching process includes applying a set voltage to achieve a low resistance state. Referring to fig. 3B, the set voltage will form the second segment 308. Then, a reset voltage is applied to the programmable metallization cell 119, the second segment 308 is removed, leaving only the first segment 306, and the programmable metallization cell 119 is switched to a high resistance state (fig. 3A). This process can be repeated as many times as desired. Since the first section 306 exists in both a high resistance state and a low resistance state, the switching time is reduced compared to a conventional pmcrram device.

Referring to fig. 4, a cross-sectional view of a memory device 400 according to some embodiments is provided.

The memory device 400 includes an embedded memory region 401a and a logic region 401 b. The embedded memory region 401a includes a dielectric layer 104 disposed over the ILD 101. A bottom interconnect via 102 is disposed within ILD 101. Memory device 400 includes two programmable metallization cells. The programmable metallization cell 119 includes: a bottom electrode 106 disposed within the dielectric layer 104; a heat dissipation layer 108 disposed over the bottom electrode 106; a dielectric layer 110 disposed over the heat dissipation layer 108. The programmable metallization cell 119 further comprises: a metal layer 112 disposed over the dielectric layer 110; a top electrode 114 disposed over the metal layer 112; sidewall spacers 116 are disposed around the top electrode 114, the metal layer 112, and the dielectric layer 110. In some embodiments, the programmable metallization cell 119 includes an angled sidewall (angled) 408. The sloped sidewall 408 includes a non-zero angle relative to a line perpendicular to the top surface of the bottom interconnect via 102. A top electrode via 120 is disposed over the top electrode 114. ILD layer 118 is formed around programmable metallization cell 119. A second ILD layer 126 is disposed over ILD layer 118. A first conductive via 122 is disposed over the top electrode via 120. A first conductive wire 124 is disposed over the first conductive via 122.

Logic region 401b includes a bottom interconnect via 402 disposed within ILD 101. A dielectric layer 104 is disposed over ILD 101. ILD layer 118 is disposed over dielectric layer 104. A second ILD layer 126 is disposed over ILD layer 118. A second conductive via 404 is disposed over the bottom interconnect via 402. In some embodiments, the second conductive via 404 is comprised of, for example, copper or aluminum. A second conductive wiring 406 is provided over the second conductive via 404. In some embodiments, the second conductive wire 406 is composed of, for example, copper or aluminum. The sidewalls of the second conductive wiring 406 extend beyond the sidewalls of the second conductive via 404.

Referring to fig. 5A, a cross-sectional view of a memory device 500a according to some embodiments is provided.

Memory device 500a includes programmable metallization cells 119 disposed in interconnect structures 504 between adjacent metal layers of memory device 500 a. Memory device 500a includes a substrate 506. The substrate 506 may be, for example, a bulk substrate (e.g., a silicon substrate) or a silicon-on-insulator (SOI) substrate. The illustrated embodiment depicts one or more Shallow Trench Isolation (STI) regions 508, where the STI regions 508 may comprise dielectric-filled trenches within the substrate 506. The cut line is disposed directly above the top surface of the sidewall spacers 116 of the two programmable metallization cells 119. The cut line passes through the top electrode vias 120 of both programmable metallization cells 119.

Two access transistors 510, 512 are disposed between the STI regions 508. Access transistors 510, 512 include access gate electrodes 514, 516, respectively; access gate dielectrics 518, 520; access sidewall spacers 522; and source/drain regions 524. Source/drain regions 524 are disposed within the substrate 506 between the access gate electrodes 514, 516 and the STI regions 508 and are doped to have a first conductivity type opposite a second conductivity type of the channel regions underlying the gate dielectrics 518, 520, respectively. The word line gate electrodes 514, 516 may be, for example, doped polysilicon or a metal (e.g., aluminum, copper, or a combination thereof). The word line gate dielectrics 518, 520 may be, for example, an oxide (e.g., silicon dioxide) or a high dielectric constant (high-k) dielectric material. The wordline sidewall spacers 522 may be formed of, for example, silicon nitride (e.g., Si)₃N₄) And (4) preparing.

Interconnect structures 504 are arranged over a substrate 506 and couple devices (e.g., transistors 510, 512) to one another. The interconnect structure 504 includes a plurality of Inter-metal dielectric (IMD) layers 526, 528, 530 and a plurality of metallization layers 532, 534, 536 stacked on top of one another in an alternating manner. The IMD layers 526, 528, 530 may be made of, for example, a low-k dielectric (e.g., undoped silicate glass) or an oxide (e.g., silicon dioxide) or a very low-k dielectric layer. The metallization layers 532, 534, 536 include metal lines 538, 540, 542, the metal lines 538, 540, 542 being formed within the trenches and may be made of a metal such as copper or aluminum. Contacts 544 extend from the bottom metallization layer 532 to the source/drain regions 524 and/or gate electrodes 514, 516; and vias 546 extend between the metallization layers 532, 534, 536. The contacts 544 and vias 546 extend through the dielectric protection layers 550, 552 (which may be made of a dielectric material and may act as an etch stop layer during fabrication). The dielectric protection layers 550, 552 may be made of, for example, a very low dielectric constant dielectric material (e.g., SiC). The contacts 544 and vias 546 may be made of a metal such as copper or tungsten, for example.

Referring to FIG. 5B, a top view of the memory device 500a shown in FIG. 5A is provided, according to some embodiments.

As shown in fig. 5B, in some embodiments, the programmable metallization cell 119 has a circular/oval shape or a square/rectangular shape when viewed from above. However, in other embodiments, the corners of the square or rectangular shape may become rounded, for example due to the preference of many etching processes, such that the programmable metallization cell 119 has a square or rectangular shape with rounded corners or has a circular or elliptical shape. In some embodiments, programmable metallization cell 119 is arranged over metal line 540 and has an upper portion that is in direct electrical connection with metal line 542 without vias or contacts therebetween. In other embodiments, the top electrode via 120 couples the upper portion to the metal line 542. The top electrode via 120, the top electrode 114, and the sidewall spacer 116 may have the same circular/elliptical shape or square/rectangular shape as the programmable metallization cell 119 when viewed from above.

Fig. 6-10 illustrate cross-sectional views 600-1000 of some embodiments of a method of forming a memory device including a programmable metallization cell according to the present disclosure. Although the cross-sectional views 600-1000 of fig. 6-10 are described with reference to one method, it should be understood that the structures shown in fig. 6-10 are not limited to only that method, but rather may be independent of that method alone. While fig. 6-10 are illustrated as a series of acts, it will be appreciated that the acts are not limited as the order of the acts may be varied in other embodiments and that the disclosed methods are applicable to other configurations. In other embodiments, some acts shown and/or described may be omitted, in whole or in part.

As shown in cross-sectional view 600 of fig. 6, a bottom interconnect via 102 is formed within ILD 101. A dielectric layer 104 is formed over the ILD 101. A bottom electrode film 602 is formed over the bottom interconnect via 102 and the dielectric layer 104. In some embodiments, the bottom electrode film 602 is composed of a material having a thermal conductivity of less than 100W/m-K. In some embodiments, the bottom electrode film 602 may be composed of, for example, titanium nitride (TiN), tantalum nitride, tantalum, titanium, platinum, nickel, hafnium, or zirconium. A heat dissipation film 604 is formed over the bottom electrode film 602. In some embodiments, the heat dissipation film 604 is composed of a material having a thermal conductivity greater than 100W/m-K. In some embodiments, the heat dissipation film 604 may be composed of aluminum nitride, silicon carbide, beryllium oxide, or boron nitride.

As shown in cross-sectional view 700 of fig. 7, a dielectric film 702 is formed over the heat dissipation film 604. A metal film 704 is formed over the dielectric film 702. A top electrode film 706 is formed over the metal film 704. A shielding layer 708 is formed over the electrode film 706. The masking layer 708 covers a central region 712 of the top electrode film 706. The masking layer 708 does not cover and expose the sacrificial portion 710 of the upper surface of the top electrode film 706. In some embodiments, masking layer 708 comprises a photoresist mask. In other embodiments, the masking layer may comprise a hard mask layer (e.g., comprising a nitride layer). In some embodiments, the masking layer may comprise a multi-layer hard mask.

As shown in cross-sectional view 800 of fig. 8, an etch process is performed to etch a bottom electrode film (602 in fig. 7), a heat dissipation film (604 in fig. 7), a dielectric film (702 in fig. 7), a metal film (704 in fig. 7), a top electrode film (706 in fig. 7), and a shielding layer (708 in fig. 7) that define bottom electrode 106, heat dissipation layer 108, dielectric layer 110, metal layer 112, and top electrode 114, respectively. The etching process involves exposing the sacrificial portion (710 shown in fig. 7) to an etchant 802. The outermost sidewalls of the bottom electrode 106, the outermost sidewalls of the heat dissipation layer 108, and the outermost sidewalls of the dielectric layer 110 are aligned. The second pair of sidewalls of the dielectric layer 110 is located inside the outermost sidewalls of the dielectric layer 110. The second pair of sidewalls of the dielectric layer 110 is aligned with the outermost sidewalls of the metal layer 112 and the outermost sidewalls of the top electrode 114.

As shown in cross-sectional view 900 of fig. 9, sidewall spacers 116 are formed around dielectric layer 110, metal layer 112, and top electrode 114. The bottom surface of sidewall spacer 116 contacts the top surface of dielectric layer 110. The outermost sidewalls of the sidewall spacers 116 are aligned with the outermost sidewalls of the bottom electrode 106 and the outermost sidewalls of the heat dissipation layer 108.

As shown in the cross-sectional view 1000 of fig. 10, a top electrode via 120 is formed over the top electrode 114. An ILD layer 118 is formed around the sidewall spacers 116, the bottom electrode 106 and the heat dissipation layer 108. A second ILD layer 126 is formed over ILD layer 118 and top electrode via 120. A first conductive via 122 is formed over the top electrode via 120. In some embodiments, the first conductive via 122 may be comprised of copper or aluminum. A first conductive wiring 124 is formed over the first conductive via 122. In some embodiments, the first conductive wire 124 may be composed of, for example, copper or aluminum. The first conductive wiring 124 extends beyond the sidewall of the first conductive via 122 and is connected to a bit line (not shown). The second ILD layer 126 surrounds the first conductive via 122 and the first conductive wire 124.

Fig. 11 illustrates a method 1100 of forming a memory device, in accordance with some embodiments. While method 1100 is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited by the illustrated ordering or acts. Thus, in some embodiments, the actions may be performed in a different order than shown, and/or may be performed simultaneously. Further, in some embodiments, illustrated acts or events may be sub-divided into multiple acts or events, which may occur at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and non-illustrated acts or events may also be included.

At 1102, interconnect wiring is formed over a substrate. Fig. 6 illustrates a cross-sectional view 600 corresponding to some embodiments of act 1102.

At 1104, a bottom electrode film is formed over the interconnect line. Fig. 6 illustrates a cut-away view 600 corresponding to some embodiments of act 1104.

At 1106, a heat dissipation film is formed over the bottom electrode film. Fig. 6 illustrates a cross-sectional view 600 corresponding to some embodiments of act 1106.

At 1108, a dielectric film is formed over the heat dissipating film. Fig. 7 illustrates a cross-sectional view 700 corresponding to some embodiments of act 1108.

At 1110, a metal film is formed over the dielectric film. Fig. 7 illustrates a cut-away view 700 corresponding to some embodiments of act 1110.

At 1112, a top electrode film is formed over the metal film. Fig. 7 illustrates a cross-sectional view 700 corresponding to some embodiments of act 1112.

At 1114, a masking layer is formed over the top electrode film, the masking layer covering a central region of the top electrode film and exposing a sacrificial portion of the top electrode film. Fig. 7 illustrates a cross-sectional view 700 corresponding to some embodiments of act 1114.

At 1116, an etch process is performed to partially remove the bottom electrode film, the heat dissipation film, the dielectric film, the metal film, and the top electrode film underlying the sacrificial portion, thereby defining a bottom electrode, a heat dissipation layer, a dielectric, a metal layer, and a top electrode, respectively. Figure 8 illustrates a cross-sectional view 800 corresponding to some embodiments of act 1116.

At 1118, sidewall spacers are formed around the top electrode, around the metal layer, and around a portion of the dielectric layer. Fig. 9 illustrates a cross-sectional view 900 corresponding to some embodiments of act 1118.

Accordingly, in some embodiments, the present disclosure relates to a method of forming a programmable metallization cell that includes a heat dissipation layer formed between a bottom electrode and a dielectric, the heat dissipation layer being comprised of a material having a thermal conductivity greater than 100W/m-K.

In some embodiments, the present disclosure relates to a pmcmram device. The pmcrram device includes: a dielectric layer disposed over the bottom electrode, the dielectric layer including a central region, the conductive bridges being capable of being formed and eliminated within the dielectric layer, and the conductive bridges being controlled within the central region of the dielectric layer; a metal layer disposed over the dielectric layer; a heat dissipation layer disposed between the bottom electrode and the dielectric layer. In some embodiments, the heat dissipation layer is comprised of a material having a thermal conductivity greater than 100W/m-K. In some embodiments, the heat dissipation layer is comprised of aluminum nitride, silicon carbide, beryllium oxide, or boron nitride. In some embodiments, the memory device is configured to switch between a high resistance state and a low resistance state; wherein when in the high-resistance state, a conductive pillar is disposed within a central region of the dielectric layer, the conductive pillar having a bottom surface in contact with an upper surface of the heat dissipation layer and having a top surface spaced apart from the top electrode by an upper portion of the dielectric layer; and wherein when in the low resistance state, the conductive post remains disposed within the central region of the dielectric layer and a conductive bridge is formed extending through the upper portion of the dielectric layer to connect the top surface of the conductive post with the top electrode. In some embodiments, the bottom surface of the conductive pillar has a first width and the top surface of the conductive pillar has a second width when in the high resistance state and when in the low resistance state, wherein the first width is greater than the second width. In some embodiments, the memory device further comprises: an interconnection line provided below the bottom electrode; a metal layer disposed between the top electrode and the dielectric layer; and a sidewall spacer disposed around the top electrode, the metal layer, and the dielectric layer, wherein the sidewall spacer comprises a first pair of outer sidewalls defined by an outermost sidewall of the top electrode and an outermost sidewall of the metal layer; and wherein the heat dissipation layer comprises a middle region located over the interconnect line and a peripheral region located under the first pair of outer sidewalls of the sidewall spacer, wherein a bottom surface of the middle region is substantially flush with a bottom surface of the peripheral region. In some embodiments, the memory device further comprises: an interconnection line provided below the bottom electrode; a sidewall spacer disposed around the top electrode and the dielectric layer, wherein the sidewall spacer comprises a first pair of outer sidewalls defined by outermost sidewalls of the top electrode; and wherein the heat dissipation layer comprises a middle region located over the interconnect line and a peripheral region located under the first pair of outer sidewalls of the sidewall spacer, wherein a top surface of the middle region is located below a bottom surface of the peripheral region. In some embodiments, the dielectric layer comprises a first pair of outer sidewalls and a second pair of outer sidewalls, wherein a width between the second pair of outer sidewalls is less than a width between the first pair of outer sidewalls. In some embodiments, the first pair of outer sidewalls are aligned with outer sidewalls of the heat dissipation layer.

In other embodiments, the present disclosure relates to a memory device. The memory device includes a Conductive Bridging Random Access Memory (CBRAM) cell disposed over an interconnect line, the programmable metallization cell including a metal ion reservoir disposed between a top electrode and a bottom electrode, an electrolyte disposed between the metal ion reservoir and the bottom electrode, and a heat dissipation layer disposed between the bottom electrode and the electrolyte; the electrolyte includes a conductive bridge region over the interconnect line, the conductive bridge region being defined between a top surface of the heat dissipation layer and a bottom surface of the metal ion reservoir, the conductive bridge being capable of being formed and eliminated within the conductive bridge region. In some embodiments, the heat dissipation layer is comprised of a material having a thermal conductivity greater than 100W/m-K. In some embodiments, the memory device further comprises: a sidewall spacer disposed around the top electrode, the metal ion reservoir, and the electrolyte, wherein the sidewall spacer comprises a pair of outer sidewalls defined by an outermost sidewall of the top electrode and an outermost sidewall of the metal ion reservoir; and wherein the heat dissipation layer comprises a middle region located above the interconnect line and a peripheral region located below the pair of outer sidewalls of the sidewall spacer, wherein a top surface of the middle region is located below a bottom surface of the peripheral region. In some embodiments, the memory device further comprises: a sidewall spacer disposed around the top electrode, the metal ion reservoir, and the electrolyte, wherein the sidewall spacer comprises a pair of outer sidewalls defined by an outermost sidewall of the top electrode and an outermost sidewall of the metal ion reservoir; and wherein a bottom surface of the heat dissipation layer is defined by substantially flush horizontal lines. In some embodiments, the programmable metallization cell is configured to switch between two states, including: a high resistance state in which a conductive structure is formed within the conductive bridge region of the electrolyte, wherein a bottom surface of the conductive structure contacts a top surface of the heat dissipation layer with a first width, wherein a top surface of the conductive structure is spaced below a top surface of the electrolyte with a second width, wherein the first width is greater than the second width, and wherein the bottom electrode is electrically isolated from the metal ion reservoir; and a low resistance state in which the conductive bridge is formed within the conductive bridge region of the electrolyte, wherein the conductive bridge electrically couples the bottom electrode with the metal ion reservoir. In some embodiments, the memory device further comprises: a substrate disposed below the programmable metallization cell, wherein the interconnect line is located above the substrate; a first dielectric layer disposed over the substrate, wherein a portion of the bottom electrode is within the first dielectric layer; a sidewall spacer disposed around the top electrode, the metal ion reservoir, and the electrolyte; an interlayer dielectric layer disposed over the sidewall spacer; and a top electrode via disposed over the top electrode, wherein a sidewall of the top electrode via is located within a sidewall of the top electrode. In some embodiments, the memory device further comprises: an interconnect line within the logic region, wherein the interconnect line is disposed over the substrate; a first conductive via disposed over the top electrode via; a first conductive wire disposed over the first conductive via, wherein the first conductive wire extends beyond a sidewall of the first conductive via; a second conductive via disposed above the interconnect line within the logic region; and a second conductive wire disposed over the second conductive via, wherein the second conductive wire extends beyond a sidewall of the second conductive via.

In other embodiments, the present disclosure relates to a method of manufacturing a memory device. The method comprises the following steps: forming a bottom electrode over an interconnect line formed over a substrate; forming a heat dissipation layer over the bottom electrode; forming a dielectric layer over the heat dissipation layer; forming a metal layer over the dielectric layer; forming a top electrode over the metal layer; forming a shielding layer over the top electrode, the shielding layer covering a central region of the top electrode, the shielding layer exposing a sacrificial portion of the top electrode; performing a first etching process to partially remove the bottom electrode, the heat dissipation layer, the dielectric layer, the metal layer and the top electrode under the sacrificial portion of the top electrode; sidewall spacers are formed around the top electrode, around the metal layer, and around a portion of the dielectric layer. In some embodiments, the dielectric layer comprises a first pair of outer sidewalls aligned with outer sidewalls of the top electrode, wherein the dielectric layer comprises a second pair of outer sidewalls aligned with outer sidewalls of the heat dissipation layer, wherein the first pair of outer sidewalls are located inward of the second pair of outer sidewalls, wherein a bottommost surface of the sidewall spacer contacts an upper surface of the dielectric layer. In some embodiments, further comprising: forming a first interlayer dielectric layer over the sidewall spacers; forming a top electrode via over the top electrode; forming a second interlayer dielectric layer on the first interlayer dielectric layer; forming a first conductive via over the top electrode via; and forming a first conductive wire over the first conductive via, wherein the first conductive wire extends beyond a sidewall of the first conductive via. In some embodiments, further comprising: forming a second interconnection line in the logic region; forming a second conductive via over the second interconnect line; and forming a second conductive wire over the second conductive via, wherein the second conductive wire extends beyond a sidewall of the second conductive via.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.