阅读说明：本技术 用于测量秒脉冲信号时差的电路和装置 (Circuit and device for measuring time difference of pulse per second signal ) 是由 谭斯仪 高峰 许祥滨 孙功宪 于 2019-10-21 设计创作，主要内容包括：本申请适用于时标检测技术领域,提供了一种用于测量秒脉冲信号时差的电路和装置,包括鉴相单元、时间电压转换单元、电压复位单元及电压输出单元,通过鉴相单元将接收到的基准秒脉冲信号与待测秒脉冲信号进行异或运算得到电压转换控制信号,通过时间电压转换单元基于电压转换控制信号对其包含的积分电容进行充电控制,通过电压复位单元对积分电容进行放电控制,进而获取积分电容两端所残留的电压的第二电压值,通过电压输出单元读取积分电容充电完成后的第一电压值及放电完成后的第二电压值,基于第一电压值和第二电压值的差值即可计算出待测秒脉冲信号与基准秒脉冲信号之间的时差。本申请的电路结构简单,成本较低。(The application is applicable to the technical field of time scale detection, and provides a circuit and a device for measuring the time difference of pulse signals per second, which comprises a phase discrimination unit, a time-voltage conversion unit, a voltage reset unit and a voltage output unit, the received reference second pulse signal and the second pulse signal to be detected are subjected to exclusive OR operation through the phase discrimination unit to obtain a voltage conversion control signal, the time voltage conversion unit controls the charging of the integral capacitor based on the voltage conversion control signal, the voltage reset unit controls the discharging of the integral capacitor, and then obtaining a second voltage value of the voltage remained at the two ends of the integrating capacitor, reading the first voltage value after the charging of the integrating capacitor and the second voltage value after the discharging of the integrating capacitor through the voltage output unit, and calculating the time difference between the pulse per second signal to be measured and the reference pulse per second signal based on the difference value of the first voltage value and the second voltage value. The circuit structure of this application is simple, and the cost is lower.)

1. A circuit for measuring time difference of a pulse per second signal, comprising: the phase demodulation unit, the time-voltage conversion unit, the voltage reset unit and the voltage output unit;

the phase discrimination unit comprises a reference signal input end, a signal to be detected input end and an output end, wherein the reference signal input end is used for receiving a reference pulse per second signal, the signal to be detected input end is used for receiving a pulse per second signal to be detected, and the output end of the phase discrimination unit is electrically connected with the controlled end of the time-voltage conversion unit; the phase discrimination unit carries out XOR operation on the received reference pulse-per-second signal and the pulse-per-second signal to be detected to obtain a voltage conversion control signal, and the voltage conversion control signal is output to a controlled end of the time-voltage conversion unit through an output end of the phase discrimination unit;

the time-voltage conversion unit comprises an input end, a controlled end, a voltage control end and an integrating capacitor, wherein the input end of the time-voltage conversion unit is used for being connected with a reference voltage source; the time-voltage conversion unit charges the integrating capacitor when detecting that the voltage conversion control signal is a charging signal, and stops charging the integrating capacitor when detecting that the voltage conversion control signal is a charging stop signal;

the voltage reset unit comprises an input end and an output end, the input end of the voltage reset unit is used for receiving a voltage reset signal, and the output end of the voltage reset unit and the voltage control end of the time-voltage conversion unit are connected to the input end of the voltage output unit in a shared mode; the voltage reset unit controls the integration capacitor to discharge when detecting that the voltage reset signal is a discharge signal, and controls the integration capacitor to stop discharging when detecting that the voltage reset signal is a discharge stop signal;

the voltage output unit comprises an input end and an output end, the voltage output unit reads a first voltage value of the integration capacitor after the charging of the integration capacitor is stopped and a second voltage value of the integration capacitor after the discharging of the integration capacitor is stopped through the input end of the voltage output unit, and the voltage output unit outputs the first voltage value and the second voltage value through the output end of the voltage output unit.

2. The circuit for measuring a time difference of a pulse per second signal according to claim 1, wherein the time-voltage conversion unit further comprises: a constant current source unit and a switch control unit;

the constant current source unit comprises a power supply end, an input end and an output end, the power supply end of the constant current source unit is connected with a first power supply, the input end of the constant current source is the input end of the time-voltage conversion unit, and the output end of the constant current source unit is connected with the first end of the switch control unit;

the switch control unit comprises a first end, a second end and a controlled end, the integral capacitor comprises a first end and a second end, the second end of the switch control unit is connected with the first end of the integral capacitor, the controlled end of the switch control unit is the controlled end of the time-voltage conversion unit, the first end of the integral capacitor is the voltage control end of the time-voltage conversion unit, and the second end of the integral capacitor is grounded.

3. The circuit for measuring time difference of pulse per second signal according to claim 1, wherein the phase detection unit comprises: an exclusive-or gate;

the first input end of the exclusive-or gate is the reference signal input end of the phase discrimination unit, the second input end of the exclusive-or gate is the signal input end to be detected of the phase discrimination unit, and the output end of the exclusive-or gate is the output end of the phase discriminator unit.

4. The circuit for measuring a time difference of a pulse per second signal according to claim 2, wherein the constant current source unit comprises: the circuit comprises a first operational amplifier, a first resistor, a second resistor, a first switching tube, a second switching tube and a third switching tube;

the non-inverting input end of the first operational amplifier is the input end of the constant current source unit, the inverting input end of the first operational amplifier and the low potential end of the first switching tube are connected to the first end of the second resistor in common, the second end of the second resistor is grounded, the output end of the first operational amplifier is connected to the first end of the first resistor, the second end of the first resistor is connected to the controlled end of the first switching tube, the high potential end of the first switching tube, the low potential end of the second switching tube and the controlled end of the second switching tube are connected to the controlled end of the third switching tube in common, the high potential end of the second switching tube and the high potential end of the third switching tube are connected in common to serve as the power supply end of the constant current source unit, and the low potential end of the third switching tube is the output end of the constant current source unit.

5. The circuit for measuring a time difference of a pulse per second signal according to claim 2, wherein the switching control unit comprises: a first diode and an in-phase buffer;

the positive electrode of the first diode and the output end of the in-phase buffer are connected in common to be used as the first end of the switch control unit, the negative electrode of the first diode is the second end of the switch control unit, and the input end of the in-phase buffer is the controlled end of the switch control unit.

6. The circuit for measuring a time difference of a pulse per second signal according to claim 1, wherein the voltage reset unit comprises: a third resistor, a fourth resistor, a fifth resistor and a fourth switching tube;

the first end of the fourth resistor is a signal input end of the voltage reset unit, the second end of the fourth resistor and the first end of the fifth resistor are connected to the controlled end of the fourth switching tube in a shared manner, the second end of the fifth resistor and the low-potential end of the fourth switching tube are connected to the ground in a shared manner, the high-potential end of the fourth switching tube is connected with the second end of the third resistor, and the first end of the third resistor is an output end of the voltage reset unit.

7. The circuit for measuring a time difference of a pulse per second signal according to claim 1, wherein the voltage output unit comprises: a second operational amplifier;

the non-inverting input end of the second operational amplifier is the input end of the voltage output unit, and the inverting input end of the second operational amplifier and the output end of the second operational amplifier are connected in common to be used as the output end of the voltage output unit.

8. The circuit for measuring time difference of pulse per second signal according to claim 4, wherein the first switch tube is an NMOS tube, the second switch tube is a first PNP type triode, and the third switch tube is a second PNP type triode;

the grid electrode of the NMOS tube is the controlled end of the first switch tube, the drain electrode of the NMOS tube is the high potential end of the first switch tube, the source electrode of the NMOS tube is the low potential end of the first switch tube, the base electrode of the first PNP type triode is the controlled end of the second switch tube, the emitter electrode of the first PNP type triode is the high potential end of the second switch tube, the collector electrode of the first PNP type triode is the low potential end of the second switch tube, the base electrode of the second PNP type triode is the controlled end of the third switch tube, the emitter electrode of the second PNP type triode is the high potential end of the third switch tube, and the collector electrode of the second PNP type triode is the low potential end of the third switch tube.

9. The circuit for measuring the time difference of pulse per second signal according to claim 6, wherein the fourth switching tube is an NPN type triode;

the base electrode of the NPN type triode is the controlled end of the fourth switching tube, the collector electrode of the NPN type triode is the high potential end of the fourth switching tube, and the emitter electrode of the NPN type triode is the low potential end of the fourth switching tube.

10. An apparatus for measuring time differences of a millisecond pulse signal, comprising: a processing unit and a circuit for measuring a time difference of a pulse per second according to any one of claims 1 to 9;

the processing unit is connected with the output end of the voltage output unit;

the processing unit is used for calculating the time difference between the pulse per second signal to be measured and the reference pulse per second signal based on the first voltage value and the second voltage value.

Technical Field

The application belongs to the technical field of time scale detection, and particularly relates to a circuit and a device for measuring a time difference of a pulse per second signal.

Background

With the rapid development of science and technology, people put higher and higher requirements on precision time and time accuracy. The requirements of power systems, communication systems, traffic systems and the like on time synchronization are continuously improved, and the time synchronization is more and more widely regarded and applied. Pulse Per Second (PPS) signals are often used as time standards for access to terminal devices requiring time synchronization. In order to ensure the correct operation of the time synchronization network of the large-scale system, the accuracy of the pulse signal as the time scale needs to be detected to ensure the working accuracy of the clock synchronization equipment.

Disclosure of Invention

In view of this, the embodiments of the present application provide a circuit and a device for measuring a time difference of a pulse per second signal, so as to solve the problems of a complex circuit structure and high cost of the existing pulse per second signal detection device.

A first aspect of an embodiment of the present application provides a circuit for measuring a time difference between pulse-per-second signals, including: the phase demodulation unit, the time-voltage conversion unit, the voltage reset unit and the voltage output unit;

the phase discrimination unit comprises a reference signal input end, a signal to be detected input end and an output end, wherein the reference signal input end is used for receiving a reference pulse per second signal, the signal to be detected input end is used for receiving a pulse per second signal to be detected, and the output end of the phase discrimination unit is electrically connected with the controlled end of the time-voltage conversion unit; the phase discrimination unit carries out XOR operation on the received reference pulse-per-second signal and the pulse-per-second signal to be detected to obtain a voltage conversion control signal, and the voltage conversion control signal is output to a controlled end of the time-voltage conversion unit through an output end of the phase discrimination unit;

the time-voltage conversion unit comprises an input end, a controlled end, a voltage control end and an integrating capacitor, wherein the input end of the time-voltage conversion unit is used for being connected with a reference voltage source; the time-voltage conversion unit charges the integrating capacitor when detecting that the voltage conversion control signal is a charging signal, and stops charging the integrating capacitor when detecting that the voltage conversion control signal is a charging stop signal;

the voltage reset unit comprises an input end and an output end, the input end of the voltage reset unit is used for receiving a voltage reset signal, and the output end of the voltage reset unit and the voltage control end of the time-voltage conversion unit are connected to the input end of the voltage output unit in a shared mode; the voltage reset unit controls the integration capacitor to discharge when detecting that the voltage reset signal is a discharge signal, and controls the integration capacitor to stop discharging when detecting that the voltage reset signal is a discharge stop signal;

the voltage output unit comprises an input end and an output end, the voltage output unit reads a first voltage value of the integration capacitor after the charging of the integration capacitor is stopped and a second voltage value of the integration capacitor after the discharging of the integration capacitor is stopped through the input end of the voltage output unit, and the voltage output unit outputs the first voltage value and the second voltage value through the output end of the voltage output unit.

Further, the time-to-voltage conversion unit further includes: a constant current source unit and a switch control unit;

the constant current source unit comprises a power supply end, an input end and an output end, the power supply end of the constant current source unit is connected with a first power supply, the input end of the constant current source is the input end of the time-voltage conversion unit, and the output end of the constant current source unit is connected with the first end of the switch control unit;

the switch control unit comprises a first end, a second end and a controlled end, the integral capacitor comprises a first end and a second end, the second end of the switch control unit is connected with the first end of the integral capacitor, the controlled end of the switch control unit is the controlled end of the time-voltage conversion unit, the first end of the integral capacitor is the voltage control end of the time-voltage conversion unit, and the second end of the integral capacitor is grounded.

Further, the phase detection unit includes: an exclusive-or gate;

the first input end of the exclusive-or gate is the reference signal input end of the phase discrimination unit, the second input end of the exclusive-or gate is the signal input end to be detected of the phase discrimination unit, and the output end of the exclusive-or gate is the output end of the phase discriminator unit.

Further, the constant current source unit includes: the circuit comprises a first operational amplifier, a first resistor, a second resistor, a first switching tube, a second switching tube and a third switching tube;

the non-inverting input end of the first operational amplifier is the input end of the constant current source unit, the inverting input end of the first operational amplifier and the low potential end of the first switching tube are connected to the first end of the second resistor in common, the second end of the second resistor is grounded, the output end of the first operational amplifier is connected to the first end of the first resistor, the second end of the first resistor is connected to the controlled end of the first switching tube, the high potential end of the first switching tube, the low potential end of the second switching tube and the controlled end of the second switching tube are connected to the controlled end of the third switching tube in common, the high potential end of the second switching tube and the high potential end of the third switching tube are connected in common to serve as the power supply end of the constant current source unit, and the low potential end of the third switching tube is the output end of the constant current source unit.

Further, the switch control unit includes: a first diode and an in-phase buffer;

the positive electrode of the first diode and the output end of the in-phase buffer are connected in common to be used as the first end of the switch control unit, the negative electrode of the first diode is the second end of the switch control unit, and the input end of the in-phase buffer is the controlled end of the switch control unit.

Further, the voltage reset unit includes: a third resistor, a fourth resistor, a fifth resistor and a fourth switching tube;

the first end of the fourth resistor is a signal input end of the voltage reset unit, the second end of the fourth resistor and the first end of the fifth resistor are connected to the controlled end of the fourth switching tube in a shared manner, the second end of the fifth resistor and the low-potential end of the fourth switching tube are connected to the ground in a shared manner, the high-potential end of the fourth switching tube is connected with the second end of the third resistor, and the first end of the third resistor is an output end of the voltage reset unit.

Further, the voltage output unit includes: a second operational amplifier;

the non-inverting input end of the second operational amplifier is the input end of the voltage output unit, and the inverting input end of the second operational amplifier and the output end of the second operational amplifier are connected in common to be used as the output end of the voltage output unit.

Further, the first switch tube is an NMOS tube, the second switch tube is a first PNP type triode, and the third switch tube is a second PNP type triode;

the grid electrode of the NMOS tube is the controlled end of the first switch tube, the drain electrode of the NMOS tube is the high potential end of the first switch tube, the source electrode of the NMOS tube is the low potential end of the first switch tube, the base electrode of the first PNP type triode is the controlled end of the second switch tube, the emitter electrode of the first PNP type triode is the high potential end of the second switch tube, the collector electrode of the first PNP type triode is the low potential end of the second switch tube, the base electrode of the second PNP type triode is the controlled end of the third switch tube, the emitter electrode of the second PNP type triode is the high potential end of the third switch tube, and the collector electrode of the second PNP type triode is the low potential end of the third switch tube.

Further, the fourth switching tube is an NPN-type triode;

the base electrode of the NPN type triode is the controlled end of the fourth switching tube, the collector electrode of the NPN type triode is the high potential end of the fourth switching tube, and the emitter electrode of the NPN type triode is the low potential end of the fourth switching tube.

A second aspect of embodiments of the present application provides an apparatus for measuring a time difference between pulse-per-second signals, comprising: a processing unit and the circuit for measuring the time difference of the pulse per second signal according to the first aspect;

the processing unit is connected with the output end of the voltage output unit;

the processing unit is used for calculating the time difference between the pulse per second signal to be measured and the reference pulse per second signal based on the first voltage value and the second voltage value.

The circuit and the device for measuring the time difference of the pulse per second signal have the following advantages that:

the circuit for measuring the time difference of the pulse per second signal provided by the embodiment of the application carries out XOR operation on the received reference pulse per second signal and the pulse per second signal to be measured through the phase discrimination unit to obtain a voltage conversion control signal, the time-voltage conversion unit controls the charging of the integral capacitor based on the voltage conversion control signal, further converting the time difference between the pulse per second signal to be measured and the reference pulse per second signal into corresponding voltage values, performing discharge control on the integrating capacitor through the voltage reset unit, further, a second voltage value corresponding to the voltage remaining at the two ends of the integrating capacitor is obtained, the first voltage value after the charging of the integrating capacitor and the second voltage value after the discharging are read by the voltage output unit, and then the time difference between the pulse per second signal to be measured and the reference pulse per second signal can be calculated based on the difference value between the first voltage value and the second voltage value. It can be seen that the circuit structure of the application is simple, and the cost is lower.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a block diagram of a circuit for measuring a time difference between pulse-per-second signals according to an embodiment of the present disclosure;

fig. 2 is a block diagram of a circuit for measuring a time difference between signals of second pulses according to another embodiment of the present application;

fig. 3 is a specific circuit diagram of a circuit for measuring a time difference of a pulse per second according to an embodiment of the present application;

fig. 4 is a block diagram of an apparatus for measuring a time difference between signals of second pulses according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It is to be noted that the term "comprises" and any variants thereof in the description and claims of this application are intended to cover non-exclusive inclusions. For example, a system, product or apparatus that comprises a list of elements is not limited to those elements listed, but may alternatively include other elements not listed or inherent to such product or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.

The circuit for measuring the time difference of the pulse per second signal provided by the embodiment of the application carries out XOR operation on the received reference pulse per second signal and the pulse per second signal to be measured through the phase discrimination unit to obtain a voltage conversion control signal, the time-voltage conversion unit controls the charging of the integral capacitor based on the voltage conversion control signal, further converting the time difference between the pulse per second signal to be measured and the reference pulse per second signal into corresponding voltage values, performing discharge control on the integrating capacitor through the voltage reset unit, further, a second voltage value corresponding to the voltage remaining at the two ends of the integrating capacitor is obtained, the first voltage value after the charging of the integrating capacitor and the second voltage value after the discharging are read by the voltage output unit, and then the time difference between the pulse per second signal to be measured and the reference pulse per second signal can be calculated based on the difference value between the first voltage value and the second voltage value. It can be seen that the circuit structure of the application is simple, and the cost is lower.

Fig. 1 is a block diagram of a circuit for measuring a time difference between pulse signals of seconds according to an embodiment of the present application, and for convenience of description, only the parts related to the embodiment of the present application are shown, and detailed descriptions are as follows:

referring to fig. 1, a circuit 100 for measuring a time difference between pulses of a second pulse signal according to an embodiment of the present application includes: the phase detection circuit comprises a phase detection unit 11, a time-voltage conversion unit 12, a voltage reset unit 13 and a voltage output unit 14. Wherein:

the phase discrimination unit 11 comprises a reference signal input end, a signal to be detected input end and an output end, the reference signal input end of the phase discrimination unit 11 is used for receiving a reference pulse per second signal, the signal to be detected input end of the phase discrimination unit 11 is used for receiving the pulse per second signal to be detected, and the output end of the phase discrimination unit 11 is connected with the controlled end of the time-voltage conversion unit 12; the phase discrimination unit 11 performs exclusive or operation on the received reference pulse-per-second signal and the pulse-per-second signal to be detected to obtain a voltage conversion control signal, and outputs the voltage conversion control signal to the controlled end of the time-voltage conversion unit 12.

The time-voltage conversion unit 12 includes an input terminal, a controlled terminal, a voltage control terminal, and an integrating capacitor (not shown in fig. 1), wherein the input terminal of the time-voltage conversion unit 12 is used for connecting a reference voltage source; the time-voltage conversion unit 12 charges the integration capacitor included therein when detecting that the voltage conversion control signal is the charge signal, and stops charging the integration capacitor included therein when detecting that the voltage conversion control signal is the charge stop signal.

The voltage reset unit 13 comprises an input end and an output end, the input end of the voltage reset unit 13 is used for receiving a voltage reset signal, and the output end of the voltage reset unit 13 and the voltage control end of the time-voltage conversion unit 12 are connected to the input end of the voltage output unit 14 in a shared manner; the voltage reset unit 13 controls the integration capacitor in the time-voltage conversion unit 12 to discharge when detecting that the voltage reset signal is the discharge signal, and controls the integration capacitor in the time-voltage conversion unit 12 to stop discharging when detecting that the voltage reset signal is the discharge stop signal.

The voltage output unit 14 includes an input end and an output end, the voltage output unit 14 reads a first voltage value of the integration capacitor after stopping charging and a second voltage value of the integration capacitor after stopping discharging through the input end, and the voltage output unit 14 outputs the first voltage value and the second voltage value through the output end.

In the embodiment of the present application, the reference voltage source is configured to output a preset reference voltage to the time-to-voltage conversion unit 12, and a voltage value of the preset reference voltage may be set according to an actual requirement, which is not limited herein.

In practical applications, the reset control signal may be determined according to a specific circuit structure of the voltage reset unit 13, and is not limited herein. For example, as an embodiment of the present application, when the reset signal is a high-level signal, the reset signal may be considered as a discharge signal; when the reset signal is a low level signal, the reset signal may be considered as a discharge stop signal, that is, when the integrating capacitor needs to be discharged, a high level signal is input to the voltage reset unit 13; when it is necessary to stop discharging the integration capacitor, a low level signal is input to the voltage reset unit 13. As another embodiment of the present application, when the reset signal is a low-level signal, the reset signal may be considered as a discharge signal; when the reset signal is a high-level signal, the reset signal may be considered as a discharge stop signal, that is, when the integrating capacitor needs to be discharged, a low-level signal is input to the voltage reset unit 13; when it is necessary to stop discharging the integration capacitor, a high level signal is input to the voltage reset unit 13.

In the embodiment of the present application, the phase discrimination unit 11 performs an exclusive or operation on the reference pulse-per-second signal and the pulse-per-second signal to obtain a voltage conversion control signal as a pulse signal, the pulse width of the pulse signal is the time difference between the rising edge of the reference second pulse signal and the rising edge of the second pulse signal to be measured, the rising edge of the pulse signal is a charging signal for controlling the time-to-voltage conversion unit 12 to charge the integration capacitor included therein, the falling edge of the pulse signal is a charging stop signal for controlling the time-voltage conversion unit 12 to stop charging the integration capacitor included therein, the time-voltage conversion unit 12 controls charging of the integration capacitor based on the pulse signal, therefore, the pulse width of the pulse signal can be linearly converted into a corresponding voltage value, and the voltage output unit 14 reads and outputs the first voltage value after the charging of the integrating capacitor is finished. It should be noted that, because there is usually a residual voltage across the integrating capacitor, the voltage resetting unit 13 controls the discharging of the integrating capacitor, and the voltage output unit 14 reads and outputs the second voltage value of the integrating capacitor after the discharging is finished, where the voltage difference between the first voltage value and the second voltage value is the voltage drop corresponding to the pulse width of the pulse signal. Therefore, the detection personnel can calculate the time difference between the to-be-detected second pulse signal and the reference second pulse signal according to the difference value between the first voltage value and the second voltage value and the preset conversion relation between the voltage value and the time difference.

Fig. 2 is a block diagram of a circuit for measuring a time difference between pulse-per-second signals according to another embodiment of the present application, and for convenience of description, only a portion related to the embodiment of the present application is shown, please refer to fig. 2, and with respect to the embodiment corresponding to fig. 1, in the circuit for measuring a time difference between pulse-per-second signals according to this embodiment, a time-voltage converting unit 12 includes: a constant current source unit 121, a switch control unit 122, and an integrating capacitor C1.

The constant current source unit 121 includes a power source terminal, an input terminal, and an output terminal, the power source terminal of the constant current source unit 121 is connected to the first power source, the input terminal of the constant current source is the input terminal of the time-voltage conversion unit 12, and the output terminal of the constant current source unit 121 is connected to the first terminal of the switch control unit 122.

The switch control unit 122 includes a first terminal, a second terminal, and a controlled terminal, the integrating capacitor C1 includes a first terminal and a second terminal, the second terminal of the switch control unit 122 is connected to the first terminal of the integrating capacitor C1, the controlled terminal of the switch control unit 122 is the controlled terminal of the time-voltage converting unit 12, the first terminal of the integrating capacitor C1 is the voltage control terminal of the time-voltage converting unit 12, and the second terminal of the integrating capacitor C1 is grounded.

In this embodiment, the first power supply provides the power supply voltage VCC to the constant current source unit 121. If the switch control unit 122 detects that the voltage conversion control signal output by the phase detection unit 11 is a charging signal, the switch control unit switches on the power supply path of the constant current source unit 121 to the integration capacitor C1, so that the constant current source unit 121 charges the integration capacitor C1; if the switch control unit 122 detects that the voltage conversion control signal output by the phase detection unit 11 is the charging stop signal, the power supply path of the constant current source unit 121 to the integrating capacitor C1 is disconnected, so that the constant current source unit 121 stops charging the integrating capacitor C1, and at this time, the voltage output unit 14 reads a first voltage value of the first end of the integrating capacitor C1 after the charging is finished.

When it is necessary to discharge the integrating capacitor C1, a discharge signal may be input to the voltage resetting unit 13, and the voltage resetting unit 13 turns on a path between the first end of the integrating capacitor C1 and the ground based on the discharge signal to control the integrating capacitor C1 to discharge; after the integrating capacitor C1 is discharged, a discharge stop signal may be output to the voltage resetting unit 13, the voltage resetting unit 13 opens a path between the first end of the integrating capacitor C1 and the ground based on the discharge stop signal to control the integrating capacitor C1 to stop discharging, and the voltage output unit 14 reads a second voltage value of the first end of the integrating capacitor C1 after the discharging is finished.

Fig. 3 is a specific circuit diagram of a circuit for measuring a time difference between pulse-per-second signals according to an embodiment of the present application, and for convenience of description, only a portion related to the embodiment of the present application is shown, please refer to fig. 3, and with respect to the embodiment corresponding to fig. 1 or fig. 2, in the circuit for measuring a time difference between pulse-per-second signals according to the present embodiment, the phase detection unit 11 includes: and an exclusive or gate U1.

A first input terminal 1PPS _ ref of the xor gate U1 is a reference signal input terminal of the phase detection unit 11, a second input terminal 1PPS _ dut of the xor gate U1 is a signal input terminal to be detected of the phase detection unit 11, and an output terminal of the xor gate U1 is an output terminal of the phase detector unit.

Further, the constant current source unit 121 includes: the circuit comprises a first operational amplifier U2, a first resistor R1, a second resistor R2, a first switch tube Q1, a second switch tube Q2 and a third switch tube Q3.

The non-inverting input terminal of the first operational amplifier U2 is the input terminal of the constant current source unit 121, the inverting input terminal of the first operational amplifier U2 and the low potential terminal of the first switching tube Q1 are commonly connected to the first terminal of the second resistor R2, the second terminal of the second resistor R2 is grounded, the output terminal of the first operational amplifier U2 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to the controlled terminal of the first switching tube Q1, the high potential terminal of the first switching tube Q1, the low potential terminal of the second switching tube Q2 and the controlled terminal of the second switching tube Q2 are commonly connected to the controlled terminal of the third switching tube Q3, the high potential terminal of the second switching tube Q2 and the high potential terminal of the third switching tube Q3 are commonly connected as the power supply terminal of the constant current source unit 121, and the low potential terminal of the third switching tube Q3 is the output terminal of the constant current source unit 121.

Further, the switch control unit 122 includes: a first diode D1 and an in-phase buffer U3.

The positive electrode of the first diode D1 is connected to the output terminal of the in-phase buffer U3 as the first terminal of the switch control unit 122, the negative electrode of the first diode D1 is the second terminal of the switch control unit 122, and the input terminal of the in-phase buffer U3 is the controlled terminal of the switch control unit 122.

By adopting the switch control unit composed of the first diode D1 and the in-phase buffer U3, the embodiment of the application has high control efficiency and low cost.

Further, the voltage reset unit 13 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a fourth switch tube Q4.

A first end of the fourth resistor R4 is a signal input end of the voltage reset unit 13, a second end of the fourth resistor R4 and a first end of the fifth resistor R5 are commonly connected to a controlled end of the fourth switch transistor Q4, a second end of the fifth resistor R5 and a low-potential end of the fourth switch transistor Q4 are commonly connected to ground, a high-potential end of the fourth switch transistor Q4 is connected to a second end of the third resistor R3, and a first end of the third resistor R3 is an output end of the voltage reset unit 13.

Further, the voltage output unit 14 includes: a second operational amplifier U4.

The non-inverting input terminal of the second operational amplifier U4 is the input terminal of the voltage output unit 14, and the inverting input terminal of the second operational amplifier U4 and the output terminal of the second operational amplifier U4 are commonly connected as the output terminal of the voltage output unit 14.

It should be noted that in the embodiment of the present application, the second operational amplifier U4 is a common operational amplifier, and is used as a voltage follower in the circuit.

As an embodiment of the present application, the first switch Q1 may be an NMOS transistor, the second switch Q2 may be a first PNP type transistor, and the third switch Q3 may be a second PNP type transistor.

The gate of the NMOS transistor is the controlled terminal of the first switch transistor Q1, the drain of the NMOS transistor is the high potential terminal of the first switch transistor Q1, the source of the NMOS transistor is the low potential terminal of the first switch transistor Q1, the base of the first PNP transistor is the controlled terminal of the second switch transistor Q2, the emitter of the first PNP transistor is the high potential terminal of the second switch transistor Q2, the collector of the first PNP transistor is the low potential terminal of the second switch transistor Q2, the base of the second PNP transistor is the controlled terminal of the third switch transistor Q3, the emitter of the second PNP transistor is the high potential terminal of the third switch transistor Q3, and the collector of the second PNP transistor is the low potential terminal of the third switch transistor Q3.

In the embodiment of the present application, the characteristics and parameters of the second switching tube Q2 and the third switching tube Q3 are the same.

As an embodiment of the present application, the fourth switching transistor Q4 may be an NPN transistor.

The base electrode of the NPN type triode is the controlled end of the fourth switching tube Q4, the collector electrode of the NPN type triode is the high potential end of the fourth switching tube Q4, and the emitter electrode of the NPN type triode is the low potential end of the fourth switching tube Q4.

The specific operation of the circuit 100 for measuring the time difference of the pulse-per-second signal provided in the present application is described in detail below with reference to fig. 3:

as shown in FIG. 3, the first operational amplifier U2, the first resistor R1, the second resistor R2 and the first switch tube Q1 constitute a first stage constant current source circuit, which is based on the non-inverting input of the first operational amplifier U2The 'virtual short' and 'virtual break' characteristics of the input terminal and the inverting input terminal, and the current flowing through the second resistor R2Since the gate-source leakage current of the first switch tube Q1 is very small, the drain current I flowing through the first switch tube Q1_D＝_R2. The second switch tube Q2 and the third switch tube Q3 form a current mirror circuit, the second switch tube Q2 and the third switch tube Q3 work in an amplifying state, I_D＝I_C+2I_B＝I_C+2I_CB, wherein I_BIs the base current, I, of the second switch tube Q2 and the third switch tube Q3_CBeta is the AC amplification factor of the second switch tube Q2 and the third switch tube Q3, because beta > 1, I is the collector current of the third switch tube Q3_C≈I_D. When the current flowing through the third switching tube Q3 changes due to temperature change, since the current of the left branch of the current mirror completely flows through the second resistor R2 and the current causes the deep negative feedback of the first operational amplifier U2, the first operational amplifier U2 keeps the current flowing through the second resistor R2 unchanged by adjusting the first switching tube Q1, i.e., I_R2Remains unchanged, i.e. the collector current I of the third switching tube Q3_CRemain unchanged. It can be seen that the temperature stability of the circuit can be improved by using the constant current source unit 121 including the first operational amplifier U2, and since the first operational amplifier U2 does not directly participate in the charging process of the integrating capacitor C1, the first operational amplifier U2 can be an ordinary operational amplifier, so that the cost can be reduced.

When the rising edges of the reference pulse-per-second signal and the pulse-per-second signal to be detected do not reach the two input ends of the exclusive-or gate U1, the two input ends of the exclusive-or gate U1 are both at low level, and at the moment, the exclusive-or gate U1 outputs a low level signal; when the rising edges of the reference pulse-per-second signal and the pulse-per-second signal to be measured reach two input ends of the exclusive-or gate U1 at different moments, that is, at a certain moment, one input end of the exclusive-or gate U1 is at a low level, and the other input end of the exclusive-or gate U1 outputs a high level signal; when the rising edges of the reference pulse-per-second signal and the pulse-per-second signal to be detected respectively reach two input ends of the exclusive-or gate U1 at the same time, the two input ends of the exclusive-or gate U1 are both at a high level, and at the moment, the exclusive-or gate outputs a low level signal. It can be seen that the phase discrimination unit 11 outputs a difference pulse signal between the reference pulse-per-second signal and the to-be-detected pulse-per-second signal, and the pulse width of the pulse signal is the time difference between the edges of the reference pulse-per-second signal and the to-be-detected pulse-per-second signal.

Specifically, when the rising edges of the reference pulse per second signal and the pulse per second signal to be measured do not reach the two input ends of the xor gate U1, the xor gate U1 outputs a low level signal, at this time, the output end of the in-phase buffer U3 is turned on to the ground and the on-resistance is extremely low, the voltage drop of the collector current of the third switching tube Q3 passing through the in-phase buffer U3 is extremely small, and the first diode D1 is turned off; when rising edges of a reference pulse per second signal and a pulse per second signal to be measured reach two input ends of the exclusive-or gate U1 at different moments, the exclusive-or gate U1 outputs a high-level signal, at the moment, an output end of the in-phase buffer U3 is closed and is in a high-impedance state, the collector current of the third switching tube Q3 keeps unchanged, but the potential rises, the first diode D1 is conducted, and the current output by the collector of the third switching tube Q3 charges the integrating capacitor C1 through the first diode D1; when the rising edges of the reference pulse-per-second signal and the pulse-per-second signal to be detected reach the input end of the exclusive-or gate U1 at the same time, the exclusive-or gate U1 outputs a low level signal, at the moment, the first diode D1 is cut off, and the integrating capacitor C1 stops charging. At this time, the voltage at the first terminal of the integrating capacitor C1

Wherein t is the time difference between the reference pulse-per-second signal and the pulse-per-second signal to be measured, V₀The voltage remaining in the integrating capacitor C1 is the voltage across the integrating capacitor C1 and the collector current I of the third transistor Q3_CLinearly integrated over time.

Since the second operational amplifier U4 is a voltage follower, when the integrating capacitor C1 stops charging, the first voltage value of the integrating capacitor C1 after the charging is stopped can be read from the output terminal of the second operational amplifier U4, and the first voltage value is V_C1。

After the first voltage value is read, the voltages at the two ends of the integrating capacitor C1 need to be reset, so as to obtain a second voltage value of the original residual voltage at the two ends of the integrating capacitor C1. In the embodiment of the present application, since the fourth switching tube Q4 is an NPN type triode, a high level signal may be input to the first end of the fourth resistor R4, so that the emitter junction of the fourth switching tube Q4 is forward biased, and the fourth switching tube Q4 is turned on, so that the integrating capacitor C1 discharges to ground through the collector-emitter of the third resistor R3 and the fourth switching tube Q4; after the discharging of the integrating capacitor C1 is completed, a low level signal may be input to the first end of the fourth resistor R4 to turn off the fourth switching tube Q4, so as to stop the discharging of the integrating capacitor C1. After the discharge of the integrating capacitor C1 is stopped, a second discharged voltage value of the integrating capacitor C1 after the discharge is stopped can be read from the output terminal of the second operational amplifier U4, and the first voltage value is V₀。

Finally, based on the formula

And calculating the time difference between the pulse-per-second signal to be measured and the reference pulse-per-second signal. Wherein t is the time difference between the pulse-per-second signal to be measured and the reference pulse-per-second signal,

is a first voltage value, V₀Is a second voltage value, C₁Is the capacitance value of the integrating capacitor C1, I_CThe collector current of the third switching tube Q3,

V_refa voltage value, R, of a preset reference voltage outputted from a reference voltage source connected to the time-voltage conversion unit 12₂Is the resistance of the second resistor R2.

It should be noted that, in the embodiment of the present application, the originally remaining voltage of the integrating capacitor C1 is related to the fourth switch Q4. By adopting the NPN type triode as the fourth switching tube Q4, the cut-off leakage current of the switching tube at high temperature can be greatly reduced, and when the charging of the integrating capacitor C1 is stopped, the voltage at the two ends of the integrating capacitor C1 cannot be obviously changed due to the leakage current of the switching tube, so that the stability of the circuit is improved.

The embodiment of the present application further provides an apparatus for measuring a time difference between pulse-per-second signals, as shown in fig. 4, the apparatus 1000 for measuring a time difference between pulse-per-second signals includes: a processing unit 101 and a circuit 100 for measuring the time difference of the pulse per second as described in the above embodiments. Wherein:

the processing unit 101 is connected to an output of the voltage output unit 14.

The processing unit 101 is configured to calculate a time difference between the to-be-measured second pulse signal and the reference second pulse signal based on the first voltage value and the second voltage value.

In the present embodiment, the processing unit 101 is specifically based on a formula

And calculating the time difference between the pulse-per-second signal to be measured and the reference pulse-per-second signal. Wherein t is the time difference between the pulse-per-second signal to be measured and the reference pulse-per-second signal,

is a first voltage value, V₀Is a second voltage value, C₁Is the capacitance value of the integrating capacitor C1, I_CThe collector current of the third switching tube Q3,

V_refa voltage value, R, of a preset reference voltage outputted from a reference voltage source connected to the time-voltage conversion unit 12₂Is the resistance of the second resistor R2.

In practical applications, the processing unit may employ a data processing chip.

The device for measuring the time difference of the pulse per second signal provided by the embodiment can directly output the time difference between the pulse per second signal to be measured and the reference pulse per second signal, manual calculation is not needed, and labor cost is saved.

As can be seen from the above, the present embodiment provides a circuit and an apparatus for measuring the time difference of the pulse-per-second signal, the received reference second pulse signal and the second pulse signal to be detected are subjected to exclusive OR operation through the phase discrimination unit to obtain a voltage conversion control signal, the time-voltage conversion unit controls the charging of the integral capacitor based on the voltage conversion control signal, further converting the time difference between the pulse per second signal to be measured and the reference pulse per second signal into corresponding voltage values, performing discharge control on the integrating capacitor through the voltage reset unit, further, a second voltage value corresponding to the voltage remaining at the two ends of the integrating capacitor is obtained, the first voltage value after the charging of the integrating capacitor and the second voltage value after the discharging are read by the voltage output unit, and then the time difference between the pulse per second signal to be measured and the reference pulse per second signal can be calculated based on the difference value between the first voltage value and the second voltage value. It can be seen that the circuit structure of the application is simple, and the cost is lower.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.