Time server
阅读说明：本技术 时间服务器 (Time server ) 是由 田永亮 于 2019-10-18 设计创作，主要内容包括：本发明涉及一种时间服务器,包括：控制单元、时间接收单元、时间同步单元和以太网单元,时间接收单元用于接收北斗卫星的时间源信号,并上传至控制单元,以太网单元用于将目标区域内的用户设备进行局域网连接,使用户设备断开与外部互联网的通信,时间同步单元用于接收用户设备的时间同步请求信号,并将时间同步请求信号发送至控制单元,控制单元根据时间同步请求信号,以时间源信号为基准,确定时间同步回复信号,并将时间同步回复信号通过时间同步单元发送至用户设备,以使用户设备的实际时间与时间源信号同步,使得在没有与外界互联网交互的保密环境中使用时,也可以通过北斗卫星准确获取时间源信号,有效地拓宽了时间服务器的使用范围。(The invention relates to a time server, comprising: the time synchronization device comprises a control unit, a time receiving unit, a time synchronization unit and an Ethernet unit, wherein the time receiving unit is used for receiving a time source signal of a Beidou satellite and uploading the time source signal to the control unit, the Ethernet unit is used for carrying out local area network connection on user equipment in a target area and enabling the user equipment to disconnect communication with the external Internet, the time synchronization unit is used for receiving a time synchronization request signal of the user equipment and sending the time synchronization request signal to the control unit, the control unit determines a time synchronization reply signal according to the time synchronization request signal by taking the time source signal as a reference and sends the time synchronization reply signal to the user equipment through the time synchronization unit so as to enable the actual time of the user equipment to be synchronous with the time source signal, and the time source signal can be accurately obtained through the Beidou satellite when the time synchronization device is used in a confidential environment without interaction with the external Internet, effectively broadens the application range of the time server.)
1. A time server, comprising: the device comprises a control unit, a time receiving unit, a time synchronization unit and an Ethernet unit;
the time receiving unit is used for receiving a time source signal of the Beidou satellite and uploading the time source signal to the control unit;
the Ethernet unit is used for carrying out local area network connection on user equipment in a target area, so that the user equipment is disconnected from communication with the external Internet;
the time synchronization unit is used for receiving a time synchronization request signal of the user equipment and sending the time synchronization request signal to the control unit;
and the control unit determines a time synchronization reply signal by taking the time source signal as a reference according to the time synchronization request signal, and sends the time synchronization reply signal to the user equipment through the time synchronization unit so as to synchronize the actual time of the user equipment with the time source signal.
2. The time server of claim 1, wherein the ethernet unit comprises a physical layer interface:
the physical layer interface provides an access channel of the ethernet network to enable the ethernet unit to communicate with the control unit.
3. The time server of claim 2, wherein the physical layer interface comprises: a physical coding sublayer, a physical media attachment, a twisted pair physical media sublayer, 10/100BASE-TX coder/decoder, and a twisted pair media access unit;
the physical coding sublayer realizes coding/decoding and convergence functions, so that different media types are transparent to the MAC sublayer;
the physical media accessory provides a common interface, shielding different details of the physical layer;
the 10/100BASE-TX coder/decoder performs parallel-to-serial/serial-to-parallel conversion;
the twisted pair medium access unit realizes signal conversion to a specific medium or reverse conversion;
the twisted-pair physical media sublayer is an interface to a transmission medium;
the physical coding sublayer, the physical media attachment, the twisted pair physical media sublayer, the 10/100BASE-TX coder/decoder and the twisted pair media access unit are in interaction and cooperation, so that the Ethernet unit is communicated with the control unit to realize data interaction.
4. The time server of claim 1, wherein the ethernet unit further comprises a network isolation transformer and a modular jack;
the ethernet unit establishes communication with the user device through the network isolation transformer and the modular jack.
5. The time server of claim 1, wherein the control unit comprises an ethernet controller;
the Ethernet controller provides 10M/100Mbps Ethernet access in a half-duplex mode and/or a full-duplex mode;
in half-duplex mode, the Ethernet controller supports CSMA/CD protocol; in a full duplex mode, the Ethernet controller supports an Ethernet control layer protocol; to enable control of the ethernet unit.
6. The time server of claim 1, wherein the time receiving unit comprises a serial interface circuit;
and the control unit controls the serial interface circuit to receive a time source signal of the Beidou satellite.
7. The time server of claim 6, wherein the serial interface circuit is further configured for program hardening and human-computer interaction to enable development and debugging of the time server.
8. The time server of claim 1, further comprising a joint test action group interface circuit;
the joint test action group interface circuit is used for realizing internal test and simulation debugging of the time server.
9. The time server of claim 1, further comprising a memory interface circuit;
the memory interface circuit comprises a random access memory and a read only memory;
the random access memory is used for constructing a random access memory system, and the read-only memory is used for constructing a code storage system so as to realize expansion of internal storage of the control unit.
10. The time server of claim 1, further comprising a reset circuit;
the reset circuit comprises a first driving gate circuit, a second driving gate circuit, a reset resistor and a reset capacitor;
the first driving gate circuit and the second driving gate circuit are used for improving the resetting capability and enhancing the jitter removal capability;
the reset resistor and the reset capacitor are used to determine a reset time.
Technical Field
The invention relates to the technical field of time service, in particular to a time server.
Background
With the rapid increase of the usage amount of computers and control systems in an automation system, more and more automation devices requiring standard time information are provided, and the requirements on stability and precision are higher and higher. And acquiring the actual time by using the reference clock, and distributing the actual time to the time server of each device. The time server is used as a clock source of the whole automatic system, can time all devices in the whole system, and is the key for realizing time synchronization of the devices in the automatic system.
At present, time servers mostly use time signals of an internet clock source as a reference for time service, but when the time servers are used in a confidential environment without interaction with the external internet, the time service cannot be carried out, and the use of the time servers is limited.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a time server, so as to implement secure use in a secure environment and widen a use range of the time server.
In order to achieve the purpose, the invention adopts the following technical scheme:
a time server, comprising: the device comprises a control unit, a time receiving unit, a time synchronization unit and an Ethernet unit;
the time receiving unit is used for receiving a time source signal of the Beidou satellite and uploading the time source signal to the control unit;
the Ethernet unit is used for carrying out local area network connection on user equipment in a target area, so that the user equipment is disconnected from communication with the external Internet;
the time synchronization unit is used for receiving a time synchronization request signal of the user equipment and sending the time synchronization request signal to the control unit;
and the control unit determines a time synchronization reply signal by taking the time source signal as a reference according to the time synchronization request signal, and sends the time synchronization reply signal to the user equipment through the time synchronization unit so as to synchronize the actual time of the user equipment with the time source signal.
Optionally, the ethernet unit includes a physical layer interface:
the physical layer interface provides an access channel of the ethernet network to enable the ethernet unit to communicate with the control unit.
Optionally, the physical layer interface includes: a physical coding sublayer, a physical media attachment, a twisted pair physical media sublayer, 10/100BASE-TX coder/decoder, and a twisted pair media access unit;
the physical coding sublayer realizes coding/decoding and convergence functions, so that different media types are transparent to the MAC sublayer;
the physical media accessory provides a common interface, shielding different details of the physical layer;
the 10/100BASE-TX coder/decoder performs parallel-to-serial/serial-to-parallel conversion;
the twisted pair medium access unit realizes signal conversion to a specific medium or reverse conversion;
the twisted-pair physical media sublayer is an interface to a transmission medium;
the physical coding sublayer, the physical media attachment, the twisted pair physical media sublayer, the 10/100BASE-TX coder/decoder and the twisted pair media access unit are in interaction and cooperation, so that the Ethernet unit is communicated with the control unit to realize data interaction.
Optionally, the ethernet unit further includes a network isolation transformer and a modular jack;
the ethernet unit establishes communication with the user device through the network isolation transformer and the modular jack.
Optionally, the control unit includes an ethernet controller;
the Ethernet controller provides 10M/100Mbps Ethernet access in a half-duplex mode and/or a full-duplex mode;
in half-duplex mode, the Ethernet controller supports CSMA/CD protocol; in a full duplex mode, the Ethernet controller supports an Ethernet control layer protocol; to enable control of the ethernet unit.
Optionally, the time receiving unit includes a serial interface circuit;
and the control unit controls the serial interface circuit to receive a time source signal of the Beidou satellite.
Optionally, the serial interface circuit is further used for program curing and man-machine interaction, so as to implement development and debugging of the time server.
Optionally, the time server further includes a joint test action group interface circuit;
the joint test action group interface circuit is used for realizing internal test and simulation debugging of the time server.
Optionally, the time server further includes a memory interface circuit;
the memory interface circuit comprises a random access memory and a read only memory;
the random access memory is used for constructing a random access memory system, and the read-only memory is used for constructing a code storage system so as to realize expansion of internal storage of the control unit.
Optionally, the time server further includes a reset circuit;
the reset circuit comprises a first driving gate circuit, a second driving gate circuit, a reset resistor and a reset capacitor;
the first driving gate circuit and the second driving gate circuit are used for improving the resetting capability and enhancing the jitter removal capability;
the reset resistor and the reset capacitor are used to determine a reset time.
A time server of the present invention includes: the system comprises a control unit, a time receiving unit, a time synchronization unit and an Ethernet unit, wherein the time receiving unit is used for receiving a time source signal from a Beidou satellite and uploading the time source signal to the control unit; the control unit determines a time synchronization reply signal by taking a time source signal from a Beidou satellite as a reference according to the time synchronization request signal, and sends the time synchronization reply signal to the user equipment through the time synchronization unit so as to synchronize the actual time of the user equipment with the time source signal and receive the time source signal from the Beidou satellite, so that the time service to the user equipment can not be obtained accurately abroad, the time service to the user equipment is more confidential, when the time service is used in a confidential environment, the problem of time leakage can not occur, and when the time service is used in a confidential environment without interaction with the external Internet, the time source signal from the Beidou satellite can be stably and quickly distributed to the user equipment in the local area network through the local area network connection of the Ethernet unit due to the locality of the Ethernet unit, the time service information can not be leaked, the equipment outside the confidential environment can not acquire accurate time service, and the time server is only used for receiving the time source signal of the Beidou satellite and can not emit signals outwards, so that the time service time confidentiality of the user equipment is good, the time server is suitable for being used in the environment with high confidentiality requirements, and the application range of the time server is widened.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a time server according to an embodiment of the present invention.
Fig. 2 is a pin layout diagram of a control chip of the control unit of fig. 1.
Fig. 3 is a schematic connection diagram of a serial interface circuit of the time receiving unit in fig. 1.
Fig. 4 is a schematic diagram of an operating process of the time server according to an embodiment of the present invention.
Fig. 5 is a schematic circuit connection diagram of the first part of the ethernet unit in fig. 1.
Fig. 6 is a circuit connection schematic of the second part of the ethernet unit in fig. 1.
Fig. 7 is a circuit connection schematic of the first portion of the memory circuit.
Fig. 8 is a circuit connection schematic of the second portion of the memory circuit.
Fig. 9 is a schematic circuit connection diagram of the reset circuit.
Fig. 10 is a schematic structural diagram of a time server according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail below. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without any inventive step, are within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a time server according to an embodiment of the present invention.
As shown in fig. 1, a time server of this embodiment includes: the device comprises a
The
The STM32F407 chip is oriented toward medical, industrial, and consumer applications requiring high integration, high performance, embedded memory and peripherals in as small as 10x10mm packages. STM32F407 provides Cortex at 168MHzTMThe performance of the M4 kernel (with floating point units). At 168MHz frequency, when executed from Flash memory, the STM32F40 microprocessor is able to provide 210DMIPS/566CoreMark performance and implement a FLASH zero wait state with the ART accelerator of Italian semiconductors. DSP instructions and floating point units expand the application range of products. The series of products adopt an intentional semiconductor 90nm process and an ART accelerator, have a dynamic power consumption adjusting function, and can also realize current consumption (@168MHz) as low as 238 μ A/MHz in an operation mode and when being executed from a Flash memory. Compared with the STM32F4x5 series, the STM32F407 product also has an Ethernet MAC10/100 meeting the IEEE1588v2 standard requirements and an 8-14 bit parallel camera interface capable of connecting CMOS camera sensors, 2 USB and OTG (one of which supports HS), a dedicated audio PLL, 2 full duplex I2And S. Up to 15 communication interfaces (including 6 speeds, USART up to 11.25Mb/s, 3 SPI speeds up to 45Mb/s, 3I2C. 2 CAN and 1 SDIO). 2 12-bit DACs, 3 12-bit ADCs with speed 2.4MSPS or 7.2MSPS (interleaved mode). The number of timers is up to 17: 16 and 32 bit timers with frequencies up to 168 MHz. The true random number generator can easily expand the storage capacity by using a flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories, and is based on an analog electronic technology.
Fig. 2 is a pin layout diagram of a control chip of the control unit of fig. 1.
As shown in FIG. 2, STM32F407 has 100 pins in total, QFP packaging is adopted, most IO ports are resistant to 5V (except for analog channels), and SWD and JTAG debugging are supported, wherein only 2 data lines are required for SWD. The IO port can be configured into 8 modes by software: input floating, input pull-up, input pull-down, analog input, open-drain output, push-pull multiplexing function, open-drain multiplexing function. The following are respectively the registers associated with the common configuration of GPIOx: the first one is: the MODER register (Port mode) is a 32-bit register, and each two bits control the mode of one IO port, for a total of 16 groups. 00: inputting; 01: a general output mode; 10: multiplexing functional modes; 11: in the analog mode, the register is normally 0 after reset, i.e., the register is normally in the input state under default conditions. The second method is as follows: the OTYPER register (output type) is a 32-bit register, the upper 16 bits are reserved, the reset value must be kept, and the lower 16 bits control one IO port output type per bit. 0: outputting push-pull; 1: the output is open-drain, the register is only used for the output mode, each bit is 0 after reset, and the default output type is push-pull output. The third is an OSPEEDR register (output speed) 32-bit register, where each two bits control the mode of one IO port, for a total of 16 groups. 00: 2 MHz; 01: 25 MHz; 10: 50 MHz; 11: 100MHz, this register is used only for the output mode, with each bit being 0 after reset. The fourth is a PUPDR register (pull-up and pull-down), a 32-bit register, with one IO port controlled every 2 bits for setting the pull-up and pull-down. 00: no pull-up and pull-down; 01: pulling up; 10: pulling down; 11: and (5) reserving. The schematic introduction of the pin diagram and the register of the control chip in the
Fig. 3 is a schematic connection diagram of a serial interface circuit of the time receiving unit in fig. 1.
Specifically, as shown in fig. 1 to fig. 3, the time service has no doubt effect on the automation equipment, and when the internet exists, the time service can be completely time-synchronized with the internet, and when the time service is used in some confidential environments without the internet, the
The serial interface of the present embodiment uses the RS-232-C standard, which is a very common serial data transmission bus standard. The communication mode is adopted in long distance and short distance along with the development of microcomputer and microcontroller, in short distance communication system, telephone line and MODEM are not used, but end-to-end connection is directly carried out, the interface adopted by RS-232-C standard is 9-core or 25-core D-type plug, taking common 9-core D-type plug as an example, each pin is defined as: DCD is a data carrier pin, RXD is a data receiving pin, TXD is a data sending pin, DTR is a data terminal preparation pin, GND is a grounding pin, DSR is a data equipment preparation pin, RTS is a request sending pin, CTS is a clear sending pin, and RI is a ringing indication pin. To complete the most basic serial communication function, only RXD, TXD and GND are actually needed, but because the high and low level signals defined by the RS-232-C standard are completely different from the high and low level signals defined by the LVTTL circuit of the STM32F407 system, the standard logic "1" of the LVTTL corresponds to the level of 2V to 3.3V, and the standard logic "0" corresponds to the level of 0V to 0.4V, while the RS-232-C standard adopts a negative logic manner, the standard logic "1" corresponds to the level of-5V to-15V, and the standard logic "0" corresponds to the level of +5V to +15V, obviously, the communication between the two needs to be converted by the signal level, which is the level conversion circuit 3232 in this embodiment.
In the system development and debugging stage, the equipment development and the user setting can be completed through the serial port for convenience, and at the moment, the work mainly completed by the serial port comprises program curing, man-machine interaction and the like. When the equipment works normally, the processor receives the time information from the time source through the serial port. The conversion of the two functions can be completed by switching a switch, but the two functions can share one set of serial equipment and work in different states without mutual influence. As shown in fig. 3, the specific interface circuit of the serial port is that MAX3232 communicates with an internal MCU through a TTL level interface, the device 1S1 is configured to set the serial port to operate in a download state or a normal operation state, the device 1S2 is configured to select which of two serial ports of the STM32F407 is in an operation state, and the MAX3232 is configured to provide an RS232 level for serial port input and output.
Fig. 4 is a schematic diagram of a working process of the time server according to the embodiment of the present invention.
As shown in fig. 1-4, the working process of the method includes that a
A time server of the present invention includes: the system comprises a control unit 1, a time receiving unit 2, a time synchronization unit 3 and an Ethernet unit 4, wherein a time source signal from a Beidou satellite is received by the time receiving unit 2 and is uploaded to the control unit 1, the Ethernet unit 4 is used for carrying out local area network connection on user equipment in a target area, so that the user equipment is disconnected from communication with the external Internet, the user equipment can only carry out communication in the local area network, and the time synchronization unit 3 is used for receiving a time synchronization request signal of the user equipment and sending the time synchronization request signal to the control unit 1; the control unit 1 determines a time synchronization reply signal by taking a time source signal from the Beidou satellite as a reference according to the time synchronization request signal, and sends the time synchronization reply signal to the user equipment through the time synchronization unit 3 so as to synchronize the actual time of the user equipment with the time source signal and receive the time source signal from the Beidou satellite, so that the time service to the user equipment can not be obtained accurately abroad, the time service to the user equipment is more secret, when the time synchronization request signal is used in a secret environment, the problem of time leakage can not occur, when the time synchronization request signal is used in a secret environment without interaction with the external Internet, the time source signal from the Beidou satellite can be stably and quickly distributed to the user equipment in the local area network through the local area network connection of the Ethernet unit 4, and due to the local area of the Ethernet unit 4, the time service information can not be leaked, the equipment outside the confidential environment can not acquire accurate time service, and the time server is only used for receiving the time source signal of the Beidou satellite and can not emit signals outwards, so that the time service time confidentiality of the user equipment is good, the time server is suitable for being used in the environment with high confidentiality requirements, and the application range of the time server is widened.
Fig. 5 is a schematic circuit connection diagram of a first part of the ethernet unit of fig. 1, and fig. 6 is a schematic circuit connection diagram of a second part of the ethernet unit of fig. 1.
As shown in fig. 1-6, further, the
An ethernet controller is embedded in the STM32F407, and supports a Media Independent Interface (MII) and a Buffered DMA Interface (BDI), and can provide 10M/100Mbps ethernet access in a half-duplex mode or a full-duplex mode, and in the half-duplex mode, the controller supports a CSMA/CD protocol and in the full-duplex mode, the controller supports an ieee802.3mac control layer protocol. Therefore, the STM32F407 actually includes ethernet MAC control therein, but does not provide a physical layer interface, and needs to be externally connected with a physical layer chip to provide an access channel of the ethernet. In this embodiment, the single 10M/100Mbps high-speed ethernet physical layer interface device is an RTL8201, provides an MII interface and a conventional 7-wire network interface, and can conveniently interface with an STM32F 407.
The function of each pin with respect to RTL8201 is described as follows:
the TXC pin, i.e., 7 pins, functions as a transmit clock: this pin provides a continuous clock signal as TXD [ 3: 0] and TXEN. The TXEN pin, i.e., 2 pin, functions as a transmit enable: this pin indicates the current TXD [ 3: the 4-bit signal at 0] is valid. TXD [ 3: pin 0], i.e. pins 3,4,5,6, functions to send data: when TXEN is active, the MAC sends TXD [ 3: 0]. The RXC pin, i.e., 16 pins, functions to receive a clock: this pin provides a continuous clock signal as RXD [ 3: 0] and RXDV, at 100Mbps, the frequency of RXC is 25MHz, and at 10Mbps, it is 2.5 MHz. The COL pin, i.e.,
table 1:
since the STM32F407 has a MAC controller with an MII interface in the chip, the RTL8201 also provides the MII interface, and the definition of various signals is clear, so that the connection between the RTL8201 and the STM32F407 is simpler. The practical circuit diagram is shown in fig. 6. The MAC controller of STM32F407 can control up to 31 RTL8201 through MDC/MDIO management interface, each RTL8201 should have a different PHY address (which may be from 00001B to 11111B). When the system is reset, the initial state of RTL8201 latch pins 9, 10, 12, 13, 15 is used as the PHY address for communicating with the STM32F407 management interface, but this address cannot be set to 00000B, otherwise RTL8201 enters power down mode. The transmitting end and the receiving end of the signal are connected to a transmission medium through a network isolation transformer and an RJ45 interface, so that all signals are isolated and output, and the anti-interference capability is strong.
Optionally, the time server of this embodiment further includes a joint test action group interface circuit; the joint test action group interface circuit is used for realizing internal test and simulation debugging of the time server. The Joint Test Action Group (JTAG) is an international standard test protocol, and the JTAG circuit is mainly used for testing the inside of a chip and simulating and debugging a system, and provides a simple and convenient method for developing and testing software. The JTAG technique is an embedded debugging technique, and a special Test Access Port (TAP) is packaged in a chip, and a dedicated JTAG Test tool is used to Test internal nodes. Generally, the effectiveness of the developed program can be simply simulated through a JTAG port external simulator, and the system programming can also be used. The JTAG interface generally has two standards, i.e. a
Fig. 7 is a schematic circuit connection diagram of a first portion of the memory circuit, and fig. 8 is a schematic circuit connection diagram of a second portion of the memory circuit.
Further, as shown in fig. 7 and 8, the time server of the present embodiment further includes a memory interface circuit; the memory interface circuit comprises a random access memory and a read-only memory; the random access memory is used to construct a random access memory system and the read only memory is used to construct a code storage system to enable expansion of the internal storage of the
Fig. 9 is a schematic circuit connection diagram of the reset circuit.
As shown in fig. 9, further, on the basis of the above embodiment, the present embodiment further includes: a reset circuit; the reset circuit comprises a first driving gate circuit, a second driving gate circuit, a reset resistor R and a reset capacitor C, wherein the first driving gate circuit and the second driving gate circuit are used for improving the reset capability and the jitter removal capability, and the reset resistor R and the reset capacitor C are used for determining the reset time.
In this embodiment, the reset circuit mainly performs power-on reset of the system and key reset of a user when the system is in operation. The reset circuit may be formed by a simple RC circuit or other relatively complex, but more fully functional, circuit may be used. The reset circuit of the present embodiment is simple in design, and an implementation schematic diagram thereof is shown in fig. 9. When power-on initialization is carried out, when RESET is pressed to be in an off state, the capacitor C is charged through the resistor R, at the moment, the first driving gate circuit IC11A outputs a high RESET level, the second driving gate circuit IC11B outputs a low RESET level, the RESET time is determined by time constants of the resistor and the capacitor, when capacitor charging is completed, the IC11A outputs a low level and the IC11B outputs a high level, when a key is closed, the capacitor starts to discharge, and the two driving gates return to the RESET state. The first driving gate circuit and the second driving gate circuit are provided to improve a load capacity of a reset level and enhance a debouncing capacity of a key so that a reset operation can be performed without fail. The connection relationship of the components is shown in fig. 9, and the detailed description thereof is omitted.
Fig. 10 is a schematic structural diagram of a time server according to an embodiment of the present invention.
A complete structural diagram of the time server in this embodiment is shown in fig. 10, where each part and module are directly described by name, and each name is already described in the above embodiments, so that it is not explained in this embodiment one by one, and they are schematic diagrams of a control part, a memory part, an ethernet unit part, a communication interface part, a JTAG interface circuit part, and a crystal oscillator part.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.