阅读说明：本技术 一种确定GaN cascode器件失效位置的测试分析方法 (Test analysis method for determining failure position of GaN cascode device ) 是由 黄火林 李飞雨 王荣华 刘晨阳 任永硕 梁辉南 于 2019-09-26 设计创作，主要内容包括：本申请公开了一种确定GaN cascode器件失效位置的测试分析方法,属于半导体芯片的可靠性测试领域。技术要点是：对器件的栅极漏电水平Igss进行测量；对器件在关态低漏级电压下的漏级漏电水平Idss@LV进行测量；对器件在关态高漏级电压下的漏电水平Idss@HV进行测量；通过测试结果分析对照表可以确定器件内部的失效位置,同时明确器件失效的原理和模型。有益效果：本发明所述的确定GaN cascode器件失效位置的测试分析方法将传统测试的繁琐流程简化为三步,且无需解封步骤,在保证测试分析结果准确性同时能快速准确地得出器件的失效位置和原理。(The application discloses a test analysis method for determining a failure position of a GaN cascode device, and belongs to the field of reliability test of semiconductor chips. The technical points are as follows: measuring a grid leakage level Igss of the device; measuring the drain leakage level Idss @ LV of the device under the off-state low drain voltage; measuring the leakage level Idss @ HV of the device under the off-state high drain voltage; the failure position in the device can be determined through analyzing the comparison table according to the test result, and the failure principle and model of the device are determined at the same time. Has the advantages that: the test analysis method for determining the failure position of the GaN cascode device simplifies the traditional test complicated process into three steps without a deblocking step, and can quickly and accurately obtain the failure position and principle of the device while ensuring the accuracy of the test analysis result.)

1. A test method for determining failure positions of GaN cascode devices is characterized in that specific failure positions in device structures, device failure principles and device failure models are determined through electrical tests and by combining judgment schemes, and the specific steps are as follows:

s1, measuring a grid leakage level Igss of the device;

s2, measuring the drain leakage level Idss @ LV of the device under the off-state low drain voltage;

s3, measuring the leakage level Idss @ HV of the device under the off-state high drain voltage;

s4, judging the failure position, wherein the judgment scheme is as follows:

when Igss is high, Idss @ LV is high and Idss @ HV is high, a SiMOSFET gate source channel (1), a SiMOSFET gate drain channel (2) and a SiMOSFET gate (6) are short-circuited; or the Si MOSFET grid drain channel (2), the Si MOSFET grid (6), the GaN HEMT grid source channel (3) and the GaN HEMT grid (5) are short-circuited; or the Si MOSFET grid drain channel (2), the Si MOSFET grid (6), the GaN HEMT grid drain channel (4) and the GaN HEMT grid (5) are short-circuited;

when Igss is high, Idss @ LV is low and Idss @ HV is high, the SiMOSFET gate-drain channel (2) and the SiMOSFET gate (6) are short-circuited and the Si MOSFET gate-source channel (1) is open-circuited;

when Igss is high, Idss @ LV is low and Idss @ HV is low, the SiMOSFET gate drain channel (2) and the SiMOSFET gate (6) are short-circuited, and at least one open circuit appears in the Si MOSFET gate source channel (1), the GaN HEMT gate source channel (3) and the GaN HEMT gate drain channel (4);

when Igss is low, Idss @ LV is high and Idss @ HV is high, the short circuit of the GaN HEMT gate source channel (3) and the GaN HEMT gate drain channel (4) causes the short circuit of the Si MOSFET body active region (7) or causes the short circuit of the Si MOSFET gate source channel (1) and the Si MOSFET gate drain channel (2); or the GaN HEMT grid source channel (3) and the GaN HEMT grid (5) are short-circuited; or the GaN HEMT grid drain channel (4) and the GaN HEMT grid (5) are short-circuited;

when Igss is low, Idss @ LV is low, and Idss @ HV is high, a GaN HEMT gate source channel (3) and a GaN HEMT gate drain channel (4) are short-circuited, or a GaN HEMT body is short-circuited with an unintentional doped layer (8);

when Igss is low, Idss @ LV is low, and Idss @ HV is low, the operation is normal; or at least one of the SiMOSFET grid source channel (1), the Si MOSFET grid drain channel (2), the GaN HEMT grid source channel (3), the GaN HEMT grid drain channel (4) and the Si MOSFET grid (6) is broken.

2. The method of claim 1, wherein in step S1, the voltage V is applied to the gate terminal by shorting the drain-source terminals₁Measuring leakage or shorting the two ends of the gate and source, and applying a voltage V to the drain₁Measuring leakage condition, 1V is less than or equal to V₁＜V_th，V_thIs the Si MOS threshold voltage.

3. The method of claim 1, wherein in step S2, the source terminal is grounded, 0 bias is applied to the gate, and a small voltage V is applied to the drain terminal₂Measuring the leakage current at the drain end at the moment, wherein 0V is less than V₂≤20V。

4. The method of claim 1, wherein in step S3, the source terminal is grounded, 0 bias voltage is applied to the gate, and a large voltage is applied to the drain terminalV₃Measuring the leakage current at the drain end, wherein the current is not less than 480V₃≤750V。

Technical Field

The invention belongs to the field of reliability test of semiconductor chips, and particularly relates to a test analysis method for determining a failure position of a GaN cascode device, which can be used for providing a test analysis method for an in-package test of the aged GaN cascode device and determining the specific failure position of the device.

Background

In the application field of power electronic devices, the service life of the device reflects the performance of the device to a certain extent, and semiconductor device manufacturers can perform aging test on the device in the product test stage to evaluate the reliability of the device. The aged devices which fail are tested and analyzed, and failure parts and failure reasons are determined, so that the product can be optimized in design and production in a targeted manner, and therefore, the determination of the failure positions of the devices is particularly important.

For the GaN material, due to polarization and other effects, the two-dimensional electron gas with high electron mobility exists at the interface of AlGaN and GaN, so that the normally-on device has simple preparation process, fewer process steps compared with the normally-off device, higher saturation current density and better stability. However, in the field of device application, the circuit power loss can be greatly reduced by normally-off operation, but because the normally-off HEMT device is complex to prepare and low in saturation current density, the normally-off Si MOSFET and the normally-on HEMT device are commonly adopted for cascade connection, and the cascode structure can not only exert the advantages of the HEMT device during conduction, but also control on-off through the Si MOSFET with mature process and low cost, and becomes a common mode for GaN HEMT device application. The GaN cascode structure is mostly packaged by TO-220, and its internal connection diagram is shown in FIG. 1.

In the conventional test flow, the failure position is determined mainly by two steps of sealing test and unsealing test. And respectively evaluating the high leakage voltage leakage level, the low leakage voltage leakage level, the grid leakage level and the on-resistance level of the device in a sealing test. The decap test can confirm the integrity of each position inside the device after decapsulation, but since the decap process may damage the internal device structure, the failure of the decap test is not completely caused by the aging process. The more accurate position of the failure of the device after deblocking can be observed under a high-power optical microscope, but the accuracy of an observation result after deblocking cannot be completely ensured due to the destructiveness and uncertainty of the deblocking process. And generally, all the steps are required to be completed when the position of the device which fails after aging is determined, so that the method is complicated, the cost and time consumed in batch test are high, the analysis is difficult, and the accuracy is relatively low.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a test analysis method for determining the failure position of a GaN cascode device, which simplifies the complicated process of the traditional test into three steps without a deblocking step, ensures the accuracy of the test analysis result to a certain extent, and can accurately and quickly obtain the failure position of the device.

The technical scheme is as follows:

a test method for determining failure positions of GaN cascode devices determines specific failure positions in device structures and device failure principles and models through electrical tests and in combination with judgment schemes, and comprises the following specific steps:

s1, measuring a grid leakage level Igss of the device;

s2, measuring the drain leakage level Idss @ LV of the device under the off-state low drain voltage;

s3, measuring the leakage level Idss @ HV of the device under the off-state high drain voltage;

s4, judging the failure position, wherein the judgment scheme is as follows:

when Igss is high, Idss @ LV is high, and Idss @ HV is high, a Si MOSFET grid source channel, a Si MOSFET grid drain channel and a SiMOSFET grid are short-circuited; or the Si MOSFET grid drain channel, the Si MOSFET grid, the GaN HEMT grid source channel and the GaN HEMT grid are short-circuited; or the Si MOSFET grid drain channel, the Si MOSFET grid, the GaN HEMT grid drain channel and the GaN HEMT grid are short-circuited;

when Igss is high, Idss @ LV is low and Idss @ HV is high, the Si MOSFET gate-drain channel and the Si MOSFET gate are short-circuited, and the Si MOSFET gate-source channel is open-circuited;

when Igss is high, Idss @ LV is low and Idss @ HV is low, the Si MOSFET grid drain channel and the Si MOSFET grid are short-circuited, and at least one open circuit appears in the Si MOSFET grid source channel, the GaN HEMT grid source channel and the GaN HEMT grid drain channel;

when Igss is low, Idss @ LV is high and Idss @ HV is high, the short circuit of the GaN HEMT gate source channel and the GaN HEMT gate drain channel causes the short circuit of the Si MOSFET body active region, or causes the short circuit of the Si MOSFET gate source channel and the Si MOSFET gate drain channel; or the GaN HEMT grid source channel and the GaN HEMT grid are short-circuited; or the grid leakage channel of the GaN HEMT and the grid short circuit of the GaN HEMT;

when Igss is low, Idss @ LV is low, and Idss @ HV is high, a GaN HEMT gate source channel and a GaN HEMT gate drain channel are short-circuited, or a GaN HEMT body is short-circuited with an unintended doped layer;

when Igss is low, Idss @ LV is low, and Idss @ HV is low, the operation is normal; or at least one open circuit appears in the Si MOSFET grid source channel, the Si MOSFET grid drain channel, the GaN HEMT grid source channel, the GaN HEMT grid drain channel and the Si MOSFET grid.

Further, in step S1, a voltage V is applied to the gate terminal by shorting the drain-source terminals₁Measuring leakage or shorting the two ends of the gate and source, and applying a voltage V to the drain₁Measuring leakage condition, 1V is less than or equal to V₁＜V_th，V_thIs the Si MOS threshold voltage.

Further, in step S2, the source terminal is grounded, a 0 bias voltage is applied to the gate, and a small voltage V is applied to the drain at the same time₂Measuring the leakage current at the drain end at the moment, wherein 0V is less than V₂≤20V。

Further, in step S3, the source terminal is grounded, a 0 bias voltage is applied to the gate, and a large voltage V is applied to the drain at the same time₃Measuring the leakage current at the drain end, wherein the current is not less than 480V₃≤750V。

The test analysis method for determining the failure position of the GaN cascode device has the following beneficial effects:

the test analysis method for determining the failure position of the GaN cascode device simplifies the traditional test complicated process into three steps, does not need a deblocking step, and ensures the accuracy of the test analysis result to a certain extent. The failure position of the device can be accurately obtained under the condition of saving test time and test cost.

Drawings

FIG. 1 is an equivalent circuit diagram of a conventional GaN cascode device;

FIG. 2 is a table for analyzing and comparing the results of the cascade in-package state tests proposed by the present invention;

FIG. 3 is a table comparing the test results of example 4 of the present invention;

the reference numbers in the figures are as follows: the HEMT comprises a 1-Si MOSFET grid source channel, a 2-Si MOSFET grid drain channel, a 3-GaN HEMT grid source channel, a 4-GaN HEMT grid drain channel, a 5-GaN HEMT grid, a 6-Si MOSFET grid, a 7-Si MOSFET body active region and an 8-GaN HEMT body unintended doping layer.

Detailed Description

The following will further describe the test analysis method for determining the failure position of the GaN cascode device with reference to fig. 1-3.