阅读说明：本技术 封装件和形成封装件的方法 (Package and method of forming a package ) 是由 余振华 郭庭豪 蔡豪益 刘重希 于 2019-05-29 设计创作，主要内容包括：一种方法包括将多个功能管芯放置在载体上、将多个伪管芯放置在载体上,将多个功能管芯和多个伪管芯封装在密封剂中,以及在多个功能管芯上形成再分配线并使多个功能管芯互连。再分配线、多个功能管芯、多个伪管芯和密封剂组合形成重建晶圆。多个功能管芯位于重建晶圆的中心区域中,且多个伪管芯位于重建晶圆的外围区域中,同时外围区域环绕中心区域。重建晶圆从载体上脱粘。重建晶圆接合至封装组件,封装组件选自基本上由中介层、封装衬底、印刷电路板、热模块及其组合组成的群组。本发明的实施例还涉及用于减少封装件中的翘曲的伪管芯。本发明的实施例还涉及封装件和形成封装件的方法。(A method includes placing a plurality of functional dies on a carrier, placing a plurality of dummy dies on the carrier, encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant, and forming redistribution lines on and interconnecting the plurality of functional dies. The redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant are combined to form a reconstituted wafer. The plurality of functional dies are located in a central region of the reconstituted wafer, and the plurality of dummy dies are located in a peripheral region of the reconstituted wafer, with the peripheral region surrounding the central region. And debonding the reconstructed wafer from the carrier. The reconstituted wafer is bonded to a package assembly selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof. Embodiments of the invention also relate to a dummy die for reducing warpage in a package. Embodiments of the invention also relate to packages and methods of forming packages.)

1. A method of forming a package, comprising:

placing a plurality of functional die on a carrier;

placing a plurality of dummy dies on the carrier;

encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant;

forming redistribution lines on the plurality of functional dies, the redistribution lines interconnecting the plurality of functional dies, wherein the redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant combine to form a reconstituted wafer, wherein the plurality of functional dies are located in a central region of the reconstituted wafer and the plurality of dummy dies are located in a peripheral region of the reconstituted wafer, while the peripheral region surrounds the central region;

debonding the reconstituted wafer from the carrier; and

the reconstituted wafer is bonded to a package assembly selected from the group consisting of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof.

2. The method of claim 1, wherein the plurality of dummy dies are evenly distributed in the peripheral region.

3. The method of claim 1, wherein the reconstituted wafer bonded to the package assembly has a circular top view shape.

4. The method of claim 1, wherein the reconstituted wafer is unsawn prior to bonding to the package assembly.

5. The method of claim 1, further comprising securing the reconstituted wafer to the package assembly by bolts penetrating the reconstituted wafer.

6. The method of claim 5, wherein the bolt passes through one of the plurality of dummy dies.

7. The method of claim 1, wherein the encapsulating comprises:

dispensing the sealant; and

planarizing the encapsulant, wherein dummy dies of the plurality of dummy dies are polished in the planarizing.

8. The method of claim 1, wherein the plurality of dummy dies are thinner than the plurality of functional dies, and wherein the packaging comprises:

dispensing the sealant; and

planarizing the encapsulant, wherein after the planarizing, the layer of encapsulant covers the plurality of dummy dies.

9. A method of forming a package, comprising:

placing a plurality of logic dies on a carrier;

placing a plurality of input-output (IO) dies on the carrier;

placing a plurality of dummy dies on the carrier, wherein the plurality of dummy dies are distributed around an area where the plurality of logic chips and the plurality of input-output chips are located;

encapsulating the plurality of logic dies, the plurality of input-output dies, and the plurality of dummy dies in an encapsulant;

forming redistribution lines on the plurality of logic dies and the plurality of input-output dies, the redistribution lines electrically coupled to the plurality of logic dies and the plurality of input-output dies to form a reconstituted wafer, the reconstituted wafer comprising the plurality of logic dies, the plurality of input-output dies, the plurality of dummy dies, the encapsulant, and the redistribution lines; and

debonding the reconstituted wafer from the carrier.

10. A package, comprising:

rebuilding a wafer, comprising:

a plurality of dummy die;

a plurality of functional dies located in a central region of the package, wherein the plurality of dummy dies are assigned in alignment with a ring surrounding the plurality of functional dies;

an encapsulant encapsulating the plurality of dummy die and the plurality of functional die therein; and

a plurality of redistribution lines (RDLs) on the plurality of functional dies, wherein the plurality of RDLs interconnect all of the functional dies in the package into an integrated system.

Technical Field

Embodiments of the invention relate to packages and methods of forming packages, and more particularly, to dummy dies for reducing warpage in packages.

Background

In the formation of three-dimensional integrated circuits, the die is typically bonded to a semiconductor wafer. The bonding process typically includes selecting a known good die (top die), and bonding the top die to the bottom chip in the bottom wafer using flip-chip die bonding. Each bottom chip may be bonded to one or more top dies. After bonding, an underfill is dispensed into the space between the top die and the bottom chip, and a molding compound is molded onto the top die and the bottom wafer. After molding of the molding compound, warpage of the package may occur due to shrinkage of the molding compound. Thus, stress may be generated and applied to the bottom wafer and the top die above.

The situation is further exacerbated as the package becomes larger and larger. As package size increases, the distance from one point of the package to another increases, which results in an increase in the distance at which stress can accumulate, resulting in an increase in stress and thus an increase in the occurrence of warpage.

In the formation of conventional packages, a dummy die is used to reduce warpage and the dummy die and functional die are molded together. After forming the RDLs connected to the functional die, the reconstituted wafer is sawed into multiple packages. Dummy dies near the edge of the reconstituted wafer are removed. The resulting package may or may not include a dummy die. The resulting package has the dummy (if any) placed side-by-side with the functional die.

Disclosure of Invention

An embodiment of the present invention provides a method of forming a package, including: placing a plurality of functional die on a carrier; placing a plurality of dummy dies on the carrier; encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant; forming redistribution lines on the plurality of functional dies, the redistribution lines interconnecting the plurality of functional dies, wherein the redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant combine to form a reconstituted wafer, wherein the plurality of functional dies are located in a central region of the reconstituted wafer and the plurality of dummy dies are located in a peripheral region of the reconstituted wafer, while the peripheral region surrounds the central region; debonding the reconstituted wafer from the carrier; and bonding the reconstituted wafer to a package assembly selected from the group consisting of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof.

Another embodiment of the present invention provides a method of forming a package, including: placing a plurality of logic dies on a carrier; placing a plurality of input-output (IO) dies on the carrier; placing a plurality of dummy dies on the carrier, wherein the plurality of dummy dies are distributed around an area where the plurality of logic chips and the plurality of input-output chips are located; encapsulating the plurality of logic dies, the plurality of input-output dies, and the plurality of dummy dies in an encapsulant; forming redistribution lines on the plurality of logic dies and the plurality of input-output dies, the redistribution lines electrically coupled to the plurality of logic dies and the plurality of input-output dies to form a reconstituted wafer, the reconstituted wafer comprising the plurality of logic dies, the plurality of input-output dies, the plurality of dummy dies, the encapsulant, and the redistribution lines; and debonding the reconstituted wafer from the carrier.

Yet another embodiment of the present invention provides a package, including: rebuilding a wafer, comprising: a plurality of dummy die; a plurality of functional dies located in a central region of the package, wherein the plurality of dummy dies are assigned in alignment with a ring surrounding the plurality of functional dies; an encapsulant encapsulating the plurality of dummy die and the plurality of functional die therein; and a plurality of redistribution lines (RDLs) on the plurality of functional dies, wherein the plurality of redistribution lines interconnect all functional dies in the package into an integrated system.

Drawings

Embodiments of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-9 illustrate cross-sectional views of intermediate stages in package formation according to some embodiments.

Fig. 10 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 11A and 11B illustrate top views of a reconstituted wafer including a central region and a peripheral region, according to some embodiments.

Fig. 12A, 12B, and 13-23 are top views of some reconstituted wafers according to some embodiments.

Figure 24 illustrates a process flow for forming a package according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different functions of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated for ease of description. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

A package and method of forming the same are provided according to some embodiments. An intermediate stage of forming a package is shown according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. According to some embodiments of the present disclosure, dummy dies are placed in a peripheral region of the reconstituted wafer, and the dummy dies may surround the functional dies.

Fig. 1-9 illustrate cross-sectional views of intermediate stages in package formation, according to some embodiments of the present disclosure. The processes shown in fig. 1-9 are also reflected schematically in process flow 200, as shown in fig. 24.

Fig. 1 shows a carrier 20 and a release film 22 formed on the carrier 20. The support 20 may be a glass support, a ceramic support, or the like. The carrier 20 may have a circular top view shape and may have the size of a typical silicon wafer. For example, the carrier 20 may have an 8 inch diameter, a 12 inch diameter, and the like. The release film 22 may be formed of a polymer-based material, such as a light-heat-conversion (LTHC) material, which may be removed together with the carrier 20 from an overlying structure to be formed in a subsequent process. According to some embodiments of the present disclosure, the release film 22 is formed of an epoxy-based thermal release material. A Die Attach Film (DAF)24 is formed on the release film 22. DAF 24 is an adhesive film and may be coated or laminated.

Fig. 1 also shows the placement of the package assembly 26 (including 26A and 26B) on the carrier 20. The corresponding process is shown as process 202 in the process flow shown in fig. 24. In accordance with some embodiments of the present disclosure, the package assembly 26 includes a logic die (e.g., a computing die), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die or a Static Random Access Memory (SRAM) die), a photonics die, a package (including an already packaged device die), an Input Output (IO) die, a digital die, an analog die, a surface mount passive device, a die stack such as a High Bandwidth Memory (HBM) block, and so forth. In accordance with some embodiments of the present disclosure, the package assembly 26A is a logic die, and the package assembly 26B is a memory die, an IO die, an Integrated Passive Device (IPD), such as a capacitor (e.g., a multilayer ceramic capacitor (MLCC)), a resistor, an inductor, or the like. Throughout the description, the package components 26 are referred to as functional die 26 because they have an electrical function. The functional die 26 may have about 20mm²To about 900mmmm²The area of (a). Some examples of these areas are 100mm²And about 400mm²。

According to some embodiments of the present disclosure, the functional die 26 includes a semiconductor substrate 28, which may be a silicon substrate, a germanium substrate, or a group III-V compound semiconductor substrate formed of, for example, GaAs, InP, GaN, InGaAs, InAlAs, or the like. Integrated circuit devices (not shown) such as transistors, diodes, resistors, capacitors, inductors, and the like may be formed on the surface or on substrate 28. Interconnect structures, such as metal lines and vias, formed in the dielectric layer are formed on and electrically coupled to the integrated circuit device. Conductive pillars 30 are formed at the surface of the respective functional die 26 and are electrically coupled to the integrated circuit devices in the functional die 26 through interconnect structures. According to some embodiments of the present disclosure, a relatively soft conductive material, such as solder, aluminum, or the like, is used to form conductive layer 33 on conductive post 30. The conductive layer 33 is used to probe the functional die 26 to ensure that the functional die 26 is defect free. Probing may be performed prior to singulating functional die 26 from the respective wafers. Since the conductive layer 33 is softer than the underlying metal stud 30, detection is easier due to improved contact between the probe card of the detection device and the conductive layer 33. A dielectric layer 32 is formed to cover the conductive layer 33 and the metal posts 30. The dielectric layer 32 may be formed of a polymer such as polyimide, Polybenzoxazole (PBO), or the like. The arrangement of the functional die 26 is discussed in detail with reference to fig. 11A, 11B, 12A, 12B, and 13-23.

Fig. 2 shows the placement of dummy die 36 on DAF 24. The corresponding process is shown as process 204 in the process flow shown in fig. 24. Dummy die 36 has no electrical function and is not electrically connected to functional die 26. Dummy die 36 may be formed of a conductive material, such as a metal or metal alloy, a semiconductor material, a dielectric material, or the like. The material of the dummy die 36 may have a Coefficient of Thermal Expansion (CTE) that is less than the CTE of the subsequently dispensed encapsulant 38 (fig. 3). For example, dummy die 36 may be formed of silicon, glass, quartz, copper, SiC, and the like. According to some embodiments of the present disclosure, one or more dummy die 36 are formed entirely of a homogeneous material, which may be selected from the materials described above. According to some embodiments of the present disclosure, the height of the dummy die 36 is less than the height of the functional die 26. According to some embodiments of the present disclosure, the height of dummy die 36 is close to or greater than the height of functional die 26. For example, the dashed lines represent portions of dummy die 36 that may or may not be present. The arrangement of dummy die 36 is discussed in detail with reference to fig. 11A, 11B, 12A, 12B, and 13-23. Dummy die 36 may have a thickness of about 1mm²To about 400mmmm²The area of (a). Some examples of these areas are about 9mm²And about 100mm². The spacing between functional dies 26, the spacing between dummy dies 36, and the spacing between a functional die 26 and an adjacent dummy die 36 may be in the range of about 20 μm to about 15 mm. Some examples of such spacing are about 50um or about 1 mm.

Next, referring to fig. 3, encapsulant 38 is encapsulated (sometimes referred to as molded) over functional die 26 and dummy die 36. The corresponding process is shown as process 206 in the process flow shown in fig. 24. The encapsulant 38 fills gaps between adjacent functional die 26 and dummy die 36 and may also cover the component functional die 26 and dummy die 36. The encapsulant 38 may include a molding compound, a molded underfill, or the like. Encapsulant 38 may include a base material that may be a polymer, an epoxy, and/or a resin and filler particles mixed in the base material. The filler particles may be formed of silica, alumina, or the like, and may have a spherical shape.

In a subsequent step, as also shown in fig. 3, a planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, is performed. The corresponding process is shown as process 208 in the process flow shown in fig. 24. The top surface of encapsulant 38 is lowered by a planarization process until metal stud 30 is exposed. Due to the planarization, the top surface of metal stud 30 is substantially coplanar with the top surface of encapsulant 38. According to some embodiments of the present disclosure, the top surface of dummy die 36 is lower than the top surface of encapsulant 38, so some portion of encapsulant 38 covers dummy die 36 after the planarization process. The conductive layer 33 may be removed in a planarization process (fig. 2), or some of the bottom of the conductive layer 33 may be left to cover the metal posts 30. According to some embodiments of the present disclosure, the top of dummy die 36 is also polished, and after the planarization process, the top surface of dummy die 36 is coplanar with the top surface of encapsulant 38. According to still other embodiments, some dummy dies 36 have surfaces that are coplanar with the top surface of encapsulant 38, and some other dummy dies 36 have top surfaces that are lower than the top surface of encapsulant 38.

Fig. 4-7 illustrate the formation of a front side redistribution line (RDL) and corresponding dielectric layer. Referring to fig. 4, a dielectric layer 40 is formed. The corresponding process is shown as process 210 in the process flow shown in fig. 24. According to some embodiments of the present disclosure, the dielectric layer 40 is formed of a photosensitive polymer such as PBO, polyimide, or the like. According to still other embodiments of the present disclosure, the dielectric layer 40 is formed of an inorganic material such as silicon nitride, silicon oxide, or the like. The dielectric layer 40 is patterned, for example using a photolithographic process, to form openings 42. The metal posts 30 of the functional die 26 are exposed through the openings 42.

An RDL is formed to electrically connect to metal pillar 30. The corresponding process is also shown as process 210 in the process flow shown in fig. 24. According to some embodiments of the present disclosure, as shown in fig. 5, a blanket metal seed layer 44 is formed that includes some portions that extend into the openings 42, as well as some other portions on the dielectric layer 40. The metal seed layer 44 may be formed of titanium, copper, nickel, or the like. According to some embodiments of the present disclosure, the metal seed layer 44 includes a titanium layer and a copper layer on the titanium layer. A plating mask 46 is then formed over the metal seed layer 44 and then patterned to form openings 48 to expose portions of the metal seed layer 44. In addition, the openings 42 are also exposed to openings 48 in the plating mask 46. The plating mask 46 may be formed of photoresist.

Referring to fig. 6, an electroplating process is performed to form the RDL 50. The plating process may include electrochemical plating, electroless plating, and the like. The plating material may include a metal or metal alloy including titanium, copper, nickel, aluminum, tungsten, multilayers thereof, and/or alloys thereof. For example, in the subsequent process, the plating mask 46 is removed in an ashing process. The portion of the blanket copper seed layer 44 previously covered by the plating mask 46 is then etched. The remaining portion of the metal seed layer 44 is considered to be part of the RDL 50. The RDL 50 includes a via portion in the dielectric layer 40 and a trace (line) portion on the dielectric layer 40. The trace portion may include a narrow portion and a wide portion, wherein the wide portion may serve as a metal pad.

Referring to fig. 7, further dielectric layers and corresponding RDL layers are formed according to some embodiments of the present disclosure. The corresponding process is shown as process 212 in the process flow shown in fig. 24. It is understood that the number of dielectric layers and RDL layers may be more or less than shown, depending on design requirements. According to some embodiments of the present disclosure, dielectric layer 52 is formed using a material selected from a group of similar candidate materials for forming dielectric layer 40. The RDL 54 is formed to electrically couple to the functional die 26. RDL 54 may be formed using similar materials and methods for forming RDL 50. Dielectric layers 40 and 52 and RDLs 50 and 54 combine to form an interconnect structure 56 that electrically interconnects all functional die 26 in the package into an integrated system.

Fig. 8 illustrates the formation of an electrical connector 57. According to some embodiments of the present disclosure, the electrical connector 57 is a soldered area. According to still other embodiments, the electrical connector 57 includes a metal post and a solder area above the metal post. Formation of electrical connector 57 may include placing solder balls on the exposed portions of the RDL pads in the top RDL layer and then reflowing the solder balls to form solder areas. According to still other embodiments of the present disclosure, the formation of the electrical connector 57 includes performing an electroplating process to form a metal post and a solder region on the metal post, and then reflowing the electroplated solder region. Throughout the description, the combination of components on the DAF 24 is referred to as a package assembly 58, which may be a reconstituted wafer 58.

According to other embodiments, the package assembly 58 may be a reconstruction panel, a reconstruction substrate, or the like. For example, in a plan view of the package assembly 58, the package assembly 58 may have a circular shape, a rectangular shape, or the like. The package assembly 26 may be arranged as an array in a reconstruction panel or a reconstruction substrate.

In a subsequent process, the reconstituted wafer 58 is unloaded from the carrier 20, for example by projecting light on the release film 22 and letting the light (the laser beam) penetrate the transparent carrier 20. The corresponding process is shown as process 214 in the process flow shown in fig. 24. Thus, the release film 22 is decomposed and the reconstituted wafer 58 is released from the carrier 20. The DAF 24 may be removed in a cleaning process. Thus, the reconstituted wafer 58 is formed as a discrete component.

Fig. 9 illustrates the formation of a package 60 in which a reconstituted wafer 58 is incorporated. The corresponding process is shown as process 216 in the process flow shown in fig. 24. According to some embodiments of the present disclosure, the reconstituted wafer 58 debonded from the carrier 20 is used in the package 60 without being sawed, and all of the functional die 26 and dummy die 36 (as shown in fig. 7) on the carrier 20 remain in the package 60. The reconstituted wafer 58 may also be trimmed, for example, by removing some of the edge portions that do not have functional die 26, dummy die 36, and RDL. For example, fig. 12A shows a trim line 71 in which the outer portion of the reconstituted wafer 58 outside the area marked by the dashed line 71 is trimmed. According to some embodiments, at least some edge portions of the reconstituted wafer 58 are not trimmed. Fig. 9 shows package 60 including two reconstituted wafers 58 as an example. It should be understood that the package may include one or more than two reconstituted wafers. Further, when there is more than one reconstituted wafer 58, the reconstituted wafers 58 may have the same structure or different structures.

According to some embodiments of the present disclosure, a plurality of package assemblies 62 (including, but not limited to, structures of packages, voltage regulator modules, power supply modules (two more specific package types), IPDs, IO connectors (such as sockets for IO of package 60), etc.) are bonded to the reconstituted wafer 58. The reconstituted wafer 58 may be attached to the thermal module 64 by a Thermal Interface Material (TIM) 66. Screws 68, bolts 69 and stiffeners/brackets 70 may be used to secure the reconstituted wafer 58 to the thermal module 64. Holes may be drilled in the reconstituted wafer 58 and thermal module 64 so that bolts 69 may pass through the reconstituted wafer 58 and thermal module 64. The thermal module 64 may include heat sinks, refrigeration plates, and the like. When a cold plate is used, the coolant may be water, oil, or the like.

Fig. 10 illustrates the formation of a package 72 in which a reconstituted wafer 58 is incorporated. According to some embodiments of the present disclosure, the reconstituted wafer 58 is bonded to the package assembly 74 by flip-chip bonding. The package assembly 74 may be a package substrate, interposer, printed circuit board, or the like. The package assembly 62 may be bonded to the package assembly 74. Thermal module 64, reconstruction wafer 58, and package assembly 74 may be secured together by screws 68 and bolts 69. In the structure shown in fig. 9 and 10, the bolts 69 may pass through the package 58 and not through the dummy die 36. Alternatively, some of the bolts 69 may pass through the dummy die 36, as shown in phantom in fig. 9, to indicate its presence or absence. Similarly, the bolts 69 in fig. 10 may or may not pass through the dummy die 36.

Enclosures 60 (FIG. 9) and 72 (FIG. 10) may be High Performance Computing (HPC) enclosures, accelerators for Artificial Intelligence (AI) servers, other performance-demanding computing enclosures for data center applications, or enclosures for servers.

Details in the placement of functional die 26 and dummy die 36 (as discussed in previous embodiments) are discussed with reference to fig. 11A, 11B, 12A, 12B, and 13-23. The reconstituted wafer 58 may be a large wafer, which may have a thickness greater than about 10000mm²The area of (a). The reconstituted wafer 58 may also have an area of about 10000mm²To about 70686mm²Within the range of (1). Fig. 11A and 11B illustrate a central region and a peripheral region of a reconstituted wafer 58, according to some embodiments. Referring to FIG. 11A, a reconstituted wafer58 have a rectangular top view shape. The reconstituted wafer 58 has a center 59. An arrow may be drawn pointing from the center 59 to any edge or corner of the reconstituted wafer 58. If the arrow has a length L1, the arrow meets the outer boundary 61 of the central region 58A. The distance L2 from the center 59 to the boundary 61 of the central region 58A would be L2, and the ratio L2/L1 would be equal to 2/3. The region of the reconstituted wafer 58 outside of the central region 58A is the peripheral region 58B. Thus, the peripheral region 58B surrounds the central region 58A, and the interface between the central region 58A and the peripheral region 58B is shown at 57.

Fig. 11B shows the central region 58A and the peripheral region 58B when the reconstituted wafer has a circular top view shape. The central region 58A has a radius R2, and the reconstituted wafer 58 has a radius R1. The ratio R2/R1 equals 2/3. In fig. 12A and 12B-23, a rectangle or circle 57 is shown, where the area inside the rectangle or circle 57 is the central area of the corresponding reconstituted wafer 58 and the area outside the rectangle or circle 57 is the peripheral area of the corresponding reconstituted wafer 58.

According to some embodiments of the present disclosure, as shown in fig. 12A, 12B, and 13-23, dummy die 36 is primarily placed in a peripheral region 58B of reconstituted wafer 58. Center region 58A may be devoid of dummy die 36 or may include some dummy die 36. The peripheral region 58B may have no functional die 26 or may include some functional die 26. Assume that in a region (either central region 58A or peripheral region 58B), the total top view area of all functional dies 26 is equal to F, and the total top view area of all dummy dies 36 is equal to D. In the central region 58A of the reconstituted wafer 58, the ratio D/F may be in a range between about 0 and about 1, and may be in a range between about 0.25 and about 0.5. In the peripheral region 58B of the reconstituted wafer 58, the ratio F/D may be in a range between about 0 and about 2/3, and may be in a range between about 0.2 and about 2/3. For example, in the peripheral region, the ratio F/D may be in a range between about 0.3 and about 0.5.

It should be understood that the carrier 20 (fig. 8) may have the same (or similar) shape and size as the reconstituted wafer 58. Thus, the carrier 20 may also be divided into the same central and peripheral regions as the reconstituted wafer 58. Before the reconstituted wafer 58 is detached from the carrier 20, the central region 58A and the peripheral region 58B of the reconstituted wafer 58 overlap the central region and the peripheral region, respectively, of the carrier 20.

It should be understood that the reconstituted wafer 58 as shown in fig. 12A, 12B and 13-23 may be a wafer already in the package 60 (fig. 9) or 72 (fig. 10), and therefore, the reconstituted wafer 58 is not singulated and trimmed. Some reconstituted wafers 58 as shown in fig. 12A, 12B and 13-23 may be trimmed (but not singulated), as shown by way of example in fig. 12A, and then used to form packages 60 (fig. 9) or 72 (fig. 10). However, dummy and functional dies will not be trimmed from the reconstituted wafer 58. In the entire embodiment as shown in fig. 12A, 12B, and 13-23, the dummy dies 36 may have the same size as each other or different sizes from each other. Also, the placement of the dummy dies 36 may follow some pattern, such as an array or other repeating pattern, or may be placed in a random layout. In peripheral region 58B, dummy dies 36 may be substantially uniformly distributed and have a substantially uniform density. In fig. 12A, 12B, and 13-23, for example, there may be some voids shown in the peripheral region 58B. These voids may be left for bolted connections or may also be used for placing dummy die. Also, some of the bolts 69 (see fig. 12A as an example) may penetrate the dummy dies 36, and some other bolts 69 may penetrate the reconstituted wafer 58 without penetrating the dummy dies 36. Alternatively, none of the bolts 69 penetrate the dummy die 36. The penetration (or non-penetration) of the bolt 69 through the dummy die 36 is also applicable to the embodiments in fig. 12B and 13-23, although the bolt 69 is not shown in these figures.

In fig. 12A, 12B, and 13-23, die 26A represents a logic die, such as a compute die (e.g., for data computation) or other type of die, such as a passive die, photonics die, etc., and die 26B represents an IO die and may represent other type of die, such as a passive die, photonics die, etc. IO die 26B is used to reconstruct data inputs and outputs between wafer 58 and external components. In accordance with some embodiments of the present disclosure, IO die 26B is placed in alignment with a ring around logic/compute die 26A to minimize routing distance between compute die 26A, thereby improving performance. The multiple logic/compute dies 26A may be identical to one another or may be different from one another. Also, rather than labeling all of the dies in fig. 12A, 12B, and 13-23, it can be found whether the die is a logic/compute die, an IO die, or a dummy die with reference to their respective shading patterns.

Fig. 12A illustrates a top view of a reconstituted wafer 58, wherein reconstituted wafer 58 has a circular top view shape, in accordance with some embodiments. According to some embodiments of the present disclosure, as shown in fig. 12A, the edge of the reconstituted wafer 58 is a full circle. According to an alternative embodiment of the present disclosure, the reconstituted wafer 58 has some trimmed edge portions, where the trimmed portions are marked by dashed lines 71. According to an alternative embodiment, all edge portions of the reconstituted wafer 58 are trimmed without trimming functional or dummy dies. Thus, the new edge of the trimmed reconstituted wafer 58 is closer to the dummy die 36. It should be understood that although trimming of the reconstituted wafer 58 is discussed using fig. 12A as an example, the trimming (or not trimming) scheme discussed above may also be applied to the embodiments in fig. 12B and 13-23. Circle 57 represents the boundary between central region 58A and peripheral region 58B. According to some embodiments of the present disclosure, all dummy dies 36 are located in the peripheral region 58B. Most of the functional die 26 are located in the central region 58A and the remaining functional die 26 are located in the peripheral region 58B.

Fig. 12B illustrates a top view of a reconstituted wafer 58, wherein reconstituted wafer 58 has a rectangular top view shape, according to some embodiments. Rectangle 57 represents the boundary between central region 58A and peripheral region 58B. According to some embodiments of the present disclosure, all dummy dies 36 are located in the peripheral region 58B. Most of the functional die 26 are located in the central region 58A and the remaining functional die 26 are located in the peripheral region 58B. Also, all IO dies 26B may be located in peripheral region 58B.

Fig. 13, 14 and 15 show a reconstituted wafer 58 having a circular top view shape. In fig. 13, all functional dies 26, including all compute dies 26A and IO dies 26B, are located in a central region 58A. Some of the dummy dies extend into the central region 58A while the remainder is located in the peripheral region 58B. In fig. 14, some of the functional die 26 are located in the central region 58A and some of the functional die 26 extend into the peripheral region 58B. Further, according to some embodiments of the present disclosure, some IO dies 26B are located in the central region 58A and some IO dies 26B are located in the peripheral region 58B. All dummy dies 36 are located in peripheral region 58B. In fig. 15, all IO dies 26B are located in peripheral region 58B, some logic/compute dies 26A are located in central region 58A, and the rest are located in peripheral region 58B. All dummy dies 36 are located in peripheral region 58B.

In fig. 12A, 12B, and 13-15, logic/compute die 26A is arranged as an array and no IO die and dummy die are inserted into the array. Fig. 16-23 show dies arranged as a group (GD as shown in fig. 16). The group GD may have the same structure as each other. Each group GD may include a logic/compute die 26A and may or may not include other types of dies, such as IO die 26B, dummy die 36, passive device die, and/or the like. Alternatively, the setup may be considered that the functional die 26 are grouped and dummy die 36 may or may not be inserted to fill the space between the groups. The intra-group spacing between logic/compute dies 26A in the same group may be equal to or less than the inter-group spacing between groups. For example, FIG. 16 shows that the intra-group spacing S1 is less than the inter-group spacing S2. Fig. 17 shows dummy die 36 placed between functional dies 26. In fig. 17, if dummy die 36 is considered to be part of a group, intra-group spacing S1 may be equal to inter-group spacing S2. Alternatively, if dummy die 36 is not considered part of a group, then intra-group spacing S1 will be less than the inter-group spacing, and dummy die 36 is interposed between these groups.

Referring to FIG. 16, each group GD includes a logic/compute die 26A, and does not include IO dies and dummy dies. In the embodiment shown in FIG. 17, each group GD includes a logic/compute die 26A, and no IO die. Fig. 18 and 19 show similar arrangements as in fig. 16 and 17, respectively, except that the reconstituted wafer 58 in fig. 16 and 17 has a circular top view shape, while the reconstituted wafer 58 in fig. 18 and 19 has a rectangular top view shape.

FIG. 20 shows that each group GD includes a logic/compute die 26A and an IO die 26B, and that there are no dummy dies in the group. As an alternative, no dummy die is inserted between the groups. Fig. 21 shows that each group GD includes a logic/compute die 26A, IO die 26B and a dummy die 36, or as an alternative, dummy die 36 is inserted between the group GD if dummy die 36 is not considered part of the group. Fig. 22 and 23 show similar arrangements as in fig. 20 and 21, respectively, except that the reconstituted wafer 58 in fig. 20 and 21 has a circular top view shape, while the reconstituted wafer 58 in fig. 22 and 23 has a rectangular top view shape.

In the above embodiments, some processes and components are discussed in accordance with some embodiments of the present disclosure. Other components and processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages or 3D IC devices. For example, the test structures may include test pads formed in the redistribution layer or on the substrate that allow testing of 3D packages or 3D ICs, using probes and/or probe cards. Verification tests may be performed on the intermediate structure as well as the final structure. In addition, the disclosed structures and methods may be used in conjunction with testing methods that include intermediate verification of known good die to improve yield and reduce cost.

The disclosed embodiments of the invention have some advantageous features. By arranging dummy die in the reconstituted wafer, space that would otherwise be occupied by an encapsulant, such as a molding compound, is occupied by the dummy die. Since the CTE of the dummy die is closer to the CTE of the functional die than the encapsulant, the addition of the dummy die can reduce stress and warpage of the reconstituted wafer. Furthermore, the dummy die includes at least some portions in the peripheral area surrounding the functional die, and adding the dummy die in the peripheral area may improve yield in the packaging process, since the reconstituted wafer may have warpage, which causes edge portions of the reconstituted wafer to lose focus during photolithography. Occupying the edge portion of the reconstituted wafer with dummy dies not only reduces warpage, but also leaves some unused de-focused edge portion, thus improving yield.

According to some embodiments of the present disclosure, a method includes placing a plurality of functional dies on a carrier, placing a plurality of dummy dies on the carrier, encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant, and forming and interconnecting redistribution lines on the plurality of functional dies; wherein the redistribution line, the plurality of functional dies, the plurality of dummy dies, and the encapsulant combine to form a reconstituted wafer, wherein the plurality of functional dies are located in a central region of the reconstituted wafer and the plurality of dummy dies are located in a peripheral region of the reconstituted wafer while the peripheral region surrounds the central region; debonding the reconstituted wafer from the carrier, and bonding the reconstituted wafer to a package assembly selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof. In one embodiment, the plurality of dummy dies are substantially evenly distributed in the peripheral region. In one embodiment, the reconstituted wafer bonded to the package assembly has a circular top view shape. In one embodiment, the reconstituted wafer is unsawn prior to bonding to the package assembly. In one embodiment, the method further comprises securing the reconstituted wafer to the package assembly by bolts penetrating the reconstituted wafer. In one embodiment, the bolt passes through one of the plurality of dummy dies. In one embodiment, the packaging includes dispensing the encapsulant and planarizing the encapsulant, wherein dummy dies of the plurality of dummy dies are polished in the planarizing. In one embodiment, the plurality of dummy dies are thinner than the plurality of functional dies, and the packaging includes dispensing the encapsulant and planarizing the encapsulant, wherein after the planarizing, the encapsulant layer covers the plurality of dummy dies. In one embodiment, the plurality of functional die are placed in a plurality of groups, with an intra-group spacing between die in the same group being less than an inter-group spacing between adjacent ones of the plurality of groups. In one embodiment, the method further comprises placing an additional plurality of dummy dies between the plurality of groups. In one embodiment, the dies in one of the plurality of groups include a compute die and an input-output die. In one embodiment, the method further comprises placing a plurality of input-output dies around the plurality of functional dies.

According to some embodiments of the present disclosure, a method includes placing a plurality of logic dies on a carrier, placing a plurality of IO dies on the carrier, placing a plurality of dummy dies on the carrier, wherein the plurality of dummy dies are distributed around an area where the plurality of logic chips and the plurality of IO chips are located; encapsulating the plurality of logic dies, the plurality of IO dies, and the plurality of dummy dies in an encapsulant; forming redistribution lines on the plurality of logic dies and the plurality of IO dies and electrically coupled to form a reconstituted wafer comprising the plurality of logic dies, the plurality of IO dies, the plurality of dummy dies, the encapsulant, and the redistribution lines; and debonding the reconstituted wafer from the carrier. In one embodiment, the method further includes bonding the reconstituted wafer to a package assembly without sawing the reconstituted wafer. In one embodiment, the method further comprises inserting a dummy die between two of the plurality of logic dies prior to the packaging. In one embodiment, the plurality of logic dies are placed as part of a plurality of groups, with the intra-group spacing between dies in the same group being less than the inter-group spacing between adjacent ones of the plurality of groups. In one embodiment, the plurality of IO dies are placed as part of the plurality of groups.

According to some embodiments of the present disclosure, a package includes a reconstituted wafer including a plurality of dummy dies, a plurality of functional dies located in a central region of the package, wherein the plurality of dummy dies are allocated in alignment with a ring surrounding the plurality of functional dies; an encapsulant in which the plurality of dummy dies and the plurality of functional dies are encapsulated; and a plurality of RDLs on the plurality of functional dies, wherein the plurality of RDLs interconnect all of the functional dies in the package into an integrated system. In one embodiment, the package further comprises a package component bonded to the reconstituted wafer, wherein the package component is selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof. In one embodiment, the reconstituted wafer bonded to the package assembly has a circular top view shape.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the described embodiments of the invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.