阅读说明：本技术 半导体结构与其制作工艺 (Semiconductor structure and manufacturing process thereof ) 是由 欧阳颖洁 夏志良 苏睿 王启光 于 2019-09-06 设计创作，主要内容包括：本申请提供了一种半导体结构与其制作工艺。该半导体结构的制作工艺,包括：形成包括沟道孔的基底结构；在沟道孔中形成预备电荷捕获层；对预备电荷捕获层进行预定处理,使得预备电荷捕获层形成电荷捕获层,电荷捕获层的陷阱密度大于预备电荷捕获层的陷阱密度。上述的制作方法中,首先在沟道中形成预备电荷捕获层,然后对该预备电荷捕获层进行预定处理,预备电荷捕获层中的部分材料形成陷阱,从而使得形成的电荷捕获层中的陷阱数量大于预备电荷捕获层中的陷阱的数量。该制作方法形成电荷捕获层中的陷阱的数量较多,缓解了现有技术中的电荷捕获层中的陷阱的数量较少的问题,保证了器件的内存窗口相对较大,进而保证了器件具有良好的性能。(The application provides a semiconductor structure and a manufacturing process thereof. The manufacturing process of the semiconductor structure comprises the following steps: forming a base structure including a channel hole; forming a preliminary charge trap layer in the channel hole; and performing predetermined processing on the preliminary charge trapping layer so that the preliminary charge trapping layer forms a charge trapping layer having a trap density greater than that of the preliminary charge trapping layer. In the manufacturing method, the preliminary charge trapping layer is first formed in the channel, and then the preliminary charge trapping layer is subjected to predetermined processing, and a part of the material in the preliminary charge trapping layer forms traps, so that the number of traps in the formed charge trapping layer is larger than that in the preliminary charge trapping layer. The manufacturing method has the advantages that the number of traps in the charge trapping layer is large, the problem that the number of traps in the charge trapping layer is small in the prior art is solved, the memory window of the device is relatively large, and the device is guaranteed to have good performance.)

1. A process for fabricating a semiconductor structure, comprising:

forming a substrate structure;

forming a preliminary charge trapping layer on at least a portion of the base structure;

and performing predetermined processing on the preliminary charge trapping layer so that the preliminary charge trapping layer forms a charge trapping layer having a trap density greater than that of the preliminary charge trapping layer.

2. The production process according to claim 1, wherein the material of the preliminary charge trap layer includes a base material and a dopant material that decomposes into a gas or into a gas and a solid substance composed of at least one predetermined element during the predetermined treatment, the predetermined element being an element in the base material.

3. The process of claim 2, wherein the dopant material comprises at least one of ozone, silicic acid, and polyethylene glycol.

4. The process of claim 2, wherein the base material comprises at least one of a silicon oxy-compound, a silicon nitrogen compound, a silicon oxy-nitrogen compound, and a high-K dielectric.

5. The process of claim 1, wherein the pre-treating the preliminary charge trapping layer comprises:

performing a heat treatment on the preliminary charge trapping layer, and/or performing an ultraviolet light treatment on the preliminary charge trapping layer.

6. The fabrication process according to any one of claims 1 to 5, further comprising:

forming a charge blocking layer and a charge tunneling layer on the substrate structure, wherein the charge trapping layer is located between the charge blocking layer and the charge tunneling layer.

7. The process of claim 6, wherein the base structure comprises a channel hole, and the charge blocking layer, the charge trapping layer, and the charge tunneling layer are sequentially formed at least on a sidewall and a bottom of the channel hole.

8. The process of claim 7, wherein forming the base structure comprises:

providing a substrate;

forming a preparation stacking structure on the substrate, wherein the preparation stacking structure comprises first insulating medium layers and sacrificial layers which are alternately arranged;

forming the channel hole exposing the substrate in the preliminary stacked structure;

and forming an epitaxial layer in the channel hole, wherein the epitaxial layer penetrates through the sacrificial layer closest to the substrate and the two first insulating medium layers closest to the substrate.

9. The process of claim 8, wherein after forming the charge trapping layer, the process further comprises:

forming a first groove in the charge blocking layer, the charge trapping layer and the charge tunneling layer at the bottom of the channel hole, wherein the first groove exposes a part of the surface of the epitaxial layer;

forming a channel layer and a second insulating medium layer in the channel hole, wherein the channel layer is surrounded by the charge tunneling layer, and the top surfaces of the channel layer and the second insulating medium layer are lower than the opening of the channel hole;

and forming a drain contact structure on the channel layer and the second insulating medium layer, wherein the drain contact structure is embedded into the channel hole.

10. A semiconductor structure, comprising:

a base structure;

a charge trapping layer formed by a preliminary charge trapping layer through a predetermined process, and having a trap density larger than that of the preliminary charge trapping layer.

11. The semiconductor structure of claim 10, wherein the material of the preliminary charge trapping layer comprises a base material and a dopant material that decomposes into a gas or into a gas and a solid substance composed of at least one predetermined element during the predetermined process, the predetermined element being an element in the base material.

12. The semiconductor structure of claim 11, wherein the dopant material comprises at least one of ozone, silicic acid, and polyethylene glycol.

13. The semiconductor structure of claim 11, wherein the base material comprises at least one of a silicon oxy compound, a silicon nitrogen compound, a silicon oxy-nitride compound, and a high-K dielectric.

14. The semiconductor structure of claim 10, wherein the predetermined process comprises at least one of: heat treatment and ultraviolet light treatment.

15. The semiconductor structure of any one of claims 10 to 14, further comprising a charge blocking layer and a charge tunneling layer formed on the base structure, wherein the charge trapping layer is located between the charge blocking layer and the charge tunneling layer.

16. The semiconductor structure of claim 15, wherein the base structure comprises a channel hole, and wherein the charge blocking layer, the charge trapping layer, and the charge tunneling layer are at least on sidewalls and a bottom of the channel hole and are sequentially distributed in a direction away from the channel hole.

17. The semiconductor structure of claim 16, wherein the base structure comprises:

a substrate;

the stacked structure is positioned on the surface of the substrate and comprises first insulating medium layers and metal gates which are alternately arranged, and the stacked structure is internally provided with the channel hole which enables the substrate to be exposed;

and the epitaxial layer is positioned in the channel hole and penetrates through one metal gate closest to the substrate and the two first insulating medium layers closest to the substrate.

18. The semiconductor structure of claim 17, wherein the charge blocking layer, the charge trapping layer, and the charge tunneling layer at the bottom of the channel hole have a first recess therein, the first recess abutting a portion of a surface of the epitaxial layer, the semiconductor structure further comprising:

the channel layer is positioned in the rest channel holes and the first groove;

a second insulating medium layer on a surface of the channel layer, a top surface of the channel layer and the second insulating medium layer being lower than the opening of the channel hole;

and the drain electrode contact structure is embedded into the channel hole and is positioned on the surface of the channel layer and the surface of the second insulating medium layer.

Technical Field

The application relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing process thereof.

Background

Disclosure of Invention

The present disclosure provides a semiconductor structure and a fabrication process thereof, so as to solve the problem of low density of traps in a charge trapping layer in a semiconductor device in the prior art.

In order to achieve the above object, according to one aspect of the present application, there is provided a process for manufacturing a semiconductor structure, including: forming a substrate structure; forming a preliminary charge trapping layer on at least a portion of the base structure; and performing predetermined processing on the preliminary charge trapping layer so that the preliminary charge trapping layer forms a charge trapping layer having a trap density greater than that of the preliminary charge trapping layer.

Further, the material of the preliminary charge trap layer includes a base material and a dopant material that decomposes into a gas or into a gas and a solid substance composed of at least one predetermined element that is an element in the base material during the predetermined process.

Further, the doping material includes at least one of ozone, silicic acid, and polyethylene glycol.

Further, the base material includes at least one of a silicon oxy compound, a silicon nitrogen compound, a silicon oxy-nitrogen compound, and a high-K dielectric.

Further, the performing of the predetermined process on the preliminary charge trap layer includes: performing a heat treatment on the preliminary charge trapping layer, and/or performing an ultraviolet light treatment on the preliminary charge trapping layer.

Further, the manufacturing process further comprises: forming a charge blocking layer and a charge tunneling layer on the substrate structure, wherein the charge trapping layer is located between the charge blocking layer and the charge tunneling layer.

Further, the substrate structure comprises a channel hole, and the charge blocking layer, the charge trapping layer and the charge tunneling layer are sequentially formed and at least located on the side wall and the bottom of the channel hole.

Further, the process of forming the base structure includes: providing a substrate; forming a preparation stacking structure on the substrate, wherein the preparation stacking structure comprises first insulating medium layers and sacrificial layers which are alternately arranged; forming the channel hole exposing the substrate in the preliminary stacked structure; and forming an epitaxial layer in the channel hole, wherein the epitaxial layer penetrates through the sacrificial layer closest to the substrate and the two first insulating medium layers closest to the substrate.

Further, after forming the charge trapping layer, the fabrication process further includes: forming a first groove in the charge blocking layer, the charge trapping layer and the charge tunneling layer at the bottom of the channel hole, wherein the first groove exposes a part of the surface of the epitaxial layer; forming a channel layer and a second insulating medium layer in the channel hole, wherein the channel layer is surrounded by the charge tunneling layer, and the top surfaces of the channel layer and the second insulating medium layer are lower than the opening of the channel hole; and forming a drain contact structure on the channel layer and the second insulating medium layer, wherein the drain contact structure is embedded into the channel hole.

In order to achieve the above object, according to one aspect of the present application, there is provided a semiconductor structure including: a base structure; a charge trapping layer formed by a preliminary charge trapping layer through a predetermined process, and having a trap density larger than that of the preliminary charge trapping layer.

Further, the material of the preliminary charge trap layer includes a base material and a dopant material that decomposes into a gas or into a gas and a solid substance composed of at least one predetermined element that is an element in the base material during the predetermined process.

Further, the doping material includes at least one of ozone, silicic acid, and polyethylene glycol.

Further, the base material includes at least one of a silicon oxy compound, a silicon nitrogen compound, a silicon oxy-nitrogen compound, and a high-K dielectric.

Further, the predetermined processing includes at least one of: heat treatment and ultraviolet light treatment.

Further, the semiconductor structure further comprises a charge blocking layer and a charge tunneling layer formed on the base structure, wherein the charge trapping layer is located between the charge blocking layer and the charge tunneling layer.

Further, the substrate structure includes a channel hole, and the charge blocking layer, the charge trapping layer, and the charge tunneling layer are at least located on a sidewall and a bottom of the channel hole and are sequentially distributed along a direction away from the channel hole.

Further, the base structure includes: a substrate; the stacked structure is positioned on the surface of the substrate and comprises first insulating medium layers and metal gates which are alternately arranged, and the stacked structure is internally provided with the channel hole which enables the substrate to be exposed; and the epitaxial layer is positioned in the channel hole and penetrates through the sacrificial layer closest to the substrate and the two first insulating medium layers closest to the substrate.

Further, the charge blocking layer, the charge trapping layer and the charge tunneling layer at the bottom of the channel hole have a first groove therein, the first groove abutting against a portion of the surface of the epitaxial layer, and the semiconductor structure further includes: the channel layer is positioned in the rest channel holes and the first groove; a second insulating medium layer on a surface of the channel layer, a top surface of the channel layer and the second insulating medium layer being lower than the opening of the channel hole; and the drain electrode contact structure is embedded into the channel hole and is positioned on the surface of the channel layer and the surface of the second insulating medium layer.

By applying the technical scheme of the application, in the manufacturing method, firstly, the preliminary charge trapping layer is formed on part of the structure of the substrate, then, the preliminary charge trapping layer is subjected to predetermined processing, and the traps are formed on part of materials in the preliminary charge trapping layer, so that the number of the traps in the formed charge trapping layer is larger than that of the traps in the preliminary charge trapping layer. The manufacturing method has the advantages that the number of traps in the charge trapping layer is large, the problem that the number of traps in the charge trapping layer is small in the prior art is solved, the memory window of the device is relatively large, and the device is guaranteed to have good performance.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

FIG. 1 shows a schematic view of a structure including a substrate, a sacrificial layer, and a first insulating dielectric layer according to the present application;

FIG. 2 is a schematic diagram illustrating a structure including a channel hole formed after etching to remove portions of the structure of FIG. 1;

FIG. 3 shows a schematic diagram of the structure after an epitaxial layer is formed in the structure of FIG. 2;

FIG. 4 shows a schematic view of the structure after forming a charge blocking layer in the channel hole of FIG. 3;

FIG. 5 shows a schematic diagram of the structure after formation of a preliminary charge trapping layer in the structure of FIG. 4;

FIG. 6 shows a schematic of the structure resulting from processing the preliminary charge trapping layer of FIG. 5;

FIG. 7 is a schematic diagram illustrating the structure of FIG. 6 after a charge tunneling layer is formed thereon;

FIG. 8 is a schematic diagram showing the structure of FIG. 7 after etching to remove portions of the structure to form a first recess;

fig. 9 is a schematic view showing a structure after a preliminary channel layer is formed on the structure of fig. 8;

FIG. 10 is a schematic view showing a structure of a channel layer formed after removing a portion of the preliminary channel layer of FIG. 9;

FIG. 11 is a schematic view showing the structure after forming a second insulating dielectric layer in the remaining channel hole of FIG. 10;

FIG. 12 shows a schematic view of the structure after an epitaxial layer is formed in the structure of FIG. 11;

FIG. 13 shows a schematic diagram of the structure after removal of the sacrificial layer of FIG. 12;

fig. 14 is a schematic view showing the structure of fig. 13 after a third insulating dielectric layer is formed on the exposed surface of the epitaxial layer;

FIG. 15 is a schematic diagram showing the structure of FIG. 14 after filling the metal material in the gap to form a metal gate; and

fig. 16 shows a band gap diagram of a part of the structure in the semiconductor structure of the embodiment.

Wherein the figures include the following reference numerals:

10. a substrate; 11. a channel hole; 12. a second groove; 20. a first insulating dielectric layer; 30. a sacrificial layer; 40. an epitaxial layer; 41. a first groove; 50. a charge blocking layer; 60. a charge trapping layer; 61. preparing a charge trapping layer; 70. a charge tunneling layer; 80. a channel layer; 81. preparing a channel layer; 90. a second insulating dielectric layer; 100. a drain contact structure; 110. a third insulating medium layer; 120. and a metal gate.

Detailed Description

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background, the present application provides a semiconductor structure and a method for fabricating the same to solve the above technical problems by using a smaller number of traps in a charge trapping layer in the prior art, so that a memory window of a memory is smaller.

In an exemplary embodiment of the present application, a method for fabricating a semiconductor structure is provided, the method comprising: forming a substrate structure; forming a preliminary charge trapping layer on at least a portion of the substrate structure; and performing predetermined processing on the preliminary charge trapping layer so that the preliminary charge trapping layer forms a charge trapping layer having a trap density higher than that of the preliminary charge trapping layer.

In the manufacturing method, a preliminary charge trapping layer is first formed on a part of the structure of the substrate, and then the preliminary charge trapping layer is subjected to predetermined processing, and traps are formed on a part of the material in the preliminary charge trapping layer, so that the number of traps in the formed charge trapping layer is larger than that in the preliminary charge trapping layer. The manufacturing method has the advantages that the number of traps in the charge trapping layer is large, the problem that the number of traps in the charge trapping layer is small in the prior art is solved, the memory window of the device is relatively large, and the device is guaranteed to have good performance.

The material of the preliminary charge trapping layer in the present application comprises a base material and a dopant material, the dopant material being decomposed into a gas or into a gas and a solid substance composed of at least one predetermined element during the predetermined process, the predetermined element being an element in the base material, so that the substance after the decomposition of the dopant material does not affect the trapping performance of the charge trapping layer. That is, the dopant material is decomposed into gas during a predetermined process, and the gas escapes, so that the surface area of the charge trap layer is increased, thereby increasing the number of traps; or the doping material is decomposed into a solid substance consisting of a gas and at least one predetermined element during a predetermined process, so that the surface area of the charge trapping layer is increased, thereby increasing the number of traps, and the remaining solid substance including at least one of nitrogen, oxygen, and silicon does not affect the trapping performance of the charge trapping layer.

The doping material in the present application can be any material in the prior art that meets the above requirements, and can be selected by those skilled in the art according to the actual situation, and in a specific embodiment in the present application, the doping material includes at least one of ozone, silicic acid, and polyethylene glycol, etc. These materials can further ensure more traps in the subsequently formed charge trapping layer.

The matrix material of the present application may be other materials that can form a charge trapping layer in the prior art, and those skilled in the art can select a suitable material to form the matrix material of the present application according to actual situations.

In a specific embodiment of the present application, the base material includes at least one of a silicon oxynitride compound, a silicon nitride compound, a silicon oxynitride compound, and a high-K dielectric. Wherein, for example, the high-K material can be HfO₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al₂O₃. Using such a base materialThe trap density in the prepared charge trapping layer can be further ensured to be larger, and the trap density in the finally formed charge trapping layer is further ensured to be larger.

In order to further ensure that a uniform and dense preliminary charge trapping layer is formed, thereby ensuring that the semiconductor device has good performance, in one embodiment of the present application, forming the preliminary charge trapping layer in the trench hole includes: the preliminary charge trapping Layer is deposited in the channel hole by Atomic Layer Deposition (ALD).

The manner of performing the predetermined treatment on the preliminary charge trapping layer in the present application may be any method that can release part of the substance in the doping material to form more traps, and a person skilled in the art may select a suitable predetermined treatment manner according to the actual situation, and specifically may select a corresponding predetermined treatment manner according to the doping material.

In a specific embodiment of the present application, the performing the predetermined process on the preliminary charge trapping layer includes: and (b) performing a heat treatment on the preliminary charge trapping layer, and/or performing an ultraviolet light treatment on the preliminary charge trapping layer. That is, the predetermined processing procedure may only include the step of performing the thermal treatment on the preliminary charge trapping layer, may only include the step of performing the ultraviolet light treatment on the preliminary charge trapping layer, and may also include both of the predetermined processing manners. The skilled person can select a suitable predetermined processing manner according to the actual situation. For example, when the doping material is ozone, the treatment mode of ultraviolet light can be selected; in the case where the doping material is silicic acid, a heat treatment may be employed.

It should be noted that the semiconductor structure in the present application may be any memory structure including a charge trapping layer, and may be a two-dimensional memory structure or a three-dimensional memory structure, and those skilled in the art can apply the manufacturing process of the present application to the manufacturing process of any memory structure including a charge trapping layer according to practical situations.

In order to limit the charges in the charge trapping layer and prevent the charges from escaping, the manufacturing process of the present application further includes forming a charge blocking layer and a charge tunneling layer on the substrate structure, wherein the charge trapping layer is located between the charge blocking layer and the charge tunneling layer. The formation locations of the charge blocking layer and the charge tunneling are different for different memory devices.

The semiconductor structure of the present application may be a two-dimensional memory device in which a charge tunneling layer is formed on a surface of a conductive channel layer on a substrate structure, a charge trapping layer is formed on a surface of the charge tunneling layer away from the conductive channel layer, and a charge blocking layer is formed on a surface of the charge trapping layer away from the charge tunneling layer, that is, after a predetermined process, the charge blocking layer is formed.

In another embodiment of the present invention, the semiconductor structure is a three-dimensional device, the base structure includes a channel hole 11, as shown in fig. 3, the charge blocking layer 50, the charge trapping layer 60 and the charge tunneling layer 70 are sequentially formed at least on the sidewall and the bottom of the channel hole 11, as shown in fig. 7, that is, after the charge trapping layer 60 is formed through a predetermined process, the charge tunneling layer 70 is formed.

The formation process of the substrate structure including the channel hole of the present application may be any feasible method, and a person skilled in the art may select a suitable method to form the substrate structure including the channel hole 11 according to practical situations, and in a specific embodiment of the present application, the forming of the substrate structure includes: providing a substrate 10; forming a preliminary stack structure on the substrate 10, wherein the preliminary stack structure includes a first insulating dielectric layer 20 and a sacrificial layer 30 alternately arranged to form a structure as shown in fig. 1, and in fig. 1, the first insulating dielectric layer 20 is in contact with the substrate 10; forming the channel hole 11 exposing the substrate 10 in the preliminary stacked structure, and immediately etching away a portion of each of the first insulating dielectric layers 20, a portion of each of the sacrificial layers 30, and a portion of the substrate 10 to expose a portion of the substrate 10, thereby forming the channel hole 11 shown in fig. 2; an epitaxial layer 40 is formed in the channel hole 11, the epitaxial layer 40 passes through one of the sacrificial layers 30 closest to the substrate 10 and two of the first insulating medium layers 20 closest to the substrate 10, as shown in fig. 3, that is, a distance between a surface of the epitaxial layer 40 remote from the substrate 10 and the substrate 10 is H1, a distance between a surface of the first sacrificial layer 30 remote from the substrate 10 and the substrate 10 is H2, H1> H2, and the first sacrificial layer 30 is the sacrificial layer 30 having the smallest distance from the substrate 10.

The steps in the above embodiments may be implemented in a feasible manner in the prior art, and the corresponding first insulating dielectric layer and the corresponding sacrificial layer may also be made of a material that is conventional in the prior art, for example, the first insulating dielectric layer is a silicon dioxide layer, and the sacrificial layer is a silicon nitride layer. Specifically, the process of etching to form the channel hole may be performed by masking with a hard mask layer.

The epitaxial layer is made of the same material as the substrate. When the material of the substrate is monocrystalline silicon, the material of the epitaxial layer is also monocrystalline silicon.

The preliminary charge trapping layer of the present application can be formed by any feasible method in the prior art, such as PECVD, etc., and those skilled in the art can select a suitable method to form the preliminary charge trapping layer of the present application according to practical situations.

In order to form the 3D NAND memory, in an embodiment of the present invention, after the forming the charge trapping layer 60, the manufacturing process further includes: forming a first recess 41 in the charge blocking layer 50, the charge trapping layer 60 and the charge tunneling layer 70 at the bottom of the channel hole, wherein the first recess 41 exposes a part of the surface of the epitaxial layer 40, specifically etching and removing a part of the charge tunneling layer 70, a part of the charge trapping layer 60, a part of the charge blocking layer 50 and a part of the epitaxial layer 40, and forming a first recess 41 in the epitaxial layer 40, as shown in fig. 8; forming a channel layer 80 and a second insulating medium layer 90 surrounded by the charge tunneling layer 70 in the channel hole 11, the channel layer 80 surrounding the second insulating medium layer 90, top surfaces of the channel layer 80 and the second insulating medium layer 90 being lower than an opening of the channel hole 11, specifically, forming a channel layer 80 in the first recess 41 and on an exposed surface of the charge tunneling layer 70, a distance between a first surface of the channel layer 80 and the substrate 10 being H3, a distance between an exposed surface of both sides of the channel hole 11 and the substrate 10 being H4, H3< H4, wherein the first surface of the channel layer 80 is a surface of the channel layer 80 having a largest distance from the substrate 10, as shown in fig. 10; forming a second insulating medium layer 90 in the first recess 41 and on the exposed surface of the channel layer, wherein the distance between the first surface of the second insulating medium layer 90 and the substrate 10 is H5, H5< H4, and the actual H5 may be equal to H3, as shown in fig. 11, the remaining channel hole 11 is a second recess 12, and the first surface of the second insulating medium layer 90 is the surface of the second insulating medium layer 90 with the largest distance from the substrate 10; a drain contact structure 100 is formed on the channel layer 80 and the second insulating medium layer 90, and the drain contact structure 100 is buried in the channel hole 11, that is, the drain contact structure 100 shown in fig. 12 is formed in the remaining channel hole 11 (i.e., in the second recess 12).

The above steps can be implemented in a manner feasible in the prior art, for example, the formation process of the channel layer 80 includes: the preliminary channel layer 81 is formed, as shown in fig. 9, and then a portion of the preliminary channel layer 81 is etched away to form the channel layer 80 of fig. 10. Of course, the channel layer 80 may also be formed after the second insulating medium layer 90 is formed, specifically, the preliminary channel layer 81 is formed first, then the preliminary second insulating medium layer 90 is formed, and finally, part of the preliminary channel layer 81 and the preliminary second insulating medium layer 90 are removed by etching, so as to form the structure shown in fig. 11.

The material of each structural layer may also be any feasible material in the prior art, for example, the charge tunneling layer may be silicon dioxide, the channel layer may be a polysilicon layer, the second insulating medium layer may be silicon dioxide, and the drain contact structure is formed of a polysilicon material. Of course, the materials of these structural layers may be replaced by other suitable materials, which will not be described herein.

The material of the charge blocking layer can be any feasible material in the prior art, such as silicon dioxide, etc., and the charge blocking layer can also be formed in any feasible manner in the prior art, and a person skilled in the art can select a suitable method and a suitable material according to actual situations to form the charge blocking layer described above in the present application.

In another specific embodiment of the present application, after forming the drain contact structure 100, the method further includes: removing the sacrificial layer 30 to form the structure shown in fig. 13; then, a third insulating medium layer 110 is formed on the surface of the exposed epitaxial layer 40, so as to form the structure shown in fig. 14; finally, a metal material is formed in the remaining void region to form a metal gate 120, as shown in fig. 15. The material of the third insulating dielectric layer 110 is any feasible material in the prior art, such as silicon dioxide or silicon nitride.

It should be noted that the method for manufacturing the three-dimensional memory structure in the present application is not limited to the above process, for example, the metal gate is not necessarily formed by forming the sacrificial layer first, and the metal gate may be deposited at the beginning and then need not be removed.

It should be noted that the semiconductor structure in the present application may be a memory or may be one memory cell of a memory, and fig. 1 to 15 show a memory including two memory cells for simplifying the structure.

In another exemplary embodiment of the present application, a semiconductor structure is provided, which is fabricated by any one of the above-mentioned fabrication processes.

The semiconductor structure is formed by adopting any method, the density of traps in the charge trapping layer is high, the memory window of the device is guaranteed to be relatively large, and the semiconductor structure is guaranteed to have good performance.

It should be noted that the above-mentioned semiconductor device may have a two-dimensional memory structure or a three-dimensional memory structure, for example, a 3D NAND memory, or memory cells of a 3D NAND memory, and fig. 15 shows only two memory cells in the memory.

In yet another exemplary embodiment of the present application, there is provided a semiconductor structure, as shown in fig. 15, including:

a base structure;

and a charge trapping layer 60, wherein the charge trapping layer 60 is formed by performing a predetermined process on a preliminary charge trapping layer, and a trap density of the charge trapping layer 60 is greater than a trap density of the preliminary charge trapping layer.

In the semiconductor structure, the charge trapping layer is formed by performing the predetermined treatment on the prepared charge trapping layer, and the number of traps is larger than that of the charge trapping layer directly formed without the predetermined treatment, so that the problem of small number of traps in the charge trapping layer in the prior art is solved, the memory window of the device is ensured to be relatively larger, and the device is ensured to have good performance.

The material of the preliminary charge trapping layer in the present application comprises a base material and a dopant material, the dopant material being decomposed into a gas or into a gas and a solid substance composed of at least one predetermined element during the predetermined process, the predetermined element being an element in the base material, so that the substance after the decomposition of the dopant material does not affect the trapping performance of the charge trapping layer. That is, the dopant material is decomposed into gas during a predetermined process, and the gas escapes, so that the surface area of the charge trap layer is increased, thereby increasing the number of traps; or the doping material is decomposed into a solid substance consisting of a gas and at least one predetermined element during a predetermined process, so that the surface area of the charge trapping layer is increased, thereby increasing the number of traps, and the remaining solid substance including at least one of nitrogen, oxygen, and silicon does not affect the trapping performance of the charge trapping layer.

The doping material in the present application can be any material in the prior art that meets the above requirements, and can be selected by those skilled in the art according to the actual situation, and in a specific embodiment in the present application, the doping material includes at least one of ozone, silicic acid, and polyethylene glycol, etc. These materials can further ensure more traps in the subsequently formed charge trapping layer.

The matrix material of the present application may be other materials that can form a charge trapping layer in the prior art, and those skilled in the art can select a suitable material to form the matrix material of the present application according to actual situations.

In a specific embodiment of the present application, the base material includes at least one of a silicon oxynitride compound, a silicon nitride compound, a silicon oxynitride compound, and a high-K dielectric. Wherein, for example, the high-K material can be HfO₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al₂O₃. The matrix material can further ensure that the trap density in the prepared charge trapping layer is higher, and further ensure that the trap density in the finally formed charge trapping layer is higher.

The manner of performing the predetermined treatment on the preliminary charge trapping layer in the present application may be any method that can release part of the substance in the doping material to form more traps, and a person skilled in the art may select a suitable predetermined treatment manner according to the actual situation, and specifically may select a corresponding predetermined treatment manner according to the doping material.

In a specific embodiment of the present application, the predetermined processing includes at least one of: heat treatment and ultraviolet light treatment. That is, the predetermined processing procedure may only include the step of performing the thermal treatment on the preliminary charge trapping layer, may only include the step of performing the ultraviolet light treatment on the preliminary charge trapping layer, and may also include both of the predetermined processing manners. The skilled person can select a suitable predetermined processing manner according to the actual situation. For example, when the doping material is ozone, the treatment mode of ultraviolet light can be selected; in the case where the doping material is silicic acid, a heat treatment may be employed.

It should be noted that the semiconductor structure in the present application may be any memory structure including a charge trapping layer, and may be a two-dimensional memory structure or a three-dimensional memory structure, and those skilled in the art can apply the manufacturing process of the present application to the manufacturing process of any memory structure including a charge trapping layer according to practical situations.

In order to limit the charges in the charge trapping layer and prevent the charges from escaping, in one embodiment of the present invention, the semiconductor structure further includes a charge blocking layer 50 and a charge tunneling layer 70 formed on the substrate structure, as shown in fig. 15, wherein the charge trapping layer 60 is located between the charge blocking layer 50 and the charge tunneling layer 70. The locations of the charge blocking layer and the charge tunneling are different for different memory devices.

The semiconductor structure of the present application may be a two-dimensional memory device, and in one of the two-dimensional devices not shown in the figures of the present application, the charge tunneling layer is located on the surface of the conductive channel layer on the base structure, the charge trapping layer is located on the surface of the charge tunneling layer away from the conductive channel layer, and the charge blocking layer is located on the surface of the charge trapping layer away from the charge tunneling layer.

In another embodiment of the present application, the semiconductor structure is a three-dimensional device, the base structure includes a channel hole 11, and as shown in fig. 15, the charge blocking layer 50, the charge trapping layer 60 and the charge tunneling layer 70 are at least located on the sidewall and the bottom of the channel hole 11 and are sequentially distributed along a direction away from the channel hole 11.

The base of the present application may be any suitable structure, and in a specific embodiment of the present application, the base structure includes a substrate 10, a stacked structure and an epitaxial layer, wherein the stacked structure is located on a surface of the substrate 10, the stacked structure includes first insulating dielectric layers 20 and metal gates 120 that are alternately disposed, and the stacked structure has the channel hole 11 therein, which exposes the substrate 10; the epitaxial layer 40 is located in the channel hole 11, and the epitaxial layer 40 passes through one of the sacrificial layers 30 closest to the substrate 10 and two of the first insulating medium layers 20 closest to the substrate, as shown in fig. 15, that is, a distance between a surface of the epitaxial layer 40 remote from the substrate 10 and the substrate 10 is H1, a distance between a surface of the first sacrificial layer 30 remote from the substrate 10 and the substrate 10 is H2, H1> H2, and the first sacrificial layer 30 is the sacrificial layer 30 having the smallest distance from the substrate 10.

The epitaxial layer is made of the same material as the substrate. When the material of the substrate is monocrystalline silicon, the material of the epitaxial layer is also monocrystalline silicon.

In a specific embodiment of the present application, the semiconductor structure is a 3D NAND memory, as shown in fig. 15, the charge blocking layer 50, the charge trapping layer 60 and the charge tunneling layer 70 at the bottom of the channel hole 11 have a first recess 41 therein, the first recess 41 abuts against a portion of the surface of the epitaxial layer 40, and the semiconductor structure further includes a channel layer 80, a second insulating medium layer 90 and a drain contact structure 100. Wherein the channel layer 80 is located in the remaining channel hole 11 and the first recess 41; a second insulating medium layer 90 is located on the surface of the channel layer 80, and the top surfaces of the channel layer 80 and the second insulating medium layer 90 are lower than the opening of the channel hole 11; the drain contact structure 100 is buried in the channel hole 11 and is located on the surface of the channel layer 80 and the surface of the second insulating medium layer 90.

In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described below with reference to specific embodiments.