阅读说明：本技术 三相四线系统断零线保护电路 (Zero line breaking protection circuit for three-phase four-wire system ) 是由 赵法强 赵鑫 于 2019-09-20 设计创作，主要内容包括：本申请提供了一种三相四线系统断零线保护电路,包括电压采集电路、第一逻辑处理电路、第二逻辑处理电路和逻辑相与电路。电压采集电路用于采集第一火线的第一电压、第二火线的第二电压、第三火线的第三电压和零线的第四电压。第一逻辑处理电路用于根据预设基准电压将第五电压分别与第一电压、第二电压和第三电压进行比较,输出并判断第一逻辑电平、第二逻辑电平和第三逻辑电平是否都是低电平,以确定第一逻辑处理电路输出低电平或高电平。第二逻辑处理电路将第四电压进行逻辑放大处理,并进行逻辑取反后得到第五逻辑电平。逻辑相与电路用于确定第五逻辑电平与第一逻辑处理电路输出的电平是否均是高电平,以确定是否断开三相四线系统的电压源。(The application provides a three-phase four-wire system zero line breaking protection circuit, which comprises a voltage acquisition circuit, a first logic processing circuit, a second logic processing circuit and a logic phase and circuit. The voltage acquisition circuit is used for acquiring a first voltage of the first live wire, a second voltage of the second live wire, a third voltage of the third live wire and a fourth voltage of the zero line. The first logic processing circuit is used for comparing the fifth voltage with the first voltage, the second voltage and the third voltage respectively according to a preset reference voltage, outputting and judging whether the first logic level, the second logic level and the third logic level are all low levels, and determining whether the first logic processing circuit outputs the low level or the high level. And the second logic processing circuit performs logic amplification processing on the fourth voltage and performs logic inversion to obtain a fifth logic level. The logical AND circuit is used for determining whether the fifth logic level and the level output by the first logic processing circuit are both high levels so as to determine whether to disconnect the voltage source of the three-phase four-wire system.)

1. A three-phase four-wire system zero-line-breaking protection circuit, comprising:

the voltage acquisition circuit (100), a first input end of the voltage acquisition circuit (100) is used for acquiring a first voltage of a first live wire (101), a second input end of the voltage acquisition circuit (100) is used for acquiring a second voltage of a second live wire (102), a third input end of the voltage acquisition circuit (100) is used for acquiring a third voltage of a third live wire (103), a fourth input end of the voltage acquisition circuit (100) is used for acquiring a fourth voltage of a zero wire (104), and the voltage acquisition circuit (100) is further used for determining a maximum value among the first voltage, the second voltage and the third voltage and outputting a fifth voltage;

the first logic processing circuit (200) is electrically connected with the voltage acquisition circuit (100), and is configured to receive the first voltage, the second voltage, the third voltage and the fifth voltage, compare the fifth voltage with the first voltage, the second voltage and the third voltage according to a preset reference voltage, and output a first logic level, a second logic level and a third logic level, and is further configured to determine whether the first logic level, the second logic level and the third logic level are all low levels, and determine, based on a determination result, that an output end of the first logic processing circuit (200) outputs a low level or a high level;

the second logic processing circuit (300) is electrically connected with the voltage acquisition circuit (100) and is used for receiving the fourth voltage, performing logic amplification processing on the fourth voltage according to the preset reference voltage to obtain a fourth logic level, performing logic inversion on the fourth logic level to obtain a fifth logic level, and outputting the fifth logic level; and

and logic circuit (400), a first input terminal of the and circuit (400) is electrically connected with the output terminal of the first logic processing circuit (200), a second input terminal of the and circuit (400) is electrically connected with the output terminal of the second logic processing circuit (300), and the and circuit is used for receiving the fifth logic level and determining whether the fifth logic level and the level output by the output terminal of the first logic processing circuit (200) are both high levels to determine whether to disconnect the voltage source of the three-phase four-wire system.

2. The three-phase four-wire system zero-line protection circuit of claim 1, wherein the first logic processing circuit (200) is configured to determine whether the first logic level, the second logic level, and the third logic level are all low levels;

if the first logic level, the second logic level and the third logic level are low levels on average, the output end of the first logic processing circuit (200) outputs low level;

if the first logic level, the second logic level and the third logic level are not all low levels, the output end of the first logic processing circuit (200) outputs high level.

3. The three-phase four-wire system zero-line-breaking protection circuit according to claim 1, characterized in that the voltage source of the three-phase four-wire system is disconnected if the logical and circuit (400) determines that the fifth logic level is a high level on average with the electrical output of the first logic processing circuit (200);

and if the logical AND circuit (400) determines that the fifth logic level and the level output by the output end of the first logic processing circuit (200) are not both high levels, the voltage source of the three-phase four-wire system is not disconnected.

4. The three-phase four-wire system zero-line protection circuit of claim 1, wherein the first logic processing circuit (200) comprises:

a voltage comparison circuit (210), electrically connected to the voltage acquisition circuit (100), for receiving the first voltage, the second voltage, the third voltage, and the fifth voltage, comparing the fifth voltage with the first voltage, the second voltage, and the third voltage according to the preset reference voltage, and outputting a first logic level, a second logic level, and a third logic level;

a logic exclusive-or circuit (220), electrically connected to the voltage comparison circuit (210), for receiving the first logic level, the second logic level, and the third logic level, and performing exclusive-or processing among the first logic level, the second logic level, and the third logic level to obtain and output a sixth logic level, a seventh logic level, and an eighth logic level; and

and the logical phase or circuit (230) is electrically connected with the logical exclusive-or circuit (220) and is used for receiving the sixth logic level, the seventh logic level and the eighth logic level, judging whether the sixth logic level, the seventh logic level and the eighth logic level are all low levels or not, and determining that the output end of the logical phase or circuit (230) outputs low level or high level to the logical phase and circuit (400) based on the judgment result.

5. The three-phase four-wire system zero-line protection circuit according to claim 4, wherein the voltage comparison circuit (210) comprises:

a first comparator (211) electrically connected to the voltage acquisition circuit (100), wherein a first input terminal of the first comparator (211) is configured to receive the fifth voltage, a second input terminal of the first comparator (211) is configured to receive the first voltage, a third input terminal of the first comparator (211) is configured to input the preset reference voltage, a fourth input terminal of the first comparator (211) is grounded, and an output terminal of the first comparator (211) outputs the first logic level to the exclusive-or circuit (220);

a first resistor (212), a first end of the first resistor (212) is electrically connected with a third input end of the first comparator (211), and a second end of the first resistor (212) is electrically connected with an output end of the first comparator (211);

a second comparator (213) electrically connected to the voltage acquisition circuit (100), wherein a first input of the second comparator (213) is configured to receive the fifth voltage, a second input of the second comparator (213) is configured to receive the second voltage, a third input of the second comparator (213) is configured to input the preset reference voltage, a fourth input of the second comparator (213) is grounded, and an output of the second comparator (213) outputs the second logic level to the exclusive-or circuit (220);

a second resistor (214), a first terminal of the second resistor (214) is electrically connected to a third input terminal of the second comparator (213), and a second terminal of the second resistor (214) is electrically connected to an output terminal of the second comparator (213);

a third comparator (215) electrically connected to the voltage acquisition circuit (100), wherein a first input of the third comparator (215) is configured to receive the fifth voltage, a second input of the third comparator (215) is configured to receive the third voltage, a third input of the third comparator (215) is configured to input the preset reference voltage, a fourth input of the third comparator (215) is grounded, and an output of the third comparator (215) outputs the third logic level to the logic exclusive-or circuit (220); and

a third resistor (216), a first terminal of the third resistor (216) being electrically connected to a third input terminal of the third comparator (215), a second terminal of the third resistor (216) being electrically connected to an output terminal of the third comparator (215).

6. The three-phase four-wire system zero-line protection circuit according to claim 4, wherein the logic phase OR circuit (230) comprises:

a first diode (231) electrically connected to the exclusive-or circuit (220), an anode of the first diode (231) for receiving the sixth logic level, and a cathode of the first diode (231) electrically connected to a first input terminal of the logical-and circuit (400);

a second diode (232) electrically coupled to the exclusive-or circuit (220), an anode of the second diode (232) for receiving the seventh logic level, a cathode of the second diode (232) electrically coupled to the first input of the logical-and circuit (400); and

a third diode (233) electrically coupled to the exclusive-or circuit (220), an anode of the third diode (233) configured to receive the sixth logic level, and a cathode of the third diode (233) electrically coupled to the first input of the logical-and circuit (400).

7. The three-phase four-wire system zero-line protection circuit according to claim 1, wherein the second logic processing circuit (300) comprises:

the voltage amplification processing circuit (310) is electrically connected with the voltage acquisition circuit (100) and is used for receiving the fourth voltage, performing logic amplification processing on the fourth voltage according to the preset reference voltage and outputting a fourth logic level; and

and the logic inverting circuit (320) is electrically connected with the voltage amplification processing circuit (310) and is used for receiving the fourth logic level, performing logic inversion on the fourth logic level to obtain a fifth logic level, and outputting the fifth logic level to a second input end of the logic AND circuit (400).

8. The three-phase four-wire system zero-line protection circuit of claim 7, wherein the voltage amplification processing circuit (310) comprises:

an operational amplifier (311), a first input terminal of the operational amplifier (311) is electrically connected to the voltage acquisition circuit (100) and is configured to receive the fourth voltage, a second input terminal of the operational amplifier (311) is configured to input the preset reference voltage, a third input terminal of the operational amplifier (311) is grounded, and an output terminal of the operational amplifier (311) outputs the fourth logic level to the logical inversion circuit (320);

a fourth resistor (312), a first end of the fourth resistor (312) is electrically connected with a fourth input end of the operational amplifier (311), and a second end of the fourth resistor (312) is grounded; and

a fifth resistor (313), wherein a first end of the fifth resistor (313) is electrically connected with a fourth input end of the operational amplifier (311), and a second end of the fifth resistor (313) is electrically connected with an output end of the operational amplifier (311).

9. The three-phase four-wire system zero-line protection circuit according to claim 1, wherein the logical AND circuit (400) comprises:

an and gate (410), a first input terminal of the and gate (410) being electrically connected to the output terminal of the first logic processing circuit (200), a second input terminal of the and gate (410) being electrically connected to the output terminal of the second logic processing circuit (300), the and gate (410) being configured to receive the fifth logic level and determine whether the fifth logic level and the level output by the output terminal of the first logic processing circuit (200) are both high levels, so as to determine whether to disconnect the voltage source of the three-phase four-wire system; and

a sixth resistor (420), a first end of the sixth resistor (420) is electrically connected to the first input end of the and gate (410), and a second end of the sixth resistor (420) is grounded.

10. The three-phase four-wire system zero-line protection circuit according to claim 1, characterized in that the voltage acquisition circuit (100) comprises:

a fourth diode (110), an anode of the fourth diode (110) being electrically connected to the first live line (101), a cathode of the fourth diode (140) being electrically connected to the first input of the first logic processing circuit (200);

a fifth diode (120), an anode of the fifth diode (120) being electrically connected to the second hot line (102), a cathode of the fifth diode (120) being electrically connected to the first input of the first logic processing circuit (200);

a sixth diode (130), an anode of the sixth diode (130) being electrically connected to the third live line (103), a cathode of the sixth diode (130) being electrically connected to the first input of the first logic processing circuit (200);

a seventh resistor (140), a first end of the seventh resistor (140) is electrically connected to the first live wire (101) and the second input end of the first logic processing circuit (200), respectively, and a second end of the seventh resistor (140) is grounded;

an eighth resistor (150), a first end of the eighth resistor (150) is electrically connected to the second live wire (102) and the third input end of the first logic processing circuit (200), respectively, and a second end of the eighth resistor (150) is grounded;

a ninth resistor (160), a first end of the ninth resistor (160) is electrically connected to the third live wire (103) and the fourth input end of the first logic processing circuit (200), respectively, and a second end of the ninth resistor (160) is grounded; and

a tenth resistor (170), wherein a first end of the tenth resistor (170) is electrically connected to the zero line (103) and a fifth input end of the first logic processing circuit (200), respectively, and a second end of the tenth resistor (170) is grounded.

11. The three-phase four-wire system zero-line protection circuit of claim 10, wherein the voltage acquisition circuit (100) further comprises:

a current limiting resistor (180), wherein a first end of the current limiting resistor (180) is electrically connected to a cathode of the fourth diode (140), a cathode of the fifth diode (120), a cathode of the sixth diode (130), and a first input end of the first logic processing circuit (200), respectively, and a second end of the current limiting resistor (180) is grounded.

Technical Field

The application relates to the technical field of power supply, in particular to a zero line breaking protection circuit of a three-phase four-wire system.

Background

At present, a three-phase four-wire power transmission network is mostly adopted in the low voltage of a distribution network in China, namely a power transmission mode of A, B, C three-phase power and a neutral wire (namely a zero line N). In a three-phase four-wire power supply system, if the zero line is not grounded well or disconnected, the result is that when the three-phase load is unbalanced, the potential of the zero line is not equal to 0, and the neutral point of the zero line is shifted.

The specific potential of the zero line is related to the unbalance degree of the three-phase load, the more unbalanced the three-phase load is, the larger the neutral point deviation is, and the higher the potential of the zero line is. The phase voltage of the three phases after zero line potential offset is not 220V, some phase voltages may exceed 220V, and some phase voltages are lower than 220V. When the offset of the neutral point is too large, the phase voltage of three phases is increased, and the electric appliance can be burnt by a user; after the potential of the zero line rises, when reaching a certain value, the zero line will cause electric shock accident danger, and the harm is huge, for example, the electric appliance burns out the conflagration that probably causes, causes loss of property, probably causes serious personal safety accidents such as electric shock casualties occasionally seriously.

Therefore, how to avoid the problem that the three-phase potential zero point drifts due to the zero line breaking of the three-phase four-wire power supply system, which causes the damage of the user electrical appliance, is urgently needed to be solved.

Disclosure of Invention

Therefore, it is necessary to provide a zero line breaking protection circuit for a three-phase four-wire system, aiming at the problem that the existing three-phase four-wire power supply system causes the drift of a three-phase potential zero point due to the zero line breaking, so as to cause the damage of a user electric appliance.

A three-phase four-wire system zero-line-breaking protection circuit comprising:

the voltage acquisition circuit comprises a first input end, a second input end, a fourth input end and a voltage acquisition circuit, wherein the first input end of the voltage acquisition circuit is used for acquiring a first voltage of a first live wire, the second input end of the voltage acquisition circuit is used for acquiring a second voltage of a second live wire, the third input end of the voltage acquisition circuit is used for acquiring a third voltage of a third live wire, the fourth input end of the voltage acquisition circuit is used for acquiring a fourth voltage of a zero line, and the voltage acquisition circuit is further used for determining the maximum value among the first voltage, the second voltage and the third voltage and outputting a fifth voltage;

the first logic processing circuit is electrically connected with the voltage acquisition circuit, and is configured to receive the first voltage, the second voltage, the third voltage and the fifth voltage, compare the fifth voltage with the first voltage, the second voltage and the third voltage according to a preset reference voltage, and output a first logic level, a second logic level and a third logic level, and is further configured to determine whether the first logic level, the second logic level and the third logic level are all low levels, and determine that an output end of the first logic processing circuit outputs a low level or a high level based on a determination result;

the second logic processing circuit is electrically connected with the voltage acquisition circuit and used for receiving the fourth voltage, performing logic amplification processing on the fourth voltage according to the preset reference voltage to obtain a fourth logic level, performing logic inversion on the fourth logic level to obtain a fifth logic level and outputting the fifth logic level; and

and the first input end of the logical AND circuit is electrically connected with the output end of the first logical processing circuit, the second input end of the logical AND circuit is electrically connected with the output end of the second logical processing circuit, and the logical AND circuit is used for receiving the fifth logical level and determining whether the fifth logical level and the level output by the output end of the first logical processing circuit are both high levels so as to determine whether to disconnect the voltage source of the three-phase four-wire system.

In one embodiment, the first logic processing circuit is configured to determine whether the first logic level, the second logic level, and the third logic level are all low levels;

if the first logic level, the second logic level and the third logic level are low levels on average, the output end of the first logic processing circuit outputs low levels;

and if the first logic level, the second logic level and the third logic level are not all low levels, the output end of the first logic processing circuit outputs high level.

In one embodiment, if the logical and circuit determines that the fifth logic level and the level output by the output of the first logic processing circuit are both high, the voltage source of the three-phase four-wire system is disconnected;

and if the logical AND circuit determines that the fifth logic level and the level output by the output end of the first logic processing circuit are not both high levels, the voltage source of the three-phase four-wire system is not disconnected.

In one embodiment, the first logic processing circuit comprises:

the voltage comparison circuit is electrically connected with the voltage acquisition circuit and is used for receiving the first voltage, the second voltage, the third voltage and the fifth voltage, comparing the fifth voltage with the first voltage, the second voltage and the third voltage respectively according to the preset reference voltage and outputting a first logic level, a second logic level and a third logic level;

a logic exclusive-or circuit electrically connected to the voltage comparison circuit, configured to receive the first logic level, the second logic level, and the third logic level, and perform exclusive-or processing among the first logic level, the second logic level, and the third logic level to obtain and output a sixth logic level, a seventh logic level, and an eighth logic level; and

and the logic phase or circuit is electrically connected with the logic exclusive-or circuit and is used for receiving the sixth logic level, the seventh logic level and the eighth logic level, judging whether the sixth logic level, the seventh logic level and the eighth logic level are all low levels or not, and determining that the output end of the logic phase or circuit outputs low level or high level to the logic phase and circuit based on the judgment result.

In one embodiment, the voltage comparison circuit includes:

a first comparator electrically connected to the voltage acquisition circuit, wherein a first input terminal of the first comparator is configured to receive the fifth voltage, a second input terminal of the first comparator is configured to receive the first voltage, a third input terminal of the first comparator is configured to input the preset reference voltage, a fourth input terminal of the first comparator is grounded, and an output terminal of the first comparator outputs the first logic level to the xor circuit;

a first end of the first resistor is electrically connected with a third input end of the first comparator, and a second end of the first resistor is electrically connected with an output end of the first comparator;

a second comparator electrically connected to the voltage acquisition circuit, wherein a first input terminal of the second comparator is configured to receive the fifth voltage, a second input terminal of the second comparator is configured to receive the second voltage, a third input terminal of the second comparator is configured to input the preset reference voltage, a fourth input terminal of the second comparator is grounded, and an output terminal of the second comparator outputs the second logic level to the xor circuit;

a first end of the second resistor is electrically connected with a third input end of the second comparator, and a second end of the second resistor is electrically connected with an output end of the second comparator;

a third comparator electrically connected to the voltage acquisition circuit, wherein a first input terminal of the third comparator is configured to receive the fifth voltage, a second input terminal of the third comparator is configured to receive the third voltage, a third input terminal of the third comparator is configured to input the preset reference voltage, a fourth input terminal of the third comparator is grounded, and an output terminal of the third comparator outputs the third logic level to the xor circuit; and

and a first end of the third resistor is electrically connected with a third input end of the third comparator, and a second end of the third resistor is electrically connected with an output end of the third comparator.

In one embodiment, the logical phase or circuit comprises:

a first diode electrically connected to the exclusive-or circuit, an anode of the first diode receiving the sixth logic level, and a cathode of the first diode electrically connected to the first input terminal of the logical-and circuit;

a second diode electrically connected to the exclusive-or circuit, an anode of the second diode being configured to receive the seventh logic level, and a cathode of the second diode being electrically connected to the first input of the logical-and circuit; and

and the anode of the third diode is used for receiving the sixth logic level, and the cathode of the third diode is electrically connected with the first input end of the logical AND circuit.

In one embodiment, the second logic processing circuit comprises:

the voltage amplification processing circuit is electrically connected with the voltage acquisition circuit and is used for receiving the fourth voltage, performing logic amplification processing on the fourth voltage according to the preset reference voltage and outputting a fourth logic level; and

and the logic inverting circuit is electrically connected with the voltage amplification processing circuit and used for receiving the fourth logic level, performing logic inversion on the fourth logic level to obtain a fifth logic level, and outputting the fifth logic level to a second input end of the logic AND circuit.

In one embodiment, the voltage amplification processing circuit includes:

the first input end of the operational amplifier is electrically connected with the voltage acquisition circuit and is used for receiving the fourth voltage, the second input end of the operational amplifier is used for inputting the preset reference voltage, the third input end of the operational amplifier is grounded, and the output end of the operational amplifier outputs the fourth logic level to the logic inverting circuit;

a first end of the fourth resistor is electrically connected with a fourth input end of the operational amplifier, and a second end of the fourth resistor is grounded; and

and a first end of the fifth resistor is electrically connected with the fourth input end of the operational amplifier, and a second end of the fifth resistor is electrically connected with the output end of the operational amplifier.

In one embodiment, the logical AND circuit comprises:

the first input end of the AND gate is electrically connected with the output end of the first logic processing circuit, the second input end of the AND gate is electrically connected with the output end of the second logic processing circuit, and the AND gate is used for receiving the fifth logic level and determining whether the fifth logic level and the level output by the output end of the first logic processing circuit are both high levels so as to determine whether to disconnect the voltage source of the three-phase four-wire system;

and a first end of the sixth resistor is electrically connected with the first input end of the AND gate, and a second end of the sixth resistor is grounded.

In one embodiment, the voltage acquisition circuit comprises:

a fourth diode, an anode of the fourth diode being electrically connected to the first live wire, and a cathode of the fourth diode being electrically connected to the first input terminal of the first logic processing circuit;

a fifth diode, an anode of the fifth diode being electrically connected to the second hot wire, and a cathode of the fifth diode being electrically connected to the first input terminal of the first logic processing circuit;

a sixth diode, an anode of the sixth diode is electrically connected to the third live wire, and a cathode of the sixth diode is electrically connected to the first input terminal of the first logic processing circuit;

a first end of the seventh resistor is electrically connected with the first live wire and the second input end of the first logic processing circuit respectively, and a second end of the seventh resistor is grounded;

a first end of the eighth resistor is electrically connected with the second live wire and the third input end of the first logic processing circuit respectively, and a second end of the eighth resistor is grounded;

a ninth resistor, a first end of which is electrically connected to the third live wire and a fourth input end of the first logic processing circuit, respectively, and a second end of which is grounded; and

and a first end of the tenth resistor is electrically connected with the zero line and a fifth input end of the first logic processing circuit respectively, and a second end of the tenth resistor is grounded.

In one embodiment, the voltage acquisition circuit further comprises:

and a first end of the current-limiting resistor is electrically connected with the cathode of the fourth diode, the cathode of the fifth diode, the cathode of the sixth diode and the first input end of the first logic processing circuit respectively, and a second end of the current-limiting resistor is grounded.

Compared with the prior art, the three-phase four-wire system zero line breaking protection circuit acquires voltages of three live wires and one zero line through the voltage acquisition circuit, compares the acquired fifth voltage with the three voltages respectively through the first logic processing circuit according to a preset reference voltage, outputs and judges whether the first logic level, the second logic level and the third logic level are all low levels, and determines that the output end of the first logic processing circuit outputs the low level or the high level based on the judgment result; and the fourth voltage is logically amplified and logically inverted based on the preset reference voltage to obtain a fifth logic level in cooperation with the second logic processing circuit, and then whether the fifth logic level and the level output by the output end of the first logic processing circuit are both high levels is determined through the logic phase and circuit, so that whether the voltage source of the three-phase four-wire system is disconnected is determined, the problem that the electric appliance of a user is damaged due to the drift of the three-phase potential zero point caused by the zero line disconnection is solved, and the safety is improved.

Drawings

Fig. 1 is a schematic circuit block diagram of a three-phase four-wire system zero line breaking protection circuit according to an embodiment of the present application;

fig. 2 is a circuit diagram of a three-phase four-wire system zero line breaking protection circuit according to an embodiment of the present application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Referring to fig. 1, an embodiment of the present application provides a three-phase four-wire system zero-line-breaking protection circuit 10, which includes: voltage acquisition circuit 100, first logic processing circuit 200, second logic processing circuit 300 and logical phase and circuit 400. A first input terminal of the voltage collecting circuit 100 is configured to collect a first voltage of a first live wire 101. A second input terminal of the voltage collecting circuit 100 is configured to collect a second voltage of the second live wire 102. A third input terminal of the voltage collecting circuit 100 is configured to collect a third voltage of a third live wire 103. A fourth input terminal of the voltage acquisition circuit 100 is configured to acquire a fourth voltage of the neutral line 104. The first logic processing circuit 200 is electrically connected to the voltage acquisition circuit 100. The voltage acquisition circuit 100 is further configured to determine a maximum value among the first voltage, the second voltage, and the third voltage, and output a fifth voltage.

The first logic processing circuit 200 is configured to receive the first voltage, the second voltage, the third voltage, and the fifth voltage. The first logic processing circuit 200 compares the fifth voltage with the first voltage, the second voltage, and the third voltage according to a preset reference voltage, and outputs a first logic level, a second logic level, and a third logic level. The first logic processing circuit 200 is further configured to determine whether the first logic level, the second logic level, and the third logic level are all low levels, and determine that the output terminal of the first logic processing circuit 200 outputs a low level or a high level based on the determination result.

The second logic processing circuit 300 is electrically connected to the voltage acquisition circuit 100. The second logic processing circuit 300 is configured to receive the fourth voltage, perform logic amplification on the fourth voltage according to the preset reference voltage to obtain a fourth logic level, perform logic inversion on the fourth logic level to obtain a fifth logic level, and output the fifth logic level. A first input terminal of the logical and circuit 400 is electrically connected to an output terminal of the first logical processing circuit 200. A second input of the logical and circuit 400 is electrically connected to an output of the second logical processing circuit 300. The and circuit 400 is configured to receive the fifth logic level and determine whether the fifth logic level and the output level of the output terminal of the first logic processing circuit 200 are both high levels to determine whether to disconnect the voltage source of the three-phase four-wire system.

It is understood that the specific circuit structure of the voltage collecting circuit 100 is not limited as long as the circuit structure has the function of collecting the voltages of the first live wire 101, the second live wire 102, the third live wire 103 and the neutral wire 104. In one embodiment, the voltage acquisition circuit 100 may be formed by a plurality of acquisition resistors in combination with a plurality of diodes. Wherein, one acquisition resistance is corresponding to and acquires a voltage. For example, a collecting resistor collects the voltage of the first live wire 101 to obtain the first voltage; the other collecting resistor collects the voltage of the second live wire 102 to obtain the second voltage.

And then determining the maximum value of the first voltage, the second voltage and the third voltage through a diode and outputting. Specifically, one end of each collecting resistor electrically connected with the live wire is electrically connected with one end of a diode, and then the other ends of the three diodes are connected in parallel. The maximum value of the first voltage, the second voltage and the third voltage can be determined by using the unidirectional conduction characteristic of the diode, and then the voltage corresponding to the maximum value (i.e. the fifth voltage) is output.

In one embodiment, a voltage value of the fifth voltage is a maximum value of the first voltage, the second voltage, and the third voltage minus a turn-on voltage value of a diode. In one embodiment, if the first voltage is a maximum value among the first voltage, the second voltage, and the third voltage, the fifth voltage differs from the first voltage by a turn-on voltage of one diode.

In one embodiment, the voltage acquisition circuit 100 may also be formed by a voltage transformer with a plurality of diodes. The voltage on each line (i.e. the first live line 101, the second live line 102, the third live line 103 and the neutral line 104) can be detected by a voltage transformer.

It is to be understood that the specific circuit structure of the first logic processing circuit 200 is not particularly limited, as long as the function of comparing the fifth voltage with the first voltage, the second voltage, and the third voltage according to the preset reference voltage, and outputting the first logic level, the second logic level, and the third logic level, and determining whether all of the three logic levels are low level, thereby determining whether to output low level or high level, is provided. In one embodiment, the first logic processing circuit 200 may be formed by a plurality of comparators, a plurality of exclusive or gates and a plurality of diodes. And the number of the comparators, the exclusive-OR gates and the diodes is the same as that of the live wires.

In one embodiment, the first logic processing circuit 200 may also be composed of a plurality of comparators along with a plurality of diodes. Wherein the number of comparator diodes is the same as the number of fire lines. In one embodiment, the preset reference voltage may be set according to actual requirements, and specific values are not illustrated here. Whether the first logic level, the second logic level, and the third logic level are all low levels may be determined by the first logic processing circuit 200, and it may be determined that the output terminal of the first logic processing circuit 200 outputs a low level or a high level based on the determination result.

Specifically, if the first logic level, the second logic level, and the third logic level are low levels on average, the output of the output terminal of the first logic processing circuit 200 is low level. If the first logic level, the second logic level, and the third logic level are not all low levels, that is, at least one of the first logic level, the second logic level, and the third logic level is a high level, the output of the first logic processing circuit 200 is a high level. The output of the first logic processing circuit 200 is output low only when the first logic level, the second logic level, and the third logic level are low on average.

It is understood that the specific circuit structure of the second logic processing circuit 300 is not limited, as long as the second logic processing circuit has a function of performing logic amplification processing on the fourth voltage according to the preset reference voltage, and performing logic inversion to obtain a fifth logic level. In one embodiment, the second logic processing circuit 300 may be formed by an operational amplifier and a not gate. In one embodiment, the second logic processing circuit 300 may also be formed by an amplifier and a comparator with a not gate.

It is to be understood that the specific circuit configuration of the and circuit 400 is not limited as long as it has a function of determining whether the fifth logic level and the level output from the output terminal of the first logic processing circuit 200 are both high levels, thereby determining whether to output a high level to disconnect the voltage source of the three-phase four-wire system. In one embodiment, the and logic circuit 400 may be formed of an and gate. In one embodiment, the and logic circuit 400 may also be formed by an and gate with a protection resistor.

Whether the output terminal of the and circuit 400 outputs a high level or a low level is determined by determining whether the fifth logic level and the level output from the output terminal of the first logic processing circuit 200 are both a high level through the and circuit 400. In one embodiment, if the and circuit 400 determines that the fifth logic level is high on electrical average with the output of the first logic processing circuit 200, the output of the and circuit 400 outputs high, thereby disconnecting the voltage supply of the three-phase four-wire system.

In one embodiment, if the and circuit 400 determines that the fifth logic level and the output of the first logic processing circuit 200 are not both high, i.e. at least one of them is low, the output of the and circuit 400 outputs low, thereby not disconnecting the voltage source of the three-phase four-wire system.

In one embodiment, the voltage on the neutral line is zero when the voltages on the three live lines are balanced. That is, the fourth voltage is zero when the voltages on the three live wires reach equilibrium. And the magnitude of the fourth voltage increases with the voltage imbalance on the three live wires. At this time, it is necessary for the voltage acquisition circuit 100, the first logic processing circuit 200, the second logic processing circuit 300 and the logical phase and circuit 400 to cooperate with each other, so as to determine whether the output end of the logical phase and circuit 400 outputs a high level, and thus determine whether to disconnect the voltage source of the three-phase four-wire system. Thereby improving the safety of use.

In this embodiment, the voltage of three live wires and one zero wire is acquired by the voltage acquisition circuit 100, then the acquired fifth voltage is compared with the three voltages respectively by the first logic processing circuit 200 according to a preset reference voltage, and then whether the first logic level, the second logic level and the third logic level are all low levels is output and judged, and it is determined that the output end of the first logic processing circuit 200 outputs a low level or a high level based on the judgment result; and cooperates with the second logic processing circuit 300 to logically amplify and logically invert the fourth voltage based on the preset reference voltage to obtain a fifth logic level, and then determines whether the fifth logic level and the level output by the output end of the first logic processing circuit are both high levels through the logic phase and circuit 400, so as to determine whether to disconnect the voltage source of the three-phase four-wire system, thereby avoiding the problem of damage to the user electrical appliance due to zero line break caused by zero-point drift of the three-phase potential, and improving the safety.

In one embodiment, the first logic processing circuit 200 comprises: a voltage comparison circuit 210, a logical exclusive-or circuit 220, and a logical phase or circuit 230. The voltage comparison circuit 210 is electrically connected to the voltage acquisition circuit 100. The voltage comparison circuit 210 is configured to receive the first voltage, the second voltage, the third voltage, and the fifth voltage. The voltage comparison circuit 210 compares the fifth voltage with the first voltage, the second voltage, and the third voltage according to the preset reference voltage, and outputs a first logic level, a second logic level, and a third logic level.

The exclusive or circuit 220 is electrically connected to the voltage comparison circuit 210. The exclusive-or circuit 220 is configured to receive the first logic level, the second logic level, and the third logic level, perform exclusive-or processing on the first logic level, the second logic level, and the third logic level, and obtain and output a sixth logic level, a seventh logic level, and an eighth logic level.

The logical phase or circuit 230 is electrically connected to the logical exclusive or circuit 220. The or circuit 230 is configured to receive the sixth logic level, the seventh logic level, and the eighth logic level, determine whether the sixth logic level, the seventh logic level, and the eighth logic level are all low levels, and determine that the output terminal of the or circuit 230 outputs a low level or a high level to the and circuit 400 based on the determination result.

In one embodiment, the voltage comparison circuit 210 may be formed by a plurality of comparators in combination with a plurality of resistors. And the number of the comparators and the number of the resistors are the same as the number of the live wires. Specifically, referring to fig. 2, the voltage comparison circuit 210 may include: a first comparator 211, a first resistor 212, a second comparator 213, a second resistor 214, a third comparator 215, and a third resistor 216. The first comparator 211 is electrically connected to the voltage acquisition circuit 100. A first input terminal of the first comparator 211 is configured to receive the fifth voltage. A second input terminal of the first comparator 211 is configured to receive the first voltage. A third input terminal of the first comparator 211 is configured to input the preset reference voltage, and a fourth input terminal of the first comparator 211 is grounded. The output terminal of the first comparator 211 outputs the first logic level to the logic exclusive-or circuit 220. A first terminal of the first resistor 212 is electrically connected to a third input terminal of the first comparator 211. A second terminal of the first resistor 212 is electrically connected to an output terminal of the first comparator 211.

The second comparator 213 is electrically connected to the voltage acquisition circuit 100. A first input of the second comparator 213 is configured to receive the fifth voltage. A second input of the second comparator 213 is configured to receive the second voltage. A third input terminal of the second comparator 213 is used for inputting the preset reference voltage. A fourth input terminal of the second comparator 213 is grounded. The output terminal of the second comparator 213 outputs the second logic level to the logic exclusive or circuit 220. A first terminal of the second resistor 214 is electrically connected to a third input terminal of the second comparator 213. A second terminal of the second resistor 214 is electrically connected to an output terminal of the second comparator 213.

The third comparator 215 is electrically connected to the voltage acquisition circuit 100. A first input of the third comparator 215 is configured to receive the fifth voltage. A second input of the third comparator 215 is configured to receive the third voltage. A third input terminal of the third comparator 215 is used for inputting the preset reference voltage. The fourth input of the third comparator 215 is connected to ground. The output of the third comparator 215 outputs the third logic level to the logic exclusive-or circuit 220. A first terminal of the third resistor 216 is electrically connected to a third input terminal of the third comparator 215. A second terminal of the third resistor 216 is electrically connected to an output terminal of the third comparator 215.

The first voltage is compared with the fifth voltage by the first comparator 211. If the first voltage and the fifth voltage have a difference of a diode turn-on voltage, the first logic level (i.e., OA in the figure) output by the output terminal of the first comparator 211 is a low level because the zero-crossing detection voltage of the first comparator 211 is always smaller than the diode turn-on voltage. While the second logic level (i.e., OB in the figure) output by the second comparator 213 and the third logic level (i.e., OC in the figure) output by the third comparator 215 are both high.

Similarly, the second voltage is compared with the fifth voltage by the second comparator 213. If the difference between the second voltage and the fifth voltage is a diode turn-on voltage, the second logic level output by the output terminal of the second comparator 213 is a low level. At this time, the first logic level output by the first comparator 211 and the third logic level output by the third comparator 215 are both high levels.

The third voltage is compared with the fifth voltage by the third comparator 215. If the third voltage and the fifth voltage differ by a diode turn-on voltage, the third logic level output by the output terminal of the third comparator 215 is a low level. At this time, the first logic level output by the first comparator 211 and the second logic level output by the second comparator 213 are both high levels.

In one embodiment, the levels on OA, OB, OC are not the same as long as the voltages on the three hot lines are not the same. The levels on OA, OB, OC will be the same and all low only when the voltages on the three fire lines are just balanced. In one embodiment, the first comparator 211, and/or the second comparator 213, and/or the third comparator 215 may each employ a comparator of model LM 336.

In one embodiment, the logic exclusive-or circuit 220 may be formed of a plurality of exclusive-or gates. Wherein the number of the exclusive-OR gates is the same as the number of the fire lines. In one embodiment, the exclusive or gate may be an exclusive or gate of type 74HC 86D. The logic output truth table of the exclusive-or gate outputs low level when the levels of the two input pins are the same, and outputs high level when the levels of the two input pins are different. And performing exclusive-or processing on the first logic level, the second logic level and the third logic level through an exclusive-or gate, wherein the output sixth logic level, the output seventh logic level and the output eighth logic level are all low level only when three logic values of OA, OB and OC are the same, namely voltages on three live wires are balanced, otherwise at least one of the output sixth logic level, the output seventh logic level and the output eighth logic level is high level.

In one embodiment, the logical phase or circuit 230 may be formed of a plurality of diodes. The number of the diodes is the same as that of the live wires. Specifically, the logic or circuit 230 may include: a first diode 231, a second diode 232, and a third diode 233. The first diode 231 is electrically connected to the logic exclusive or circuit 220. The anode of the first diode 231 is used to receive the sixth logic level. The cathode of the first diode 231 is electrically connected to a first input terminal of the logical phase and circuit 400. The second diode 232 is electrically connected to the logic exclusive-or circuit 220.

The anode of the second diode 232 is used to receive the seventh logic level. The cathode of the second diode 232 is electrically connected to the first input of the logical phase and circuit 400. The third diode 233 is electrically connected to the logic exclusive or circuit 220. The anode of the third diode 233 is configured to receive the sixth logic level. The cathode of the third diode 233 is electrically connected to the first input of the logical and circuit 400.

Through the cooperation of the first diode 231, the second diode 232 and the third diode 233, the sixth logic level, the seventh logic level and the eighth logic level are determined to be high or low, and only when the sixth logic level, the seventh logic level and the eighth logic level are all low, the output end of the or circuit 230 outputs a low level. And the output terminal (i.e., LO) of the or circuit 230 outputs a high level as long as any one of the sixth, seventh and eighth logic levels is a high level.

In one embodiment, the voltage comparison circuit 210, the exclusive-or circuit 220, and the or circuit 230 cooperate to determine whether the three live voltages are balanced. When the voltages on the three live lines are balanced with each other, the LO output is low; at this time, even if the voltage on the zero line 104 is 0, the output terminal (i.e., LN) of the second logic processing circuit 300 outputs a high level, and the output terminal of the logical phase or circuit 230 outputs a low level (i.e., OUT output is a low level). When the zero line 104 is disconnected and the voltages of the three live lines are exactly balanced with each other, the OUT output is also at a low level; however, when the voltages on the three live wires are unbalanced, a high level is output on the LO, and at the moment, the high level is output on the OUT immediately, so that the voltage source of the three-phase four-wire system further improves the use safety.

In one embodiment, the second logic processing circuit 300 comprises: a voltage amplification processing circuit 310 and a logic inversion circuit 320. The voltage amplification processing circuit 310 is electrically connected to the voltage acquisition circuit 100. The voltage amplification processing circuit 310 is configured to receive the fourth voltage, perform logic amplification processing on the fourth voltage according to the preset reference voltage, and output the fourth logic level. The logic inverting circuit 320 is electrically connected to the voltage amplification processing circuit 310. The logic inverting circuit 320 is configured to receive the fourth logic level, perform logic inverting on the fourth logic level to obtain a fifth logic level, and output the fifth logic level to the second input end of the logic and circuit 400.

In one embodiment, the voltage amplification processing circuit 310 may be composed of an operational amplifier and a resistor. Specifically, the voltage amplification processing circuit 310 may include: an operational amplifier 311, a fourth resistor 312, and a fifth resistor 313. A first input terminal of the operational amplifier 311 is electrically connected to the voltage acquisition circuit 100 and is configured to receive the fourth voltage. A second input terminal of the operational amplifier 311 is used for inputting the preset reference voltage. The third input terminal of the operational amplifier 311 is grounded. The output terminal of the operational amplifier 311 outputs the fourth logic level to the logic inverting circuit 320. A first end of the fourth resistor 312 is electrically connected to a fourth input end of the operational amplifier 311. A second terminal of the fourth resistor 312 is connected to ground. A first end of the fifth resistor 313 is electrically connected to a fourth input end of the operational amplifier 311. A second terminal of the fifth resistor 313 is electrically connected to the output terminal of the operational amplifier 311.

When only a slight voltage (that is, the fourth voltage is a slight voltage) is collected on the zero line 104, the slight voltage is amplified by the operational amplifier 311. In one embodiment, the fourth voltage is greater than or equal to 0.01V. When the collected fourth voltage is less than 0.01V, neglecting and defaulting to zero. In one embodiment, the amplification factor of the operational amplifier 311 is greater than or equal to 100 times, so that the output end of the operational amplifier 311 can output a high level only when the fourth voltage is greater than or equal to 0.01V. On the contrary, when the collected fourth voltage is less than 0.01V (i.e. the fourth voltage is 0), the output end of the operational amplifier 311 outputs a low level.

In one embodiment, the logic inverting circuit 320 may be formed by a not gate. And the fourth logic level is logically inverted through the not gate, and the fifth logic level is obtained and then output to the second input end of the logical and circuit 400. For example, when the fourth voltage is 0, the fourth logic level is a low level, and the fifth logic level obtained by logic inversion is a high level. Through the cooperation of the voltage amplification processing circuit 310 and the logic inversion circuit 320, the collected tiny voltage can be logically processed, and then the logic phase and the circuit 400 can be conveniently subjected to logic judgment.

In one embodiment, the logical AND circuit 400 includes: and gate 410, sixth resistor 420. A first input terminal of the and gate 410 is electrically connected to an output terminal of the first logic processing circuit 200. A second input terminal of the and gate 410 is electrically connected to an output terminal of the second logic processing circuit 300. The and gate 410 is configured to receive the fifth logic level and determine whether the fifth logic level and the level output by the output terminal of the first logic processing circuit 200 are both high levels, so as to determine whether to disconnect the voltage source of the three-phase four-wire system. A first terminal of the sixth resistor 420 is electrically connected to a first input terminal of the and gate 410. A second terminal of the sixth resistor 420 is grounded.

Whether the fifth logic level and the level output from the output of the first logic processing circuit 200 are both high level is determined by the and gate 410, thereby determining whether the output of the and gate 410 outputs high level or low level. In one embodiment, if the and gate 410 determines that the fifth logic level is high on average with the voltage output by the output of the first logic processing circuit 200, the output of the and gate 410 outputs high, thereby disconnecting the voltage source of the three-phase four-wire system.

In one embodiment, if the and gate 410 determines that the fifth logic level and the output level of the output terminal of the first logic processing circuit 200 are not both high, i.e. at least one of them is low, the output terminal of the and gate 410 outputs low, so as not to disconnect the voltage source of the three-phase four-wire system. The and gate 410 can be protected from damage by the sixth resistor 420.

In one embodiment, the voltage acquisition circuit 100 includes: a fourth diode 110, a fifth diode 120, a sixth diode 130, a seventh resistor 140, an eighth resistor 150, a ninth resistor 160, and a tenth resistor 170. The anode of the fourth diode 110 is electrically connected to the first live line 101. The cathode of the fourth diode 140 is electrically connected to the first input terminal of the first logic processing circuit 200. The anode of the fifth diode 120 is electrically connected to the second hot line 102. The cathode of the fifth diode 120 is electrically connected to the first input terminal of the first logic processing circuit 200. The anode of the sixth diode 130 is electrically connected to the third live line 103. The cathode of the sixth diode 130 is electrically connected to the first input terminal of the first logic processing circuit 200.

A first end of the seventh resistor 140 is electrically connected to the first live wire 101 and a second input end of the first logic processing circuit 200, respectively. A second terminal of the seventh resistor 140 is grounded. A first end of the eighth resistor 150 is electrically connected to the second active line 102 and a third input end of the first logic processing circuit 200, respectively. A second terminal of the eighth resistor 150 is grounded. A first end of the ninth resistor 160 is electrically connected to the third live wire 103 and a fourth input end of the first logic processing circuit 200, respectively. A second terminal of the ninth resistor 160 is connected to ground. A first end of the tenth resistor 170 is electrically connected to the zero line 103 and a fifth input end of the first logic processing circuit 200, respectively. A second terminal of the tenth resistor 170 is connected to ground.

In one embodiment, the voltage on the first live line 101 may be collected through the seventh resistor 140 to obtain the first voltage (i.e. VA in fig. 2); the voltage on the second live line 102 can be collected through the eighth resistor 150 to obtain the second voltage (i.e. VB in fig. 2); the voltage on the third live line 103 can be collected through the ninth resistor 160 to obtain the third voltage (i.e. VC in fig. 2); the voltage on the neutral wire 104 may be acquired through the tenth resistor 170, resulting in the fourth voltage (i.e., VN in fig. 2).

In one embodiment, by cooperation of the fourth diode 110, the fifth diode 120, and the sixth diode 130, a maximum value of the first voltage, the second voltage, and the third voltage may be determined, and a voltage corresponding to the maximum value (i.e., VD in fig. 2) may be output. VD is the maximum value of the three voltages minus the conducting voltage value of the diode on the corresponding line, i.e. the fifth voltage. The voltages of the first live wire 101, the second live wire 102, the third live wire 103 and the zero wire 104 are respectively collected by the voltage collecting circuit 100, so that the subsequent circuits can conveniently perform logic processing.

In one embodiment, the voltage acquisition circuit 100 further comprises: a current limiting resistor 180. A first end of the current limiting resistor 180 is electrically connected to a cathode of the fourth diode 140, a cathode of the fifth diode 120, a cathode of the sixth diode 130, and a first input end of the first logic processing circuit 200, respectively, and a second end of the current limiting resistor 180 is grounded. The output end corresponding to the fifth voltage is protected by the current limiting resistor 180, and the output end is prevented from being damaged due to overlarge voltage.

In one embodiment, the three-phase four-wire system zero line protection circuit 10, when in use, detects whether the neutral line 104 is open or not is detecting whether there is voltage on VN. And VN has no voltage, there are two cases: one is that the voltages on the three live wires are balanced with each other, and at this time, the voltage sources of the three live wires cannot be disconnected, because the voltages on the three live wires are in short time balance with each other, and are in a normal power utilization state; another situation is when the neutral conductor 104 is disconnected, and a high voltage must be output at OUT, thereby signaling disconnection of the voltage sources for the three live conductors. In this circuit, the LN outputs a high level in both cases. In order to avoid the power supply from being mistakenly disconnected, the OUT output signal also needs to judge whether the three-phase current is just balanced when the zero line 104 is at 0 voltage, so as to further judge whether the voltage sources of the three live wires need to be disconnected, and further improve the safety of power utilization.

To sum up, in the present application, the voltage acquisition circuit 100 acquires voltages of three live wires and one zero wire, the first logic processing circuit 200 compares the acquired fifth voltage with the three voltages according to a preset reference voltage, and then outputs and judges whether the first logic level, the second logic level, and the third logic level are all low levels, and determines that the output end of the first logic processing circuit 200 outputs a low level or a high level based on the judgment result; and cooperates with the second logic processing circuit 300 to logically amplify and logically invert the fourth voltage based on the preset reference voltage to obtain a fifth logic level, and then determines whether the fifth logic level and the level output by the output end of the first logic processing circuit are both high levels through the logic phase and circuit 400, so as to determine whether to disconnect the voltage source of the three-phase four-wire system, thereby avoiding the problem of damage to the user electrical appliance due to zero line break caused by zero-point drift of the three-phase potential, and improving the safety.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.