阅读说明：本技术 使用开关电容器或电容器-电感器块的并联电压调节器 (Parallel voltage regulator using switched capacitors or capacitor-inductor blocks ) 是由 蒋帅 南辰浩 李昕 郑子宇 莫巴沙尔·亚兹达尼 于 2018-06-05 设计创作，主要内容包括：至少一个方面涉及一种电源。该电源包括一个或多个未调节电压转换器。每个未调节电压转换器包括跨其输出端子产生输出电压的开关块。该电源包括被耦合至未调节电压转换器中的至少一个的电压供给输入以及被耦合至未调节电压转换器中的至少一个的未调节电压总线。该电源包括电压调节器,该电压调节器被耦合至未调节电压总线并且跨电压调节器的输出端子产生调节电压。电压调节器的输出端子被并联连接至未调节电压转换器中的至少一个的输出端子。这可以跨一对电源输出端子产生调节输出电压。(At least one aspect relates to a power supply. The power supply includes one or more unregulated voltage converters. Each unregulated voltage converter includes a switch block that generates an output voltage across its output terminals. The power supply includes a voltage supply input coupled to at least one of the unregulated voltage converters and an unregulated voltage bus coupled to at least one of the unregulated voltage converters. The power supply includes a voltage regulator coupled to the unregulated voltage bus and producing a regulated voltage across output terminals of the voltage regulator. The output terminals of the voltage regulators are connected in parallel to the output terminal of at least one of the unregulated voltage converters. This may produce a regulated output voltage across a pair of power supply output terminals.)

1. A power supply, comprising:

one or more unregulated voltage converters, each unregulated voltage converter including a switching block that generates an output voltage across a first converter output terminal and a second converter output terminal;

a voltage supply input coupled to at least one of the unregulated voltage converters;

an unregulated voltage bus coupled to at least one of the unregulated voltage converters; and

a voltage regulator coupled to the unregulated voltage bus and producing a regulated voltage across a first regulator output terminal and a second regulator output terminal,

wherein the first regulator output terminal is connected to the first converter output terminal of at least one of the unregulated voltage converters and the second regulator output terminal is connected to the second converter output terminal of the at least one unregulated voltage converter to yield a regulated output voltage across a first power supply output terminal and a second power supply output terminal.

2. The power supply of claim 1, wherein each switch block comprises:

a first solid state switch between a first input terminal of the switch block and a first terminal of a capacitor;

a second solid state switch between the second input terminal of the switch block and the second terminal of the capacitor;

a third solid state switch between the first terminal of the capacitor and the first converter output terminal of the switch block; and

a fourth solid state switch between the second terminal of the capacitor and the second converter output terminal of the switch block.

3. The power supply of claim 1, wherein each switch block comprises:

a first solid state switch between a first input terminal of the switch block and a first terminal of a capacitor;

a second solid state switch between a second input terminal of the switch block and the first terminal of the capacitor;

a third solid state switch between a second terminal of the capacitor and the first converter output terminal of the switch block; and

a fourth solid state switch between the second terminal of the capacitor and the second converter output terminal of the switch block.

4. The power supply of claim 3, wherein the third and fourth solid state switches have a voltage rating that is less than a maximum input voltage of the voltage supply input and greater than or equal to the regulated output voltage.

5. The power supply of claim 1, wherein each switch block comprises:

a tank circuit comprising a capacitor coupled in series to an inductor, the tank circuit having a first terminal and a second terminal;

a first solid state switch between a first input terminal of the switch block and the first terminal of the tank circuit;

a second solid state switch between a second input terminal of the switch block and a second terminal of the tank circuit;

a third solid state switch between the first terminal of the tank circuit and the first converter output terminal of the switch block; and

a fourth solid state switch between the second terminal of the tank circuit and the second converter output terminal of the switch block.

6. The power supply of claim 1, wherein each switch block comprises:

a tank circuit comprising a capacitor coupled in series to an inductor, the tank circuit having a first terminal and a second terminal;

a first solid state switch between a first input terminal of the switch block and a first terminal of the tank circuit;

a second solid state switch between a second input terminal of the switch block and the first terminal of the tank circuit;

a third solid state switch between the second terminal of the tank circuit and the first converter output terminal of the switch block; and

a fourth solid state switch between the second terminal of the tank circuit and the second converter output terminal of the switch block.

7. The power supply of claim 6, wherein the third and fourth solid state switches have a voltage rating that is less than a maximum input voltage of the voltage supply input and greater than or equal to the regulated output voltage.

8. The power supply of claim 1, wherein the voltage regulator has a non-inverting buck-boost configuration.

9. The power supply of claim 1, wherein the voltage regulator has an inverting buck-boost configuration.

10. The power supply of claim 1, comprising number B_lTo B_NThe N switch blocks of (2), wherein:

each switch block having a first converter input terminal and a second converter input terminal;

the voltage supply input is coupled to B_lThe first converter input terminal of a switching block;

the unregulated voltage bus is coupled to B_NThe second converter input terminal of the switching block; and

for number B₂To B_NEach switch block of, B_iThe first converter input terminal of the switch block is coupled to B_i-1The second converter input terminal of the switch block.

11. The power supply of claim 10, comprising at least three switch blocks, wherein:

switch block B_lThe method comprises the following steps:

a first solid state switch between the first converter input terminal of the switch block and a first terminal of a capacitor;

for number B_lTo B_N-1Each switch block B_iThe method comprises the following steps:

at the first terminal of the capacitor and B_i+1A second solid state switch between the first terminals of the capacitors; and

switch block B_NThe method comprises the following steps:

a third solid state switch between the first terminal of the capacitor and the second converter input terminal of the switch block.

12. The power supply of claim 10, comprising at least three switch blocks, wherein:

for odd values of i, B_iThe switching block includes a tank circuit having a capacitor and an inductor coupled in series; and

for even values of i, B_iThe switching block includes a capacitor.

13. The power supply of claim 12, wherein:

switch block B_lThe method comprises the following steps:

a first solid state switch between the first converter input terminal of the switching block and a first terminal of the capacitor or tank circuit;

for number B_lTo B_N-1Each switch block B_iThe method comprises the following steps:

at the first terminal of the capacitor or tank circuit and B_i+1A second solid state switch between the first terminals of the capacitor or tank circuit; and

switch block B_NThe method comprises the following steps:

a third solid state switch between the second converter input terminal of the switch block and the first terminal of the capacitor or tank circuit.

14. The power supply of claim 10, wherein:

the first regulator output terminal is connected to the first converter output terminal of at least a second one of the unregulated voltage converters, and the second regulator output terminal is connected to the second converter output terminal of the second unregulated voltage converter.

15. The power supply of claim 10, wherein the voltage regulator is a first voltage regulator, the power supply comprising:

a second voltage regulator coupled to the unregulated voltage bus and producing a second regulated voltage across a third regulator output terminal and a fourth regulator output terminal,

wherein the third regulator output terminal is connected to the first converter output terminal of at least a second of the unregulated voltage converters, and the fourth regulator output terminal is connected to the second converter output terminal of the second unregulated voltage converter to yield a second regulated output voltage across a third power supply output terminal and a fourth power supply output terminal.

16. The power supply of claim 10, wherein each switch block comprises:

a first solid state switch between the first converter input terminal of the switch block and a first terminal of a capacitor;

a second solid state switch between the second converter input terminal of the switch block and the first terminal of the capacitor;

a third solid state switch between a second terminal of the capacitor and the first converter output terminal of the switch block; and

a fourth solid state switch between the second terminal of the capacitor and the second converter output terminal of the switch block,

wherein, number B₂To B_NIs coupled to a shunt capacitor.

17. The power supply of claim 10, wherein each switch block comprises:

a first solid state switch between the first converter input terminal of the switch block and a first terminal of a capacitor;

a second solid state switch between the second converter input terminal of the switch block and the first terminal of the capacitor;

a third solid state switch between a second terminal of the capacitor and the first converter output terminal of the switch block; and

a fourth solid state switch between the second terminal of the capacitor and the second converter output terminal of the switch block,

wherein for even values of i, B_iThe first converter output terminal of the switch block is coupled to at least one odd-numbered B_jSaid second converter output terminal of the switch block, and B_iThe second converter output terminal of the switch block is coupled to the at least one odd-numbered B_jThe first converter output terminal of the switching block.

18. A method of generating a regulated power supply, comprising:

receiving a voltage supply input at least one of one or more unregulated voltage converters, each unregulated voltage converter including a switching block having a first converter output terminal and a second converter output terminal;

generating, with each of the unregulated voltage converters, an output voltage across the first converter output terminal and the second converter output terminal;

obtaining an unregulated voltage bus from at least one of the unregulated voltage converters;

providing the unregulated voltage bus to a voltage regulator;

generating, with the voltage regulator, a regulated voltage across a first regulator output terminal and a second regulator output terminal; and

producing a regulated output voltage across a first power output terminal and a second power output terminal, wherein:

the first power supply output terminal is connected to the first regulator output terminal and the first converter output terminal of at least one of the unregulated voltage converters, an

The second power supply output terminal is connected to the second regulator output terminal and the second converter output terminal of the at least one unregulated voltage converter.

19. The method of claim 18, comprising:

providing the unregulated voltage bus to a second voltage regulator;

generating, with the second voltage regulator, a second regulated voltage across a third regulator output terminal and a fourth regulator output terminal; and

producing a second regulated output voltage across the third power supply output terminal and the fourth power supply output terminal, wherein:

the third power supply output terminal is connected to the third regulator output terminal and to the first converter output terminal of at least a second of the unregulated voltage converters, an

The fourth power supply output terminal is connected to the fourth regulator output terminal and the second converter output terminal of the second unregulated voltage converter.

20. The method of claim 18, wherein:

the first power supply output terminal is connected to the first converter output terminals of at least two unregulated voltage converters; and

the second power supply output terminal is connected to the second converter output terminals of the at least two unregulated voltage converters.

Background

Many power supply applications require a regulated (constant) output voltage. Unregulated DC-DC voltage converters can be much smaller and cheaper than regulated voltage converters; however, adjusting the output of the unregulated voltage converter by passing the output through the voltage regulator in a two-stage or cascade arrangement may offset the cost and size advantages of using an unregulated voltage converter.

Disclosure of Invention

At least one aspect relates to a power supply. The power supply includes one or more unregulated voltage converters. Each unregulated voltage converter includes a switch block that generates an output voltage across a first converter output terminal and a second converter output terminal. The power supply includes a voltage supply input coupled to at least one of the unregulated voltage converters. The power supply includes an unregulated voltage bus coupled to at least one of the unregulated voltage converters. The power supply includes a voltage regulator coupled to the unregulated voltage bus and producing a regulated voltage across a first regulator output terminal and a second regulator output terminal. The first regulator output terminal is connected to a first converter output terminal of at least one of the unregulated voltage converters, and the second regulator output terminal is connected to a second converter output terminal of the at least one unregulated voltage converter to yield a regulated output voltage across the first and second power supply output terminals.

In some embodiments, each switch block may include a first solid state switch between the first input terminal of the switch block and the first terminal of the capacitor. Each switch block may include a second solid state switch between the second input terminal of the switch block and the second terminal of the capacitor. Each switching block may comprise a third solid state switch between the first terminal of the capacitor and the first converter output terminal of the switching block. Each switch block may include a fourth solid state switch between the second terminal of the capacitor and the second converter output terminal of the switch block.

In some embodiments, each switch block may include a first solid state switch between the first input terminal of the switch block and the first terminal of the capacitor. Each switch block may include a second solid state switch between the second input terminal of the switch block and the first terminal of the capacitor. Each switch block may comprise a third solid state switch between the second terminal of the capacitor and the first converter output terminal of the switch block. Each switch block may include a fourth solid state switch between the second terminal of the capacitor and the second converter output terminal of the switch block. In some embodiments, the third and fourth solid state switches may have a voltage rating that is less than a maximum input voltage of the voltage supply input and greater than or equal to the regulated output voltage.

In some embodiments, each switching block may include a tank circuit including a capacitor coupled in series to an inductor, the tank circuit having a first terminal and a second terminal. Each switching block may include a first solid state switch between a first input terminal of the switching block and a first terminal of the tank circuit. Each switching block may include a second solid state switch between the second input terminal of the switching block and the second terminal of the tank circuit. Each switching block may comprise a third solid state switch between the first terminal of the tank circuit and the first converter output terminal of the switching block. Each switching block may include a fourth solid state switch between the second terminal of the tank circuit and the second converter output terminal of the switching block.

In some embodiments, each switching block may include a tank circuit including a capacitor coupled in series to an inductor, the tank circuit having a first terminal and a second terminal. Each switching block may include a first solid state switch between a first input terminal of the switching block and a first terminal of the tank circuit. Each switching block may include a second solid state switch between the second input terminal of the switching block and the first terminal of the tank circuit. Each switching block may comprise a third solid state switch between the second terminal of the tank circuit and the first converter output terminal of the switching block. Each switching block may include a fourth solid state switch between the second terminal of the tank circuit and the second converter output terminal of the switching block. In some embodiments, the third and fourth solid state switches may have a voltage rating that is less than a maximum input voltage of the voltage supply input and greater than or equal to the regulated output voltage.

In some embodiments, the voltage regulator may have a non-inverting buck-boost configuration.

In some embodiments, the voltage regulator may have an inverting buck-boost configuration.

In some embodiments, the power source may include a number B_lTo B_NN switching blocks. Each switch block may have a first converter input terminal and a second converter input terminal. The voltage supply input may be coupled to B_lA first converter input terminal of the switch block. An unregulated voltage bus may be coupled to B_NA second converter input terminal of the switch block. For number B₂To B_NEach switch block of, B_iFirst converter of switch blockThe input terminal can be coupled to B_i-1A second converter input terminal of the switch block.

In some embodiments, the power supply may include at least three switch blocks, among others. Switch block B_lA first solid state switch may be included between the first converter input terminal of the switch block and the first terminal of the capacitor. For number B_lTo B_N-1Each switch block B_iMay be included at the first terminal of the capacitor and B_i+1A second solid state switch between the first terminals of the capacitors. Switch block B_NA third solid state switch may be included between the first terminal of the capacitor and the second converter input terminal of the switch block.

In some embodiments, the power supply may include at least three switch blocks. For odd values of i, B_iThe switching block may include a tank circuit having a capacitor and an inductor coupled in series. For even values of i, B_iThe switching block may include a capacitor. In some embodiments, the switch block B_lA first solid state switch may be included between the first converter input terminal of the switching block and the first terminal of the capacitor or tank circuit. For number B_lTo B_N-1Each switch block B_iMay be included in the first terminal of the capacitor or tank circuit and B_i+1A second solid state switch between the first terminals of the capacitor or tank circuit. Switch block B_NA third solid state switch may be included between the second converter input terminal of the switching block and the first terminal of the capacitor or tank circuit.

In some embodiments, the first regulator output terminal is connected to a first converter output terminal of at least a second one of the unregulated voltage converters, and the second regulator output terminal is connected to a second converter output terminal of the second unregulated voltage converter.

In some embodiments, the voltage regulator may be a first voltage regulator. The power supply may include a second voltage regulator coupled to the unregulated voltage bus and producing a second regulated voltage across the third regulator output terminal and the fourth regulator output terminal. The third regulator output terminal may be connected to a first converter output terminal of at least a second one of the unregulated voltage converters, and the fourth regulator output terminal may be connected to a second converter output terminal of the second unregulated voltage converter to yield a second regulated output voltage across the third and fourth power supply output terminals.

In some embodiments, each switch block may include a first solid state switch between a first converter input terminal of the switch block and a first terminal of a capacitor. Each switch block may include a second solid state switch between the second converter input terminal of the switch block and the first terminal of the capacitor. Each switch block may comprise a third solid state switch between the second terminal of the capacitor and the first converter output terminal of the switch block. Each switch block may include a fourth solid state switch between the second terminal of the capacitor and the second converter output terminal of the switch block. Number B₂To B_NMay be coupled to a shunt capacitor.

In some embodiments, each switch block may include a first solid state switch between a first converter input terminal of the switch block and a first terminal of a capacitor. Each switch block may include a second solid state switch between the second converter input terminal of the switch block and the first terminal of the capacitor. Each switch block may comprise a third solid state switch between the second terminal of the capacitor and the first converter output terminal of the switch block. Each switch block may include a fourth solid state switch between the second terminal of the capacitor and the second converter output terminal of the switch block. For even values

The first converter output terminal of the switch block may be coupled to at least one odd-numbered B_jA second converter output terminal of the switch block, and B_iThe second converter output terminal of the switch block may be coupled to at least one odd-numbered B_jA first converter output terminal of the switch block.

At least one aspect relates to a method. The method comprises the following steps: a voltage supply input is received at least one of one or more unregulated voltage converters, each unregulated voltage converter including a switch block having a first converter output terminal and a second converter output terminal. The method comprises the following steps: with each of the unregulated voltage converters, an output voltage is generated across the first converter output terminal and the second converter output terminal. The method comprises the following steps: an unregulated voltage bus is taken from at least one of the unregulated voltage converters. The method comprises the following steps: an unregulated voltage bus is provided to a voltage regulator. The method comprises the following steps: a regulated voltage is generated across the first regulator output terminal and the second regulator output terminal using the voltage regulator. The method comprises the following steps: a regulated output voltage is produced across the first power output terminal and the second power output terminal. The first power supply output terminal is connected to the first regulator output terminal and a first converter output terminal of at least one of the unregulated voltage converters. The second power supply output terminal is connected to the second regulator output terminal and to a second converter output terminal of the at least one unregulated voltage converter.

In some embodiments, the method may comprise: an unregulated voltage bus is provided to a second voltage regulator. The method can comprise the following steps: with the second voltage regulator, a second regulated voltage is generated across the third regulator output terminal and the fourth regulator output terminal. The method can comprise the following steps: a second regulated output voltage is produced across the third power supply output terminal and the fourth power supply output terminal. The third power supply output terminal is connected to the third regulator output terminal and to the first converter output terminal of at least a second one of the unregulated voltage converters. The fourth power supply output terminal is connected to the fourth regulator output terminal and to the second converter output terminal of the second unregulated voltage converter.

In some embodiments, the first power supply output terminal is connected to a first converter output terminal of the at least two unregulated voltage converters, and the second power supply output terminal is connected to a second converter output terminal of the at least two unregulated voltage converters.

These and other aspects and embodiments are discussed in detail below. The foregoing information and the following detailed description include illustrative examples of various aspects and embodiments, and provide an overview or framework for understanding the nature and character of the claimed aspects and embodiments. The accompanying drawings provide an illustration and a further understanding of the various aspects and embodiments, and are incorporated in and constitute a part of this specification.

Drawings

The drawings are not intended to be drawn to scale. Like reference numbers and designations in the various drawings indicate like elements. For purposes of clarity, not every component may be labeled in every drawing.

In the drawings:

1A-1D show simplified schematic diagrams of an example unregulated voltage converter switching block in accordance with an illustrative embodiment;

2A-2D illustrate schematic diagrams of example unregulated voltage converter switch blocks in accordance with an illustrative embodiment;

FIG. 3 shows a symbolic representation of an unregulated voltage converter switch block in accordance with an illustrative embodiment;

FIG. 4 shows a simplified schematic diagram of a power supply architecture with multiple independent regulated outputs in accordance with an illustrative embodiment;

FIG. 5 shows a simplified schematic diagram of a power supply architecture with combined regulated outputs in accordance with an illustrative embodiment;

FIG. 6 shows a simplified schematic diagram of a power supply architecture with combined regulated outputs in accordance with an illustrative embodiment;

FIG. 7 shows a simplified schematic diagram of a power supply architecture with an output in parallel with a voltage bus in accordance with an illustrative embodiment;

FIG. 8 shows a schematic diagram of a power supply architecture with a single regulated output in accordance with an illustrative embodiment;

FIG. 9 shows a schematic diagram of a power supply architecture with a single regulated output in accordance with an illustrative embodiment;

FIG. 10 shows a schematic diagram of a power supply architecture with two independent regulated outputs in accordance with an illustrative embodiment; and

FIG. 11 shows a flowchart depicting an example method of generating a regulated power supply in accordance with an illustrative embodiment.

Detailed Description

The following is a description of various concepts and embodiments thereof related to systems and methods for supplying power using parallel voltage regulators using switched capacitors or capacitor-inductor blocks. The various concepts introduced above and discussed in more detail below may be implemented in any of numerous ways, as the described concepts are not limited to implementation in any particular manner. Examples of specific embodiments and applications are provided primarily for illustrative purposes.

The present disclosure relates generally to parallel voltage regulator architectures using switched capacitors or capacitor-inductor ("LC" or "tank") blocks. Certain power supply applications may benefit from high density and efficient direct current to direct current (DC-DC) power conversion. However, achieving the desired density and efficiency becomes challenging when the application requires regulation of the output voltage.

For example, a regulated DC-DC converter is relatively large and expensive. While unregulated voltage converters can be smaller and cheaper, regulating their output traditionally requires that the entire output flow through the voltage regulator. This two-stage, cascaded configuration has at least two disadvantages. First, the voltage regulator must be rated for the full output power of the power supply, making it relatively large and expensive. Second, the cascaded configuration produces a cumulative effect on power loss through the unregulated voltage converter and the voltage regulator. For example, if the efficiency of the unregulated voltage converter is 95% and the efficiency of the voltage regulator is 90%, the overall efficiency of the power supply will be 0.95 x 0.90-86%.

The present disclosure proposes a power supply based on a parallel rather than cascaded arrangement of an unregulated voltage converter and a voltage regulator. For example, the power supply of the present disclosure may have a relatively small and efficient unregulated voltage converter and voltage regulator arranged in parallel with the output of the unregulated voltage converter and voltage regulator. In this arrangement, the voltage regulator only needs to handle the power necessary to regulate the output of the unregulated voltage converter. Moreover, the overall efficiency of the system will be based on the power supplied by each part of the power supply to estimate a weighted average of the respective efficiencies. For example, if the unregulated voltage converter provides 70% of the output power at 95% efficiency and the voltage regulator provides 30% of the output power at 90% efficiency, then the overall efficiency of the power supply will be 0.95 × 0.70+0.90 × 0.30 — 0.67+0.27 — 94% efficiency. The resulting power supply is smaller and less expensive than a cascade arrangement and exhibits less heat dissipation.

Fig. 1A-1D show simplified schematic diagrams of example unregulated voltage converter switch blocks 100a-100D (collectively "switch blocks 100") according to an illustrative embodiment. The switch blocks 100 may be in a series configuration (e.g., switch blocks 100a and 100b) or a parallel configuration (e.g., switch blocks 100c and 100 d). The switch blocks 100a and 100c include capacitors 110a or 110c, respectively. Switching blocks 100b and 100d include capacitor-inductor ("LC" or "tank") circuits consisting of capacitors 110b or 100d in series with inductors 120b or 120d, respectively. Each switch block 100 includes two Single Pole Double Throw (SPDT) switches 130a-130d and 140a-140d (collectively "switches 130 and 140"). Each switch block 100 includes input terminals 150a-150d and 160a-160d (collectively, "input terminals 150 and 160") and output terminals 170a-170d and 180a-180d (collectively, "output terminals 170 and 180"). The switches 130 and 140 are controlled by Pulse Width Modulators (PWMs) 132a-132d and 142a-140d, respectively (collectively "PWMs 132 and 142").

Fig. 1A shows a switch block 100a that includes a capacitor 110a in a series configuration. The SPDT switch 130a electrically couples the first input terminal 150a or the second input terminal 160a to the first terminal of the capacitor 110 a. The SPDT switch 140a electrically couples the second terminal of the capacitor 110a to either the first output terminal 170a or the second output terminal 180 a. Switch 130a may operate under the control of PWM132a, and switch 140a may operate under the control of PWM 142 a. In some embodiments, the functions of the PWMs 132a and 142a may be performed by a single PWM. The input reference ground and the output reference ground (i.e., the potentials at terminals 160a and 180a, respectively) may have offset voltage levels. The switch block 100a may include an additional voltage source 190a to complete a circuit loop between the reference grounds of the terminals 160a and 180a and to set the voltage offset between the two.

Fig. 1B shows a switch block 100B that includes an "LC" or "tank" circuit in a series configuration. The tank circuit includes a capacitor 110b and an inductor 120b connected in series. The SPDT switch 130b electrically couples either the first input terminal 150b or the second input terminal 160b to the first terminal of the tank circuit. The SPDT switch 140b electrically couples the second terminal of the tank circuit to either the first output terminal 170b or the second output terminal 180 b. Switch 130b may operate under control of PWM132 b, and switch 140b may operate under control of PWM 142 b. In some embodiments, the functions of the PWMs 132b and 142b may be performed by a single PWM. The input reference ground and the output reference ground (i.e., the potentials at terminals 160b and 180b, respectively) may have offset voltage levels. The switch block 100b may include an additional voltage source 190b to complete a circuit loop between the reference grounds of terminals 160b and 180b and to set the voltage offset between the two.

Fig. 1C shows a switch block 100C that includes a capacitor 110C in a parallel configuration. The SPDT switch 130c electrically couples the first input terminal 150c or the first output terminal 170c to the first terminal of the capacitor 110 c. The SPDT switch 140c electrically couples the second terminal of the capacitor 110c to the second input terminal 160c or the second output terminal 180 c. Switch 130c may operate under the control of PWM132c, and switch 140c may operate under the control of PWM 142 c. In some embodiments, the functions of the PWMs 132c and 142c may be performed by a single PWM.

Fig. 1D shows a switch block 100D that includes tank circuits in a parallel configuration. The tank circuit includes a capacitor 110d and an inductor 120d connected in series. The SPDT switch 130d electrically couples the first input terminal 150d or the first output terminal 170d to a first terminal of the tank circuit. The SPDT switch 140d electrically couples the second terminal of the tank circuit to the second input terminal 160d or the second output terminal 180 d. Switch 130d may operate under control of PWM132d, and switch 140d may operate under control of PWM 142 d. In some embodiments, the functions of the PWMs 132d and 142d may be performed by a single PWM.

The switch block 100 may convert the DC voltage across the input terminals 150 and 160 to a DC voltage across the output terminals 170 and 180. In some embodiments, the DC input voltage may be converted to the DC output voltage at a 1:1 ratio. In some embodiments, the ratio may be higher or lower. In some embodiments, the PWMs 132 and 142 operate without feedback or control so that the ratio remains constant during operation of the switching block. Thus, the output voltage, i.e., the voltage across output terminals 170 and 180, will remain proportional to the input voltage, i.e., the voltage across input terminals 150 and 160, and the output voltage will vary with the input voltage. Thus, the switching block 100 operates as an unregulated DC-DC voltage converter.

Fig. 2A-2D show schematic diagrams of example unregulated voltage converter switch blocks 200 a-200D (collectively "switch blocks 200") according to an illustrative embodiment. The switch block 200 is similar in structure and function to the switch block 100 previously described. However, the switch block 200 is described in terms of the solid state switches that make up the SPDT switches 130 and 140. The solid state switches include solid state switches 230a-230d, 235a-235d, 240a-240d, and 245a-245d (collectively referred to as "solid state switch 230", "solid state switch 235", "solid state switch 240", "solid state switch 245", respectively). The solid state switches 230, 235, 240, and 245 may be transistors, Field Effect Transistors (FETs), metal oxide semiconductor FETs (mosfets), solid state relays, Insulated Gate Bipolar Transistors (IGBTs), or any controllable semiconductor switching components, respectively. The solid state switches 230, 235, 240 and 245 may be arranged in pairs to perform the functions of the SPDT switches 130 and 140 previously described. The solid state switches 230, 235, 240, and 245 may be driven by two Pulse Width Modulator (PWM) control signals. The PWMs 232a-232d and 242a-242d (collectively "PWM 232" and "PWM 242") may provide PWM control signals to the solid state switches 230 and 235 and the solid state switches 240 and 245, respectively. In some embodiments, the functions of the PWMs 232 and 242 may be combined into a single PWM. In some implementations, additional components such as buffers and/or inverters may be used to provide PWM control signals to each of the solid state switches 230, 235, 240, and 245 based on one or more signals provided by the PWM. The PWM control signals to the pair of solid state switches 230 and 235 or solid state switches 240 and 245 may be complementary signals (i.e., one logic high and the other logic low) having a duty cycle of about 50%. In some embodiments, the frequency of the PWM control signal may be from several hundred hertz to several tens of megahertz. In some embodiments, the frequency of the PWM control signal may be from tens of kilohertz to megahertz. In some embodiments, the frequency of the PWM control signal may be from about 100 khz to 1 mhz.

Fig. 2A shows a schematic diagram of an example unregulated voltage converter switching block 200 a. The switch block 200a includes a first input terminal 250a and a second input terminal 260 a. The solid-state switch 230a controllably couples the first input terminal 250a to a first terminal of the capacitor 210 a. The solid state switch 235a controllably couples the second input terminal 260a to the first terminal of the capacitor 210 a. PWM232 a provides a PWM control signal and a complementary PWM control signal to solid state switches 230a and 235a, respectively. The switching block 200a includes a first output terminal 270a and a second output terminal 280 a. The solid-state switch 240a controllably couples the first output terminal 270a to the second terminal of the capacitor 210 a. The solid state switch 245a controllably couples the second output terminal 280a to the second terminal of the capacitor 210 a. PWM 242a provides PWM control signals and complementary PWM control signals to solid state switches 240a and 245a, respectively. In some embodiments, the functionality of the PWMs 232a and 242a may be combined into a single PWM.

Fig. 2B shows a schematic diagram of an example unregulated voltage converter switching block 200B. The switch block 200b includes a first input terminal 250b and a second input terminal 260 b. The solid state switch 230b controllably couples the first input terminal 250b to a first terminal of a tank circuit that includes a capacitor 210b connected in series to an inductor 220 b. A solid state switch 235b controllably couples the second input terminal 260b to the first terminal of the tank circuit. PWM232b provides PWM control signals and complementary PWM control signals to solid state switches 230b and 235b, respectively. The switching block 200b includes a first output terminal 270b and a second output terminal 280 b. Solid state switch 240b controllably couples first output terminal 270b to the second terminal of the tank circuit. A solid state switch 235b controllably couples the second output terminal 280b to a second terminal of the tank circuit. PWM 242b provides PWM control signals and complementary PWM control signals to solid state switches 240b and 245b, respectively. In some embodiments, the functions of the PWMs 232b and 242b may be combined into a single PWM.

In embodiments of power supplies using switch blocks 200a and 200b, the solid state switches need not handle the full input voltage of the power supply. Rather, they may only need to be rated for the desired regulated output voltage. Thus, standard low voltage components may be used for such power supplies. For example, if the regulated output voltage is 12V, the solid state switch may be a standard 12 VMOSFET.

Fig. 2C shows a schematic diagram of an example unregulated voltage converter switching block 200C. The switch block 200c includes a first input terminal 250c and a second input terminal 260 c. The solid state switch 230c controllably couples the first input terminal 250c to a first terminal of the capacitor 210 c. The solid state switch 240c controllably couples the second input terminal 260c to the second terminal of the capacitor 210 c. The switching block 200c includes a first output terminal 270c and a second output terminal 280 c. Solid state switch 235c controllably couples first output terminal 270c to a first terminal of capacitor 210 c. The solid state switch 245c controllably couples the second output terminal 280a to a second terminal of the capacitor 210 c. PWM232 c provides PWM control signals and complementary PWM control signals to solid state switches 230c and 235c, respectively. PWM 242c provides PWM control signals and complementary PWM control signals to solid state switches 240c and 245c, respectively. In some embodiments, the functionality of the PWMs 232c and 242c may be combined into a single PWM.

Fig. 2D shows a schematic diagram of an example unregulated voltage converter switching block 200D. The switch block 200d includes a first input terminal 250d and a second input terminal 260 d. The solid state switch 230d controllably couples the first input terminal 250d to a first terminal of a tank circuit that includes a capacitor 210d connected in series to an inductor 220 d. Solid state switch 240d controllably couples second input terminal 260d to a second terminal of the tank circuit. The switch block 200d includes a first output terminal 270d and a second output terminal 280 d. A solid state switch 235d controllably couples the first output terminal 270d to a first terminal of the tank circuit. The solid state switch 245d controllably couples the second output terminal 280d to a second terminal of the tank circuit. PWM232d provides a PWM control signal and a complementary PWM control signal to solid state switches 230d and 235d, respectively. PWM 242d provides PWM control signals and complementary PWM control signals to solid state switches 240d and 245d, respectively. In some embodiments, the functions of the PWMs 232d and 242d may be combined into a single PWM.

FIG. 3 shows a symbolic representation of an unregulated voltage converter switch block 300 in accordance with an illustrative embodiment. Each of the switch blocks 100 or 200 described with reference to fig. 1 and 2 may be symbolized by a switch block 300. The symbol is similar to a transformer; however, the switching block 300 is intended to convert a dc voltage (including ac ripple that may be present). While either of the previously described switch blocks 100 or 200 may perform the desired function of the wider circuit for which it is a component, the switch block 300 may be used to represent a general switch block. A power supply according to the present disclosure may include a plurality of switch blocks 100 and/or 200, including combinations of different types of switch blocks 100 and/or 200. As with switch blocks 100 and 200, in some embodiments, the input and output reference voltages may be offset or biased; i.e. they do not need to share a common ground.

The switch block 300 includes a first input terminal 350, a second input terminal 360, a first output terminal 370, and a second output terminal 380. Each may represent one of the following: a first input terminal 150 or 250, a second input terminal 160 or 260, a first output terminal 170 or 270, or a second output terminal 180 or 280.

FIG. 4 shows a simplified schematic diagram of a power supply 400 architecture with multiple independent regulated outputs 450a-450n in accordance with an illustrative embodiment. The power supply 400 receives an input voltage 410, which input voltage 410 is fed in series through each of the switch blocks 440a to 440n (collectively "switch blocks 440"). That is, the input voltage is connected to the first input terminal of the first switching block 440 a. The second input terminal of the first switching block 440a is connected to the first input terminal of the second switching block 440b, the second input terminal of the second switching block 440b is connected to the first input terminal of the next switching block 440, and so on. A second input terminal of the last switch block 440n is connected to the unregulated voltage bus 420. The unregulated voltage bus 420 is connected to one or more voltage regulators 460a-460n (collectively, "voltage regulators 460") that regulate the output voltage of the switching block 440.

In the example power supply 400, a second output terminal of each switch block 440 is connected to ground 430. Accordingly, each output 450a-450N (collectively "outputs 450") may provide an output voltage V _1-V _ N, respectively, at each first output terminal of each switch block 440 with reference to a ground potential.

The input of each voltage regulator 460 is connected to the unregulated voltage bus 420. Each voltage regulator 460 may provide a different output voltage 450. For example, but not limiting of, in some embodiments, the voltage regulator 460a may have an output voltage V _ l of 12V, the voltage regulator 460b may have an output voltage V _2 of 18V and the voltage regulator 460N may have an output voltage V _ N of 24V. In some embodiments, each voltage regulator 460 may have an output voltage of 12 volts. In some embodiments, outputs 450 may be connected in parallel.

In some embodiments, each output voltage may have a different value (i.e., V _1 ≠ V _2 ≠ V _ N, etc.). In some embodiments, the output of each switching block 440 may be regulated by a respective voltage regulator 460. For example, voltage regulator 460a may regulate the output of switch block 450a to a voltage value of V _ l, voltage regulator 460b may regulate the output of switch block 450b to a voltage value of V _2, and so on.

In some embodiments, each output voltage may have the same value (i.e., V _1 ═ V _2 ═ V _ N, etc.). In some embodiments, the outputs of all switch blocks 440 may be connected in parallel and their output voltages may be regulated by a single voltage regulator 460.

In some embodiments, some, but not all, of the output voltages 450 may have the same value (e.g., V _1 ≠ V _ N, etc.). As described above, switch blocks 440 having equal or substantially equal regulated output voltage levels may be connected in parallel. In some embodiments, the power supply 400 may include a voltage regulator 460 for each desired output voltage value.

Generally, there is a relationship between the voltages of the power supplies 400. Specifically, the sum of V _1, V _2,. V _ N may be equal to the difference between VIN and VBUS. Namely: VIN-VBUS ═ SUM { V _1, V _2,.. V _ N }. VIN may vary based on the power supply to the power supply 400, and the regulated outputs V _1, V _2,.. V _ N may be held substantially constant by the voltage regulator 460, and thus VBUS may vary with VIN according to the formula VBUS-VIN-SUM { V _1, V _2,. V _ N }. Thus, based on the above equations, the type of voltage regulator selected for use as voltage regulator 460 may depend on the desired regulated voltage and the expected range of VBUS. For example, but not limiting of, the voltage converter 460 may have a buck or step-down converter design if VBUS is expected to always have a higher voltage of the same polarity relative to the regulated voltage during normal operation. The voltage converter 460 may have a boost converter design if VBUS is expected to always have a lower voltage of the same polarity relative to the regulated voltage during normal operation. The voltage converter 460 may have a non-inverting buck-boost converter design if it is expected that VBUS may vary between higher and lower voltages of the same polarity relative to the regulated voltage during normal operation. If it is expected that VBUS may vary between higher and lower voltage magnitudes relative to the regulated voltage but with opposite polarity during normal operation, then the voltage converter 460 may have an inverting buck-boost converter design. Other DC-DC converter designs may be used depending on the desired output voltage 460 and the expected range of voltages on the unregulated voltage bus 420. Each voltage regulator 460 may include its own feedback loop and controller by which its own output voltage is regulated. In regulating the output voltage of the switching block 440, the voltage regulator 460 may deliver power to each output load in parallel with the switching block 440. The switch block 440 may operate with greater efficiency and density relative to the voltage regulator 460. Although the voltage regulator 460 may operate at a relatively low efficiency and density, the voltage regulator 460 provides only a portion of the power to the load, while the switching block 440 provides the remaining power. Thus, the overall converter efficiency and density may be higher than a two-stage converter architecture in which all power delivered to the load must pass through the voltage regulator.

In some embodiments, the input side of the switching block 440 is connected in series between the voltage input 410 and the unregulated voltage bus 420. Thus, the voltage across the input terminals of each converter will be equal to the difference between VIN and VBUS divided by the number of switch blocks. In addition, each of the switch blocks 440 may have a voltage conversion ratio of 1:1 (although the precise output voltage will be regulated by the voltage regulator 460). Thus, the input voltage of each switch block 440 will be a fraction of VIN, and the output voltage of each switch block 440 will be close to the input voltage. In embodiments where the switch block 440, such as the switch blocks 220a and 220b previously described, has a series configuration, the solid state switches need only be rated for the desired regulated output voltage. Accordingly, the switch block 440 may comprise a standard low voltage solid state switch. For example, if the regulated output voltage is 12V, the solid state switch may be a standard 12V MOSFET. A solid state switch rated for low voltage may be smaller and less expensive than components rated for the full input voltage VIN, which may reach or exceed 60V. Thus, in embodiments employing switch blocks 220a and 220b arranged with their input terminals connected in series between the voltage input 410 and the unregulated voltage bus 420, the power supply 400 may be smaller and less expensive than solid state switches that need to be rated for all VIN.

Fig. 5 shows a simplified schematic diagram of a power supply 500 architecture with a combined regulated output 550a in accordance with an illustrative embodiment. Power supply 500 is similar to power supply 400 previously described; however, the power supply 500 has the outputs of its two switch blocks 540a and 540b connected in parallel as a single output 550 a. The power supply 500 receives an input voltage 510, which input voltage 510 is fed in series through each of the switch blocks 540a-540n (collectively "switch blocks 540"). That is, the input voltage is connected to the first input terminal of the first switch block 540 a. The second input terminal of the first switch block 540a is connected to the first input terminal of the second switch block 540b, the second input terminal of the second switch block 540b is connected to the first input terminal of the next switch block 540, and so on. A second input terminal of the last switch block 540n is connected to the unregulated voltage bus 520. The unregulated voltage bus 520 is connected to one or more voltage regulators 560a-560n (collectively "voltage regulators 560") that regulate the output voltage of the switch block 540.

In the example power supply 500, a second output terminal of each switch block 540 is connected to ground 530. Accordingly, each output 550a-550N (collectively "outputs 550") may provide an output voltage V _1-V _ N, respectively, at each first output terminal of each switch block 540 with reference to a ground potential.

In the example power supply 500, the outputs of the switch blocks 540a and 540b are connected in parallel. That is, a first output terminal of the switch block 540a is connected to a first output terminal of the switch block 540b, and a second output terminal of the switch block 540a is connected to a second output terminal of the switch block 540b and the ground 530. The parallel outputs of switch blocks 540a and 540b may be regulated by a single voltage regulator 560a to an output voltage of V _ l. In some embodiments, additional switch blocks 540 may be connected in parallel, each contributing additional power to output 550 a. The power output by the switch block 540 connected to output 550a may all be regulated by a single voltage regulator 560 a. Although the power handling components of voltage regulator 560a may need to be larger to regulate additional output power, the feedback and switching electronics of voltage regulator 560a need not be expanded. Thus, an increased ratio of switching blocks 540 to voltage regulator 560 may increase the density of power supply 500.

Similar to power supply 400, there is a relationship between the voltages of power supply 500. Specifically, the sum of the output voltages V _ l to V _ N may be equal to the difference between VIN and VBUS. Namely: VIN-VBUS ═ SUM { V _ 1.. V _ N }. Thus, in the power supply 500, VBUS can be obtained according to the formula VBUS VIN-SUM {2 × V _1, V _2.. V _ N }. One type of voltage regulator 560 may be selected based on the same constraints described above for the voltage regulator 460 of the power supply 400.

Fig. 6 shows a simplified schematic diagram of a power supply 600 architecture with combined regulated outputs in accordance with an illustrative embodiment. Power supply 600 is similar to power supply 400 previously described; however, in power supply 600, output 650a of switch block 640a is connected to an input of switch block 640 b.

The power supply 600 receives an input voltage 610, which input voltage 610 is fed in series through each of the switch blocks 640a-640n (collectively "switch blocks 640"). That is, the input voltage is connected to the first input terminal of the first switch block 640 a. The second input terminal of the first switch block 640a is connected to the first input terminal of the second switch block 640b, the second input terminal of the second switch block 640b is connected to the first input terminal of the next switch block 640, and so on. A second input terminal of the last switch block 640n is connected to the unregulated voltage bus 620. The unregulated voltage bus 620 may be connected to inputs of one or more voltage regulators that regulate the output voltage of the switch block 640 in the same manner as previously described for the power supplies 400 and 500.

Each switch block 640 of power supply 600 has an output 650a-650n (collectively "outputs 650"). In the example power supply 600, a second output terminal of each switch block 640b-640n is connected to ground 630. Thus, each output 650b-650n provided at each first output terminal of the switch block 640 may provide an output voltage referenced to ground potential.

In the example power supply 600, the output 650a of the first switch block 640a is connected to the input of the second switch block 650 b. That is, a first output terminal of the output 650a is connected to a first input terminal of the second switch block 640b, and a second output terminal of the output 650a is connected to a second input terminal of the second switch block 640 b. In this configuration, V _1 is V _2 as in the configuration of the power supply 500. Thus, the voltage of the unregulated voltage bus will be: VBUS-SUM {2 × V _1, V _2.. V _ N }.

FIG. 7 shows a simplified schematic diagram of a power supply 700 architecture with an output 750a in parallel with an unregulated voltage bus 720 in accordance with an illustrative embodiment. In power supply 700, output 750a of first switch block 740a is connected in parallel with unregulated voltage bus 720.

The power supply 700 receives an input voltage 710, which input voltage 710 is fed in series through each of the switch blocks 740a-740n (collectively "switch blocks 740"). That is, the input voltage is connected to a first input terminal of a first switch block 740a, a second input terminal of the first switch block 740a is connected to a first input terminal of a second switch block 740b, a second input terminal of the second switch block 740b is connected to a first input terminal of a next switch block 640, and so on. A second input terminal of the last switch block 740n is connected to the unregulated voltage bus 720. Unregulated voltage bus 720 is connected to one or more voltage regulators (not shown) that regulate the output voltage of switch block 740 in the same manner as previously described for power supplies 400 and 500.

Each switch block 740 of power supply 700 has an output 750a-750n (collectively "outputs 750"). In the example power supply 700, a second output terminal of each switch block 740a-740n is connected to ground 730. Accordingly, each of the output voltages V _ l to V _ N provided at each of the first output terminals of the switch block 740 is referenced to the ground potential.

Additionally, the unregulated voltage bus 720 is connected to a first output terminal of a first output 750a of a first switch block 740 a. The remaining outputs 750b-750n may be connected to independent voltage sources (voltage regulators). Thus, VBUS — V _1 — 0.5 (VIN-SUM { V _2.. V _ N }).

Fig. 8 shows a simplified schematic diagram of a power supply 800 architecture with a single regulated output 850 in accordance with an illustrative embodiment. Power supply 800 includes three switch blocks 840a, 840b, and 840c (collectively "switch blocks 840"). The inputs of the switching block 840 are connected in series between the input voltage 810 and the unregulated voltage bus 820. The outputs of the switching block 840 are connected in parallel to yield a single output 850 with respect to ground 830. The output voltage VOUT is regulated by a voltage regulator 860.

In power supply 800, each switch block 840 includes a capacitor. When the individual solid state switches of the switch blocks 840 are controlled in the same manner, each switch block 840 may produce an output voltage that is in phase with the other switch blocks 840. In some embodiments, filter capacitors 870a and 870b (collectively "filter capacitors 870") may be added as desired for energy buffering and for maintaining voltage across the solid state switches.

In some embodiments, the input voltage 810VIN may have a nominal value of 54V and a range of approximately 40-60V. The output 850 voltage VOUT may be regulated to 12V. The unregulated voltage bus 820 may therefore operate at a nominal value of 18V, VBUS, ranging from about 4V to 24V. Thus, a non-inverting buck-boost converter may be used as the voltage regulator 860.

In the example power supply 800 and under the example operating parameters described above, the voltage regulator 860 need only carry 1/3 of the total power under steady state conditions under nominal conditions. If each switching block 840 has an efficiency of 98% and the voltage regulator has an efficiency of 96%, the overall efficiency may be 97.3%. In contrast, using a two-stage configuration in which the entire output of the unregulated voltage converter passes through the voltage regulator, the voltage regulator would have to handle twice the power and the efficiency would be 98% 96% 94.1%.

Fig. 9 shows a simplified schematic diagram of a power supply 900 architecture with a single regulated output 950 in accordance with an illustrative embodiment. Power supply 900 is similar to power supply 800; however, in power supply 900, the middle switch block 940b (or, in embodiments with four or more switch blocks, even numbered switch blocks) has Pulse Width Modulator (PWM) logic that is offset 180 degrees from the other switch blocks. This allows the functionality of some solid state switches to be combined into a single solid state switch, such as solid state switches 980a and 980b (collectively "solid state switches").

Power supply 900 includes three switch blocks 940a, 940b, and 940c (collectively "switch blocks 940"). The inputs of the switch block 940 are connected in series between the input voltage 910 and the unregulated voltage bus 920. The outputs of the switch blocks 940 are connected in parallel to yield a single output 950 relative to ground 930. The output voltage VOUT is regulated by a voltage regulator 960.

The switch blocks 940a and 940c include a capacitor and an inductor ("LC" or "tank" circuit) connected in series. The switching block 940b includes a capacitor. In embodiments with four or more switching blocks 940, alternate switching blocks will have capacitors and other switching blocks will have tank circuits. Each switching block 940 may produce an output voltage that is in phase with the other switching blocks 940. However, unlike power supply 800, individual solid state switches are not controlled in the same manner, but alternating switch blocks have PWM logic that is offset 180 degrees from other switch blocks. In this configuration, the solid state switches at the second input terminal of the switch block 940 will open and close in synchronization with the solid state switches at the first input terminal of the next switch block 940. Thus, the two solid state switches may be replaced by a single solid state switch, e.g., solid state switches 980a and 980b, that performs both functions. Incorporating solid state switches in this manner may further reduce the size and increase the density of power supply 900.

An additional advantage of power supply 900 is the combination of capacitor and tank circuit switching block 940. This mixing of capacitors and the tank switch block 940 may allow for resonant operation, which may achieve higher efficiency. For example, the PWM controller of the switching block may be synchronized with the resonant frequency of the tank circuit so that switching occurs at the time of current zero crossing, thereby reducing switching losses. That is, the PWMs may be timed to switch the solid state switches when little or no current flows through them. This may reduce the power dissipated by the solid state switch when transitioning from off to on and back again. The resonant frequency of the tank circuit will depend at least in part on the values of the capacitor and inductor of the tank circuit. Only the switch block of capacitors (i.e., switch block 940b) will include non-resonant capacitors. The value of the non-resonant capacitor may be an order of magnitude or more greater than the value of the resonant capacitors in switch blocks 940a and 940 c. Thus, when the solid state switch 980 connects the non-resonant capacitor, the non-resonant capacitor will have little effect on the resonant frequency of the tank circuit.

Fig. 10 shows a simplified schematic diagram of a power supply 1000 architecture having two independent regulated outputs 1050a and 1050b (collectively "outputs 1050"), according to an illustrative embodiment. The power supply 1000 includes three switch blocks 1040a, 1040b and 1040c (collectively "switch blocks 1040"). The inputs of the switch block 1040 are connected in series between the input voltage 1010 and the unregulated voltage bus 1020. Similar to power supply 900, the middle switch block 1040b (or, in embodiments with four or more switch blocks, alternating switch blocks) has Pulse Width Modulator (PWM) logic that is offset 180 degrees from the other switch blocks. This allows the functionality of some solid state switches to be combined into a single solid state switch, such as solid state switches 1080a and 1080b (collectively "solid state switches").

The outputs of switch block 1040b are connected in parallel to the outputs of switch block 1040a to yield a single output 1050a relative to ground 1030. Output 1050a is also connected in parallel with the output of voltage regulator 1060a, which voltage regulator 1060a regulates the voltage VOUT _ l at output 1050 a. The output 1050b of the switching block 1040c is connected in parallel with the output of a voltage regulator 1060b, which voltage regulator 1060b regulates the voltage VOUT _2 at the output 1050 b.

In some embodiments, the input voltage 1010VIN may have a nominal value of 54V and a range of approximately 40 to 60V. Output 1050a voltage VOUT _ l may be regulated to 12V, and output 1050b voltage VOUT _2 may be regulated to 5V. Thus, the unregulated voltage bus will operate at a nominal voltage VBUS-VIN-2-VOUT _1-VOUT _ 2-54-2-12V-5V-25V nominal, ranging from about 11 to 31V. Thus, in some embodiments, voltage regulator 1060a may use a non-inverting buck-boost converter and voltage regulator 1060b may use a buck converter.

FIG. 11 shows a flowchart depicting an example method 1100 of generating a regulated power supply, in accordance with an illustrative embodiment. Method 1100 may be performed using one or more of power supplies 400, 500, 600, 700, 800, 900, or 1000 described previously. Method 1100 includes coupling a voltage supply input to at least one of the one or more unregulated voltage converters (stage 1110). Method 1100 includes generating an output voltage across a first converter output terminal and a second converter output terminal with each of the unregulated voltage converters (stage 1120). Method 1100 includes taking an unregulated voltage bus from at least one of the unregulated voltage converters (stage 1130). Method 1100 includes providing an unregulated voltage bus to a voltage regulator (stage 1140). Method 1100 includes generating a regulated voltage across a first regulator output terminal and a second regulator output terminal with a voltage regulator (stage 1150). Method 1100 includes producing a regulated output voltage across a first power supply output terminal and a second power supply output terminal (stage 1160).

Method 1100 includes receiving a voltage supply input at least one of the one or more unregulated voltage converters (stage 1110). The voltage supply input may receive an input voltage, such as input voltage 410, 510, 610, 710, 810, 910, or 1010. The input voltage may be coupled to a switching block of the unregulated voltage converter, such as switching blocks 440, 540, 640, 740, 840, 940, or 1040. The switching block may comprise a capacitor or a tank circuit. Each switch block may have a first converter output terminal and a second converter output terminal.

Method 1100 includes generating an output voltage across a first converter output terminal and a second converter output terminal with each of the unregulated voltage converters (stage 1120). A Pulse Width Modulator (PWM), such as PWM132, 142, 232, or 242, may control switches in the switch block to convert a voltage across the first and second converter input terminals to a voltage across the first and second converter output terminals. The output voltage may vary with the input voltage.

Method 1100 includes taking an unregulated voltage bus from at least one of the unregulated voltage converters (stage 1130). An input voltage and an unregulated voltage bus, such as unregulated voltage bus 420, 520, 620, 720, 820, 920, or 1020, may be connected in series through the input side of the switch block. That is, the input voltage may be coupled to the first converter input terminal of the first switch block. The second converter input terminal of the first switching block may be connected to the first converter input terminal of the second switching block, and so on. The second converter input terminal of the last switching block may be connected to the unregulated voltage bus.

Method 1100 includes providing an unregulated voltage bus to a voltage regulator (stage 1140). The unregulated voltage bus may be connected to an input of one or more voltage regulators, such as voltage regulators 460, 560, 860, 960, or 1060.

Method 1100 includes generating a regulated voltage across a first regulator output terminal and a second regulator output terminal with a voltage regulator (stage 1150). The regulated voltage produced by the voltage regulator may be used to regulate the output of one or more of the unregulated voltage converters. The type of voltage regulator used may depend on the nominal regulated voltage and the expected voltage range that will occur on the unregulated voltage bus.

Method 1100 includes producing a regulated output voltage across a first power supply output terminal and a second power supply output terminal (stage 1160). The output terminals of the voltage regulator and the output terminals of the one or more unregulated voltage converters may be connected in parallel to provide power at a regulated voltage to the load. That is, the first power supply output terminal is connected to the first regulator output terminal and the first converter output terminal of at least one of the unregulated voltage converters, and the second power supply output terminal is connected to the second regulator output terminal and the second converter output terminal of the at least one unregulated voltage converter. By connecting these outputs in parallel, the voltage regulator need only provide enough power to regulate the output of the unregulated voltage converter and need not provide the full output power of the power supply. Thus, much power can be provided by a smaller, more efficient and less expensive unregulated converter than a voltage regulator. Thus, the power supply may be smaller, less expensive, and more efficient than a power supply having a two-stage cascaded configuration of an unregulated voltage converter and a voltage regulator.

In some embodiments, the method may include connecting the voltage regulator output terminals in parallel with output terminals of at least two unregulated voltage converters. That is, the first power supply output terminal may be connected to first converter output terminals of the at least two unregulated voltage converters, and the second power supply output terminal may be connected to second converter output terminals of the at least two unregulated voltage converters.

In some embodiments, the method may include providing an unregulated voltage bus to a second voltage regulator and generating a second regulated voltage. The method may include connecting an output terminal of the second voltage regulator in parallel with one or more additional unregulated voltage converters. The power supply can thus produce two different regulated output voltages.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features specific to particular implementations of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

References to "or" may be construed as inclusive such that any term described using "or" may refer to any single term, more than one term, and all terms described. The labels "first," "second," "third," etc. are not necessarily intended to be sequential, and are typically used merely to distinguish one item or element from another, which may be the same or similar.

Various modifications to the embodiments described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the claims are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with the invention, principles and novel features disclosed herein.