阅读说明：本技术 电容介质层表面处理方法及电容器 (Surface treatment method of capacitance dielectric layer and capacitor ) 是由 不公告发明人 于 2018-07-06 设计创作，主要内容包括：本发明提供了一种电容介质层表面处理方法和电容器,所述方法包括：提供一形成于基底上的电极支撑结构,电极支撑结构具有多个电容成型孔,电容成型孔的侧壁以及底面由下电极层构成；在下电极层的表面形成电容介质层,且电容介质层还覆盖电极支撑结构；对电容介质层进行氨气退火处理,以形成介质表面修复层在电容介质层的表面层,介质表面修复层的表面具有纳米微晶结构；在介质表面修复层的表面形成上电极层,且上电极层还覆盖在电极支撑结构上的介质表面修复层；上电极填充物填充在电容成型孔中,并且上电极填充物覆盖在电极支撑结构上的上电极层。改善电容介质层表面性质,降低电容器的漏电流,减少上电极板的阻值,改善电容器可靠性寿命。(The invention provides a surface treatment method of a capacitance dielectric layer and a capacitor, wherein the method comprises the following steps: providing an electrode supporting structure formed on a substrate, wherein the electrode supporting structure is provided with a plurality of capacitor forming holes, and the side walls and the bottom surfaces of the capacitor forming holes are formed by lower electrode layers; forming a capacitance dielectric layer on the surface of the lower electrode layer, wherein the capacitance dielectric layer also covers the electrode supporting structure; performing ammonia annealing treatment on the capacitance dielectric layer to form a dielectric surface repairing layer on the surface layer of the capacitance dielectric layer, wherein the surface of the dielectric surface repairing layer has a nano microcrystalline structure; forming an upper electrode layer on the surface of the dielectric surface repairing layer, wherein the upper electrode layer also covers the dielectric surface repairing layer on the electrode supporting structure; an upper electrode filler is filled in the capacitor forming hole, and the upper electrode filler covers the upper electrode layer on the electrode supporting structure. The surface property of the capacitor dielectric layer is improved, the leakage current of the capacitor is reduced, the resistance value of the upper electrode plate is reduced, and the reliability and the service life of the capacitor are improved.)

1. A surface treatment method for a capacitance dielectric layer is characterized by comprising the following steps:

providing an electrode supporting structure formed on a substrate, wherein the electrode supporting structure is provided with a plurality of capacitor forming holes, and the side walls and the bottom surfaces of the capacitor forming holes are formed by lower electrode layers;

forming a capacitance dielectric layer on the surface of the lower electrode layer, wherein the capacitance dielectric layer also covers the electrode supporting structure;

subjecting the capacitor dielectric layer to ammonia gas (NH)₃) Annealing treatment is carried out to form a medium surface repairing layer on the surface layer of the capacitor medium layer, wherein the surface of the medium surface repairing layer is provided with a nano microcrystalline structure;

forming an upper electrode layer on the surface of the dielectric surface repairing layer, wherein the upper electrode layer also covers the dielectric surface repairing layer on the electrode supporting structure; and

an upper electrode filler is filled in the capacitor forming hole, and the upper electrode filler covers the upper electrode layer on the electrode support structure.

2. The method according to claim 1, wherein the material of the capacitor dielectric layer comprises zirconia.

3. The surface treatment method for the capacitor dielectric layer according to claim 1, wherein in the ammonia annealing treatment, the capacitor dielectric layer forms a polycrystalline structure.

4. The method according to claim 3, wherein the polycrystalline structure of the capacitor dielectric layer comprises one of a tetragonal phase, a cubic phase, and an orthorhombic phase.

5. The method according to claim 1, wherein the material of the nanocrystalline structure comprises zirconium oxynitride.

6. The surface treatment method for the dielectric layer of claim 1, wherein the grain size range of the dielectric surface repair layer is between 2.5nm and 3.0 nm.

7. The method of claim 1, wherein the ammonia anneal is performed in one of a group consisting of Low Pressure Chemical Vapor Deposition (LPCVD), Sequential Flow Deposition (SFD), Advanced Sequential Flow Deposition (ASFD), and Atomic Layer Deposition (ALD).

8. The method according to claim 1, wherein the annealing temperature of the ammonia annealing is in a range of 330 to 550 ℃.

9. The method according to claim 8, wherein the annealing time of the ammonia annealing is in a range of 30s to 100 s.

10. The method for surface treatment of a capacitor dielectric layer according to claim 1, wherein the ratio of the thickness of the capacitor dielectric layer to the thickness of the dielectric surface repair layer is in the range of 10 to 20.

11. The method according to claim 1, wherein the step of forming the upper electrode fill comprises:

a first polycrystalline layer made of boron-doped silicon germanium is formed on the surface of the upper electrode layer, and the first polycrystalline layer fills the capacitor forming hole and covers the electrode supporting structure;

a second polycrystalline layer of a material comprising boron doped silicon is formed on a surface of the first polycrystalline layer.

12. The method for surface treatment of a capacitor dielectric layer as claimed in any one of claims 1 to 11, wherein the step after filling the capacitor forming holes with the upper electrode filler further comprises:

forming a metal conductive layer on the surface of the upper electrode filler;

and forming an oxide insulating layer on the surface of the metal conducting layer.

13. A capacitor, comprising:

a substrate;

an electrode support structure formed on the substrate, the electrode support structure having a plurality of capacitor forming holes;

the lower electrode layer is formed on the side wall and the bottom surface of the capacitor forming hole;

the capacitance dielectric layer is formed on the surface of the lower electrode layer;

the dielectric surface repairing layer is positioned on the surface layer of the capacitor dielectric layer, wherein the surface of the dielectric surface repairing layer has a nano microcrystalline structure; and

and the upper electrode comprises an upper electrode layer and an upper electrode filler, the upper electrode layer is formed on the surface of the dielectric surface repairing layer on the lower electrode layer, the capacitor forming hole is filled with the upper electrode filler, and the upper electrode layer and the upper electrode filler both cover the electrode supporting structure.

14. The capacitor of claim 13 wherein said capacitance medium layer comprises a zirconia layer.

15. The capacitor of claim 13 wherein said capacitance dielectric layer comprises a polycrystalline structure formed in said ammonia anneal process.

16. The capacitor of claim 15 wherein the polycrystalline structure of the capacitance dielectric layer further comprises one of a tetragonal phase, a cubic phase, and an orthorhombic phase.

17. The capacitor of claim 13, wherein the nanocrystalline structure comprises a zirconium oxynitride layer.

18. The capacitor of claim 13, wherein the grain size of the dielectric surface repair layer ranges from 2.5nm to 3.0 nm.

19. The capacitor of claim 13, wherein the surface of the capacitor dielectric layer is annealed at an annealing temperature in a range of 330 ℃ to 550 ℃.

20. The capacitor of claim 19, wherein the surface of the capacitance dielectric layer is annealed with the ammonia anneal for a time in a range of 30s to 100 s.

21. The capacitor of claim 13, wherein the ratio of the thickness of the capacitance dielectric layer to the thickness of the dielectric surface repair layer is in the range of 10 to 20.

22. The capacitor of claim 13, wherein the upper electrode fill includes a first polycrystalline layer formed on a surface of the upper electrode layer, the first polycrystalline layer filling the capacitor forming hole and covering the electrode support structure, and a second polycrystalline layer formed on a surface of the first polycrystalline layer.

23. The capacitor of claim 22, wherein the first polycrystalline layer comprises a boron doped silicon germanium layer and the second polycrystalline layer comprises a boron doped silicon layer.

24. The capacitor of any one of claims 13-23, further comprising:

a metal conductive layer formed on the surface of the upper electrode filler and an oxide insulating layer formed on the surface of the metal conductive layer.

Technical Field

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a surface treatment method of a capacitance dielectric layer and a capacitor.

Background

With the development of semiconductor integrated circuit manufacturing technology, the size of DRAM components is gradually reduced, and the high-dielectric constant material replaces the conventional gate insulating layer process of a silicon dioxide dielectric layer, so that the actual physical thickness of the dielectric layer can be increased while maintaining the same Equivalent Oxide Thickness (EOT), the electric field and the defect density in the gate insulating layer can be reduced, sufficient driving current can be maintained, the quantum tunneling effect can be effectively inhibited, and the leakage current can be reduced.

However, with the complexity and difficulty of the manufacturing process, the overall electrical property and surface property of the capacitor dielectric layer are greatly affected, which results in a large leakage current and affects the lifetime of the capacitor.

Disclosure of Invention

The present invention provides a method for surface treatment of a capacitive dielectric layer and a capacitor, which overcome or alleviate one or more of the problems of the background art, and at least provides a useful choice.

As one aspect of the present invention, there is provided a surface treatment method for a capacitor dielectric layer, comprising:

providing an electrode supporting structure formed on a substrate, wherein the electrode supporting structure is provided with a plurality of capacitor forming holes, and the side walls and the bottom surfaces of the capacitor forming holes are formed by lower electrode layers;

forming a capacitance dielectric layer on the surface of the lower electrode layer, wherein the capacitance dielectric layer also covers the electrode supporting structure;

ammonia gas (NH) is carried out on the surface of the capacitance dielectric layer₃) Annealing treatment is carried out to form a medium surface repairing layer on the surface layer of the capacitor medium layer, wherein the surface of the medium surface repairing layer is provided with a nano microcrystalline structure;

forming an upper electrode layer on the surface of the dielectric surface repairing layer, wherein the upper electrode layer also covers the dielectric surface repairing layer on the electrode supporting structure; and

an upper electrode filler is filled in the capacitor forming hole, and the upper electrode filler covers the upper electrode layer on the electrode support structure.

Preferably, in the surface treatment method of the capacitor dielectric layer, the material of the capacitor dielectric layer includes zirconia.

Preferably, in the above method for processing a surface of a capacitor dielectric layer, the capacitor dielectric layer is formed into a polycrystalline structure by the ammonia annealing.

Preferably, in the surface treatment method for the capacitor dielectric layer, the polycrystalline structure of the capacitor dielectric layer includes one of a tetragonal phase, a cubic phase and an orthorhombic phase.

Preferably, in the surface treatment method of a capacitor dielectric layer, the material of the nanocrystalline structure includes zirconium oxynitride.

Preferably, in the surface treatment method of the capacitor dielectric layer, the crystal grain size of the zirconium oxynitride ranges from 2.5nm to 3.0 nm.

Preferably, in the method for processing the surface of the capacitor dielectric layer, the ammonia annealing is performed in one of the processes selected from the group consisting of Low Pressure Chemical Vapor Deposition (LPCVD), Sequential Flow Deposition (SFD), Advanced Sequential Flow Deposition (ASFD) and Atomic Layer Deposition (ALD).

Preferably, in the surface treatment method of the capacitor dielectric layer, the annealing temperature range of the ammonia annealing treatment is between 330 ℃ and 550 ℃.

Preferably, in the surface treatment method of a capacitor dielectric layer, the annealing time of the ammonia annealing treatment is in a range of 30s to 100 s.

Preferably, in the capacitor dielectric layer surface treatment method, the ratio of the thickness of the capacitor dielectric layer to the thickness of the dielectric surface repair layer is in a range of 10 to 20.

Preferably, in the above method for processing a surface of a capacitor dielectric layer, the step of forming the upper electrode filler includes:

a first polycrystalline layer made of boron-doped silicon germanium is formed on the surface of the upper electrode layer, and the first polycrystalline layer fills the capacitor forming hole and covers the electrode supporting structure;

a second polycrystalline layer of a material comprising boron doped silicon is formed on a surface of the first polycrystalline layer.

Preferably, in the above method for processing a surface of a capacitor dielectric layer, the step after the upper electrode filler fills the capacitor forming hole further includes:

forming a metal conductive layer on the surface of the upper electrode filler;

and forming an oxide insulating layer on the surface of the metal conducting layer.

In another aspect, a capacitor is included, comprising:

a substrate;

an electrode support structure formed on the substrate, the electrode support structure having a plurality of capacitor forming holes;

the lower electrode layer is formed on the side wall and the bottom surface of the capacitor forming hole;

the capacitance dielectric layer is formed on the surface of the lower electrode layer;

the dielectric surface repairing layer is positioned on the surface layer of the capacitor dielectric layer, wherein the surface of the dielectric surface repairing layer has a nano microcrystalline structure; and

and the upper electrode comprises an upper electrode layer and an upper electrode filler, the upper electrode layer is formed on the surface of the dielectric surface repairing layer on the lower electrode layer, the capacitor forming hole is filled with the upper electrode filler, and the upper electrode layer and the upper electrode filler both cover the electrode supporting structure.

Preferably, in the capacitor described above, the capacitance medium layer includes a zirconium oxide layer.

Preferably, in the capacitor described above, the capacitance dielectric layer includes a polycrystalline structure formed in the ammonia annealing process.

Preferably, in the capacitor described above, the polycrystalline structure of the capacitance dielectric layer further includes one of a tetragonal phase, a cubic phase, and an orthorhombic phase.

Preferably, in the above capacitor, the nanocrystalline structure includes a zirconium oxynitride layer.

Preferably, in the capacitor, the grain size of the dielectric surface repair layer is in a range of 2.5nm to 3.0 nm.

Preferably, in the capacitor, the annealing temperature range of the ammonia annealing treatment on the surface of the capacitance dielectric layer is between 330 and 550 ℃.

Preferably, in the capacitor, the annealing time range for the ammonia annealing treatment on the surface of the capacitance dielectric layer is between 30s and 100 s.

Preferably, in the capacitor, the ratio of the thickness of the capacitance dielectric layer to the thickness of the dielectric surface repairing layer ranges from 10 to 20.

Preferably, in the capacitor described above, the upper electrode filler includes a first polycrystalline layer formed on a surface of the upper electrode layer, and a second polycrystalline layer formed on a surface of the first polycrystalline layer, the first polycrystalline layer filling the capacitor forming hole and covering the electrode supporting structure.

Preferably, in the capacitor described above, the first polycrystalline layer comprises a boron-doped silicon germanium layer, and the second polycrystalline layer comprises a boron-doped silicon layer.

Preferably, the capacitor further includes:

a metal conductive layer formed on the surface of the upper electrode filler and an oxide insulating layer formed on the surface of the metal conductive layer.

By adopting the technical scheme, the invention has the following advantages: and performing ammonia annealing treatment on the surface of the capacitance dielectric layer to form a dielectric surface repairing layer with a nano microcrystalline structure on the surface layer of the capacitance dielectric layer, so that the grain size of the surface of the capacitance dielectric layer is reduced, the surface property of the capacitance dielectric layer is further improved, the leakage current of the capacitor is reduced, the resistance value of an upper electrode plate can be reduced, and the reliability and the service life of the capacitor are greatly improved.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.

Fig. 1 is a flow chart of a method for processing a surface of a capacitor dielectric layer according to an embodiment of the invention.

Fig. 2 is a side view of an electrode supporting structure having a lower electrode layer formed in a capacitor forming hole according to an embodiment of the present invention.

Fig. 3 is a top view of an electrode supporting structure with a lower electrode layer formed in a capacitor forming hole according to an embodiment of the invention.

FIG. 4 is a side view of an electrode supporting structure with a capacitor dielectric layer formed on the inner and outer surfaces of the lower electrode layer according to an embodiment of the present invention.

Fig. 5 is a top view of an electrode supporting structure for forming a capacitor dielectric layer on the inner surface and the outer surface of the lower electrode layer according to an embodiment of the invention.

FIG. 6 is a side view of an electrode supporting structure with a mixture dielectric layer formed on the surface of a capacitor dielectric layer according to an embodiment of the invention.

Fig. 7 is a top view of an electrode supporting structure with a mixture dielectric layer formed on the surface of a capacitor dielectric layer according to an embodiment of the invention.

FIG. 8 is a side view of an electrode supporting structure having an upper electrode layer formed on a surface of a mixture dielectric layer according to an embodiment of the present invention.

Fig. 9 is a top view of an electrode supporting structure having an upper electrode layer formed on a surface of a mixture dielectric layer according to an embodiment of the invention.

Fig. 10 is a schematic diagram of a capacitor structure according to an embodiment of the invention.

FIG. 11(a) is a TEM image of the surface of the capacitor dielectric layer without any treatment provided by the prior art.

FIG. 11(b) is a TEM image of the surface of the dielectric layer of the mixture provided by the embodiment of the present invention.

FIG. 12(a) shows an AFM image of the surface of a capacitor dielectric layer without any treatment as provided in the prior art.

FIG. 12(b) shows an AFM image of the surface of the dielectric layer of the mixture according to the embodiment of the present invention.

FIG. 13 shows Ar and NH under different substrates provided by an embodiment of the present invention₃X-ray diffraction XRD pattern of annealing treatment.

Fig. 14 shows SIMS of secondary ion mass spectra of different TiN upper electrode layers according to an embodiment of the present invention.

FIG. 15 shows a capacitor dielectric layer of the same thickness and different NH thicknesses provided in accordance with an embodiment of the present invention₃Leakage current plot at anneal time.

FIG. 16 shows a capacitor dielectric layer of the same thickness and different NH thicknesses provided in accordance with an embodiment of the present invention₃TDDB electrical analysis of time dependent dielectric breakdown at annealing time.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.